CN115621277A - PWELL Isolated Gated Diode Triggered SCR Devices for ESD Protection - Google Patents

Abstract

The invention discloses a PWELL-isolated gate-controlled diode trigger SCR device for ESD protection, including: by adding a P+ injection region and a second N well on a conventional SCR and using a gate-controlled diode to assist triggering, a device with a gate-controlled diode is proposed. A technical solution with small voltage hysteresis and strong ESD robustness. On the one hand, the SCR device has an auxiliary trigger path of a gate-controlled diode, which can reduce the trigger voltage of the device and increase the current discharge capability; on the other hand, with the increase of ESD stress, the device is located in the SCR trigger path Turning on is beneficial to enhance the ESD current discharge capability of the device and improve the ESD robustness of the device, and the longer base width can increase the sustain voltage of the device, which is beneficial to improve the deep hysteresis problem existing in the ESD protection device.

Description

PWELL Isolated Gated Diode Triggered SCR Devices for ESD Protection

technical field

The invention belongs to the field of electrostatic discharge protection of integrated circuits, and in particular relates to a PWELL isolated gate control diode triggering SCR device for ESD protection.

Background technique

With the rapid development of the field of integrated circuits, the integration of integrated circuit (IC) chips is increasing day by day, the technological process of electronic products and related application materials are diversified, and the production links are gradually increasing. On the one hand, this makes the feature size of the IC manufacturing process shrink day by day, which improves the performance and power consumption of the chip. On the other hand, it also brings challenges to the reliability of the IC chip. ) protection design is facing increasingly severe challenges.

Different types of electrostatic discharge (ESD) models for ICs, ESD protection methods, ESD protection device design and related testing techniques have all been developed rapidly. Generally speaking, ESD protection devices need to meet the three conditions of transparency, effectiveness and robustness, that is, the protection device should be in the off state when the integrated circuit is working normally, and it should be turned on quickly to discharge the ESD current when the ESD pulse arrives. The device itself also needs to have some resistance to ESD pulses. From the electrical characteristics, it can be concluded that the trigger voltage of the ESD protection device is lower than the breakdown voltage of the protected device, and the maintenance voltage of the protection device is higher than the normal operating voltage of the chip. For safety reasons, there is usually 10%-15 % safety margin, and the secondary failure current of the protective device should be high enough.

At present, ESD protection devices commonly used in on-chip ICs mainly include diodes, MOS transistors, and thyristors (SCRs). Diodes have a simple structure and few parasitic effects, and are often used for ESD protection of low-voltage ICs, but the leakage current of the device is large; MOS tubes have good process compatibility, and are widely used in ESD protection of on-chip ICs, especially NMOS, because of their In the ESD protection, the overall performance is relatively compromised, and it is mostly used in the ESD protection of each IO port in the IC. The biggest disadvantage of MOS devices is that they have poor ESD robustness and occupy a large chip area.

Compared with diodes and MOS devices, SCR devices have enhanced ESD robustness while consuming the same chip area. However, since the SCR structure has the characteristics of deep hysteresis (high trigger voltage and low sustain voltage) under the action of ESD stress, it is prone to latch-up effect. Therefore, the traditional SCR structure generally cannot be directly used for ESD protection of on-chip ICs. It is usually necessary to adapt to the needs of the circuit after improving and optimizing the layout based on the traditional SCR structure according to the working requirements of different circuits.

Contents of the invention

In order to solve the low maintenance voltage problem of the traditional low trigger voltage SCR as an ESD protection device, the embodiment of the present invention provides a PWELL isolated gate-controlled diode trigger SCR device for ESD protection, making full use of the strong ESD robustness of the SCR structure , and by embedding a gate-controlled diode, the width of the base region of the triode in the parasitic SCR is increased, so that the device can form an auxiliary trigger path of the gate-controlled diode and an SCR trigger path located on the surface and buried layer under the action of the ESD pulse, and realize a ESD protection design scheme with low trigger, high sustain voltage and strong ESD robustness.

The PWELL isolated gate-controlled diode trigger SCR device for ESD protection provided by the embodiment includes a P substrate, and is characterized in that it also includes a first N well, a P well, and a second N well arranged on the surface of the P substrate, A first N+ implant region and a second P+ implant region respectively embedded in the first N well and the P well, straddling the first N well and the P well and an embedded first P+ implant region spanning The third P+ injection region embedded in the P well and the second N well is spaced apart from the second N+ injection region, the fourth P+ injection region, and the third N+ injection region embedded in the second N well;

The surface of the first N well and the first thin gate oxide layer and the first polysilicon gate layer covering it are provided between the first N+ implantation region and the first P+ implantation region, and the second On the surface of the N well, a second thin gate oxide layer and a second polysilicon gate covering it are provided between the third P+ implantation region and the second N+ implantation region;

A gate-controlled diode D2 is formed by the first N+ injection region, the first N well, the first thin gate oxide layer, the first polysilicon gate layer covering it, and the first P+ injection region;

A gate-controlled diode D1 is formed by the third P+ implantation region, the second N well, the second thin gate oxide layer, the second polysilicon gate covering it, and the second N+ implantation region;

A parasitic resistance Rn1 is formed by the second N well and the third N+ injection region, and a parasitic PNP transistor is formed by the fourth P+ injection region, the second N well, the P well and the P substrate Q1 is composed of the fourth P+ injection region, the second N well, and the third P+ injection region to form a parasitic PNP transistor Q2, and the second P+ injection region, the P well, and the third P+ The injection region forms a parasitic resistance Rp1, the second N well, the P well and the first N well form a parasitic NPN transistor Q3, the P substrate 101 forms a parasitic resistance Rp2, and the first N+ The injection region and the first N well form a parasitic resistance Rn2.

In an embodiment, on the surface of the P substrate, the left edge of the P substrate is connected to the left edge of the first N well, and the right side of the first N well is connected to the left edge of the P well. The right side of the P well is connected to the left side of the second N well, and the right side of the second N well is connected to the right edge of the P substrate.

In an embodiment, on the surface of the first N well, the left side of the first thin gate oxide layer and the first polysilicon gate layer covering it is connected to the right side of the first N+ implanted region, so The right side of the first thin gate oxide layer and the first polysilicon gate layer covering it is connected to the left side of the first P+ injection region.

In an embodiment, on the surface of the second N well, the left side of the second thin gate oxide layer and the second polysilicon gate covering it is connected to the right side of the third P+ implantation region, the The right side of the second thin gate oxide layer and the second polysilicon gate covering it is connected to the left side of the second N+ implantation region.

In an embodiment, when the SCR device is used for ESD protection, the circuit connection of the SCR device includes: the first N+ injection region is connected to the first metal, the first polysilicon gate is connected to the second metal, the The first P+ injection region is connected to the third metal, the second P+ injection region is connected to the fourth metal, the third P+ injection region is connected to the fifth metal, and the second polysilicon gate is connected to the sixth metal , the second metal, the third metal, the fifth metal and the sixth metal are all connected to the tenth metal, the first metal and the fourth metal are all connected to the ninth metal, from The ninth metal leads out the first electrode and is used as a metal cathode of the device;

The fourth P+ injection region is connected to the seventh metal, the third N+ injection region is connected to the eighth metal, and both the seventh metal and the eighth metal are connected to the eleventh metal. A metal leads out the second electrode, which is used as a metal anode of the device.

In the embodiment, when the forward ESD stress appears on the metal anode 2 of the device, the avalanche breakdown first occurs at the junction of the second N well and the third P+ injection region, and the reverse gate The diode D1 conducts immediately; then, the ESD current reaches the metal cathode through the reverse gate control diode D1 and the forward gate control diode D2, and the ESD current in the second N well will be in the floating The second N+ implantation region 109 gathers;

In addition, electrostatic discharge current will apply a voltage to the gate of the gated diode through the third P+ injection region connected across.

In an embodiment, when ESD occurs on the metal anode, the potential of the second N well increases; at a certain moment, the junction between the second N well and the third P+ injection region is Avalanche breakdown begins to occur due to the high electric field, and electron-hole pairs will be generated; then, the hole current flows into the P well through the parasitic PNP transistor Q1 and the parasitic PNP transistor Q2, which increases the P well the potential of the parasitic NPN transistor Q3; the emitter-base junction of the parasitic NPN transistor Q3 is forward biased by the potential of the P well, and is turned on; the current of the Q3 from the collector of the Q1 to the cathode is the Q1 A forward bias is provided; the voltage at the anode 213 no longer needs to provide a bias for the Q1.

In the embodiment, by adjusting the length of the P well, the length of the first P+ implantation region, the length of the third P+ implantation region, and the distance between the second P+ implantation region and the third P+ implantation region, the maintenance can be realized. Voltage tuning to meet different needs.

Compared with the prior art, the beneficial effects of the present invention at least include:

In the present invention, the first N+ implantation region, the first thin gate oxide layer and the first polysilicon gate layer covering it, the first P+ implantation region, the third P+ implantation region, The second polysilicon gate and the second thin gate oxide layer covered by it and the second N+ implantation region constitute two gate-controlled diodes, and due to the high concentration of the third P+ implantation region, it has a low trigger voltage, the parasitic resistance Rn2 is formed by the first N well and the first N+ injection region, and the parasitic resistance Rn2 is formed by the second thin gate oxide layer and the second polysilicon gate covering it and the second N well The formed parasitic capacitance and the parasitic resistance Rn2 can form a resistance-capacitance coupling trigger network, which reduces the trigger voltage of the device and increases the turn-on speed of the device.

In the present invention, the P substrate, the first N well, the P well, the second N well, the first N+ implant region, the second P+ implant region, the third The P+ implantation region, the fourth P+ implantation region, and the third N+ implantation region constitute an SCR path. A parasitic NPN transistor is formed by the second N well, the P well and the first N well, and a parasitic resistance Rp1 is formed by the second P+ injection region, the P well and the third P+ injection region, The parasitic resistance Rn2 and the parasitic resistance Rp1 and the P well as the base region of the parasitic NPN triode increase the sustain voltage of the device, and the SCR path can enhance the ESD robustness of the device.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic cross-sectional view of the structure of an SCR device provided by an embodiment of the present invention;

Fig. 2 is the circuit connection diagram that the SCR provided by the embodiment of the present invention is used for ESD protection;

Fig. 3 is the equivalent circuit diagram of the auxiliary trigger path of the SCR provided by the embodiment of the present invention under the action of ESD stress;

FIG. 4 is an equivalent circuit diagram of the SCR trigger path of the SCR device provided by the embodiment of the present invention under the action of ESD stress.

Fig. 5 is a comparison diagram of the structure of the SCR device provided by the embodiment of the present invention and the traditional low trigger voltage SCR;

Fig. 6 is a comparison chart of the test results of the SCR device provided by the embodiment of the present invention in forward electrostatic protection.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, and do not limit the protection scope of the present invention.

Aiming at the deep hysteresis problem of the traditional SCR structure in ESD protection, by adding P+ injection region and the second N-Well on the conventional SCR and using gate-controlled diodes to assist triggering, a new method with small voltage hysteresis amplitude and A technical solution with strong ESD robustness. On the one hand, the device has an auxiliary trigger path of gate-controlled diodes, which can reduce the trigger voltage of the device and increase the current discharge capability; on the other hand, as the ESD stress increases, the SCR trigger path between the surface and the substrate of the device is turned on. , which is conducive to enhancing the ESD current discharge capability of the device and improving the ESD robustness of the device, and the maintenance voltage of the device can be increased by adjusting the base width of the longer parasitic transistor, which is conducive to improving the deep hysteresis problem existing in the ESD protection device.

As shown in Figure 1, the internal structure sectional view of the SCR device provided by the embodiment of the present invention, as shown in Figure 1, the embodiment designs a gate-controlled diode triggering SCR device for PWELL isolation of ESD protection, including a gate-controlled The auxiliary trigger path of the diode and the SCR trigger path that adjusts the base width of the parasitic transistor on the surface and the substrate can reduce the trigger voltage of the ESD protection device, increase the maintenance voltage, and reduce the voltage hysteresis after the ESD protection device is turned on. Enhance the ESD robustness of the device, specifically including: P substrate (P-sub) 101, first N well (Nwell) 102, P well (Pwell) 103, second N well (Nwell) 104, first N+ implant Region 105, first P+ implant region 106, second P+ implant region 107, third P+ implant region 108, second N+ implant region 109, fourth P+ implant region 110, third N+ implant region 111, first thin gate oxide Layer 112 and a first polysilicon gate layer 113 covering it, a second thin gate oxide layer 114 and a second polysilicon gate layer 115 covering it.

The first N well 102, the P well 103 and the second N well 104 are sequentially arranged in the surface area of the P substrate 101 from left to right, and the left edge of the P substrate 101 is connected to the The left edge of the first N well 102 is connected, the right side of the first N well 102 is connected with the left side of the P well 103, and the right side of the P well 103 is connected with the second N well 104 The left side of the second N well 104 is connected to the right side of the P substrate 101 .

The first N+ implant region 105 and the second P+ implant region 107 are respectively embedded in the first N well 102 and the P well 103 from the surface, the second N+ implant region 109, the fourth P+ implant region The region 110 and the third N+ implant region 111 are embedded in the second N well 104 from the surface in a spaced manner. The first P+ implantation region 106 straddles and embeds the first N well 102 and the P well 103 . The third P+ implantation region 108 straddles and embeds the P well 103 and the second N well 104 .

The first thin gate oxide layer 112 and the first polysilicon gate layer 113 covering it are arranged on the surface of the first N well 102 and between the first N+ implantation region 105 and the first P+ implantation region 106, specifically the left side of the first thin gate oxide layer 112 and the first polysilicon gate layer 113 covering it is connected to the right side of the first N+ implantation region 105, and the first thin gate The right side of the oxide layer 112 and the first polysilicon gate layer 113 covering it is connected to the left side of the first P+ implantation region 106 .

The second thin gate oxide layer 114 and the second polysilicon gate 115 covering it are arranged on the surface of the second N well 104 and between the third P+ implantation region 108 and the second N+ implantation region 109 Specifically, the left side of the second thin gate oxide layer 114 and the second polysilicon gate 115 covering it is connected to the right side of the third P+ implantation region 108, and the second thin gate oxide layer 114 and the right side of the second polysilicon gate 115 covering it is connected to the left side of the second N+ implantation region 109 .

The lengths of the first thin gate oxide layer 112 and the first polysilicon gate layer 113 covering it and the second thin gate oxide layer 114 and the second polysilicon gate 115 covering it meet the requirements of the manufacturing process. Minimum feature size, the length of the P-well 103 is designed according to requirements, which can increase the base width of the parasitic NPN transistor and increase the sustain voltage of the device.

When the SCR device provided by the embodiment is used for ESD protection, as shown in FIG. 2 , the circuit connection of the SCR device includes: the first N+ injection region 105 is connected to the first metal 201, and the first polysilicon gate 113 is connected to the first metal 201. The second metal 202 is connected, the first P+ implantation region 106 is connected to the third metal 203, the second P+ implantation region 107 is connected to the fourth metal 204, and the third P+ implantation region 108 is connected to the fifth metal 205 , the second polysilicon gate 115 is connected to the sixth metal 206, the second metal 202, the third metal 203, the fifth metal 205 and the sixth metal 206 are all connected to the tenth metal 210 The first metal 201 and the fourth metal 204 are both connected to the ninth metal 209, and the first electrode 212 is drawn from the ninth metal 209, which is used as a metal cathode of the device.

The fourth P+ injection region 110 is connected to the seventh metal 207, the third N+ injection region 111 is connected to the eighth metal 208, and both the seventh metal 207 and the eighth metal 208 are connected to the eleventh metal 211 The second electrode 213 is drawn from the eleventh metal 211 and used as a metal anode of the device. It needs to be said that the same material is chosen for all metals.

FIG. 3 is an equivalent circuit diagram of an auxiliary trigger path of the SCR device provided by an embodiment of the present invention under the action of ESD stress. As shown in FIG. 3, the first N+ implantation region 105, the first N well 102, the first thin gate oxide layer 112 and the first polysilicon gate layer 113 covering it and the first A P+ implanted region 106 constitutes a gated diode D2. The gate is formed by the third P+ implantation region 108, the second N well 104, the second thin gate oxide layer 114, the second polysilicon gate 115 covering it, and the second N+ implantation region 109. control diode D1. The parasitic resistance Rn1 is formed by the second N well 104 and the third N+ injection region 111. When the forward ESD stress appears on the metal anode 213 of the device, avalanche breakdown first occurs in the second N well 104 and the third P+ injection region 108 junction, and the reverse gate control diode D1 is immediately turned on, because the third P+ injection region 108 has a higher concentration, so it has a lower trigger voltage. Then, the ESD current reaches the metal cathode 212 of the device through the reverse gate control diode D1 and the forward gate control diode D2, and the ESD current in the second N well 104 will flow in the floating second N well 104. The N+ implantation regions 109 are concentrated because the doping concentration of the floating second N+ implantation regions 109 is relatively high.

In addition, the electrostatic discharge current will apply a voltage to the gates of the gate-controlled diodes D1 and D2 through the connected third P+ injection region 108, which will improve the current discharge capability of the gate-controlled diode D1 on the one hand, And accelerate the conduction of the gate control diode D2. On the other hand, for the gate-controlled diode D1, the parasitic resistance formed by the gate capacitance and the second N+ injection region 109 and the second N well 104 forms a resistance-capacitance coupling trigger network, which reduces the trigger voltage of the device, Improve device turn-on speed. The increased gate voltage further enhances the gate coupling effect, thereby improving the current discharge capability of the gate control diode D1. For the gate-controlled diode D2, the first polysilicon layer 113 reduces the length of the current path of the gate-controlled diode D2, and achieves triggering with a lower voltage and faster response time under ESD stress. The gate voltage accelerates this process, therefore, the gate voltage accelerates the conduction of said gate diode D2. Once the gate control diode D2 is turned on, the auxiliary triggered diode path starts to discharge the ESD current, and when the voltage drop generated by the current on the parasitic resistor Rn1 reaches 0.7V, the SCR path is triggered to discharge the main ESD current.

FIG. 4 is an equivalent circuit diagram of the SCR trigger path of the SCR device provided by the embodiment of the present invention under the action of ESD stress. As shown in FIG. 4, the parasitic resistance Rn1 is formed by the second N well 104 and the third N+ injection region 111, and the parasitic resistance Rn1 is formed by the fourth P+ injection region 110, the second N well 104, the P well 103 and the P substrate 101 constitute a parasitic PNP transistor Q1, and the fourth P+ implantation region 110, the second N well 104, and the third P+ implantation region 108 constitute a parasitic PNP transistor Q2, and the fourth P+ implantation region 108 constitutes a parasitic PNP transistor Q2. Two P+ injection regions 107, the P well 103 and the third P+ injection region 108 form a parasitic resistance Rp1, and the second N well 104, the P well 103 and the first N well 102 form a parasitic NPN The triode Q3 is composed of the P substrate 101 to form a parasitic resistance Rp2, and the first N+ injection region 105 and the first N well 102 form a parasitic resistance Rn2.

When ESD occurs on the metal anode 213, the potential of the second N well 104 increases. At a certain moment, avalanche breakdown begins to occur at the junction of the second N well 104 and the third P+ injection region 108 due to the high electric field of the two regions, and electron-hole pairs will be generated. Then, the hole current flows into the P well 103 through the parasitic PNP transistor Q1 and the parasitic PNP transistor Q2 , which increases the potential of the P well 103 . The emitter-base junction of the parasitic NPN transistor Q3 is forward biased by the potential of the P well 103 and turned on. The Q3 current from the Q1 collector to the cathode provides forward bias for the Q1. The voltage at the anode 213 is no longer needed to bias the Q1. Therefore, whether the ESD current released by the diode path of the auxiliary trigger produces a voltage drop of 0.7V on the parasitic resistor Rn1, or the potential of the emitter-base junction of the parasitic NPN transistor Q3 passes through the P well 103. Any direction bias will trigger the SCR path to discharge the main ESD current, thus achieving lower trigger voltage and higher robustness.

In addition, since free carriers are injected from the emitter regions of the two PNP transistors Q1 and Q2, the holding voltage depends on the degree of space charge neutralization of the base regions of the NPN transistor Q3 and the PNP transistors Q1 and Q2 . Therefore, the lateral dimensions related to the base width of the triode and the Rn2 and Rp1 are very important. By adjusting the length of the P well 103, the length of the first P+ implantation region 106, the length of the third P+ implantation region 108, and the distance between the second P+ implantation region 107 and the third P+ implantation region 108 can be realized Keep tuning of the voltage to meet different needs.

Fig. 5 is a comparison diagram of the structure of the SCR device provided by the embodiment of the present invention and a traditional low trigger voltage SCR, and Fig. 6 is a comparison diagram of the test results of the SCR device provided by the embodiment of the present invention in forward electrostatic protection. It can be seen from Fig. 6 that when used for forward electrostatic pulse protection, the maintenance voltage (Voltage) of the traditional low trigger voltage SCR structure is about 3V, and the maintenance voltage of the SCR device provided in this embodiment is about 6V, which is different from that of the traditional SCR structure. Compared with that, the maintenance voltage of the SCR device provided by this embodiment has been significantly improved; the trigger voltage of the traditional low trigger voltage SCR is about 10V, and the trigger voltage of the SCR device provided by this embodiment is about 10V, which is similar to that of the traditional SCR structure. Compared with that, the trigger voltage of the SCR device provided in this embodiment is basically the same; at the same time, according to Figure 6, the failure current of the traditional low trigger voltage SCR device is about 2.6A, while the failure current of the SCR device provided in this embodiment is about 2.6A. A. Compared with the traditional low trigger voltage SCR structure, the failure current of the SCR device provided by this embodiment is basically the same; that is, when the trigger voltage and failure current are basically unchanged, the maintenance voltage of the SCR device provided by this embodiment is similar to Compared with the traditional low trigger voltage SCR structure, it has been significantly improved.

In a word, the SCR device provided by the above-mentioned embodiment uses gate-controlled diodes to reduce the trigger voltage of the device and increase the turn-on speed of the device; in addition, it also combines the advantages of the SCR structure with strong ESD robustness, and improves the SCR through the design of the structure. Sustain voltage; under the action of ESD stress, the SCR device provided by the embodiment can not only form an auxiliary trigger path composed of gate-controlled diodes to reduce the voltage hysteresis amplitude after the ESD protection device is turned on, but also form a high sustain voltage The SCR trigger path enhances the ESD robustness of the device.

The above-mentioned specific embodiments have described the technical solutions and beneficial effects of the present invention in detail. It should be understood that the above-mentioned are only the most preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, supplements and equivalent replacements made within the scope shall be included in the protection scope of the present invention.

Claims (8)

1. The gate-controlled diode-triggered SCR device comprises a P substrate, and is characterized by further comprising a first N well, a P well and a second N well which are arranged on the surface of the P substrate, a first N + injection region and a second P + injection region which are respectively embedded into the first N well and the P well, a first P + injection region which stretches across the first N well and the P well and is embedded into the first N well, a third P + injection region which stretches across the P well and the second N well and is embedded into the second N well, and a second N + injection region, a fourth P + injection region and a third N + injection region which are embedded into the second N well at intervals;

a first thin gate oxide layer and a first polycrystalline silicon gate layer covering the first thin gate oxide layer are arranged on the surface of the first N well and between the first N + injection region and the first P + injection region, and a second thin gate oxide layer and a second polycrystalline silicon gate covering the second thin gate oxide layer are arranged on the surface of the second N well and between the third P + injection region and the second N + injection region;

a gate control diode D2 is formed by the first N + injection region, the first N well, the first thin gate oxide layer, a first polycrystalline silicon gate layer covering the first thin gate oxide layer and the first P + injection region;

a gate-controlled diode D1 is formed by the third P + injection region, the second N well, the second thin gate oxide layer, the second polysilicon gate covering the second thin gate oxide layer and the second N + injection region;

the second N well and the third N + implantation region form a parasitic resistance Rn1, the fourth P + implantation region, the second N well, the P well and the P substrate form a parasitic PNP triode Q1, the fourth P + implantation region, the second N well and the third P + implantation region form a parasitic PNP triode Q2, the second P + implantation region, the P well and the third P + implantation region form a parasitic resistance Rp1, the second N well, the P well and the first N well form a parasitic NPN triode Q3, the P substrate forms a parasitic resistance Rp2, and the first N + implantation region and the first N well form a parasitic resistance Rn2.

2. The PWELL-isolated gated diode triggered SCR device for ESD protection of claim 1, wherein at the surface of the pbase, the left edge of the pbase is connected to the left edge of the first N-well, the right side of the first N-well is connected to the left side of the P-well, the right side of the P-well is connected to the left side of the second N-well, and the right side of the second N-well is connected to the right edge of the pbase.

3. The PWELL isolated gated diode triggered SCR device for ESD protection of claim 1, wherein the left side of the first thin gate oxide layer and the overlying first polysilicon gate layer is connected to the right side of the first N + implant region and the right side of the first thin gate oxide layer and the overlying first polysilicon gate layer is connected to the left side of the first P + implant region on the surface of the first N-well.

4. The PWELL-isolated gated diode triggered SCR device for ESD protection as claimed in claim 1, wherein the left side of the second thin gate oxide and the second polysilicon gate overlying it is connected to the right side of the third P + implant region and the right side of the second thin gate oxide and the second polysilicon gate overlying it is connected to the left side of the second N + implant region at the surface of the second N-well.

5. The PWELL isolated gated diode triggered SCR device for ESD protection as claimed in claim 1, wherein the circuit connection of the SCR device when the SCR device is used for ESD protection comprises: the first N + injection region is connected with a first metal, the first polysilicon gate is connected with a second metal, the first P + injection region is connected with a third metal, the second P + injection region is connected with a fourth metal, the third P + injection region is connected with a fifth metal, the second polysilicon gate is connected with a sixth metal, the second metal, the third metal, the fifth metal and the sixth metal are all connected with a tenth metal, the first metal and the fourth metal are all connected with a ninth metal, and a first electrode is led out from the ninth metal and used as a metal cathode of a device;

the fourth P + injection region is connected with a seventh metal, the third N + injection region is connected with an eighth metal, the seventh metal and the eighth metal are both connected with an eleventh metal, and a second electrode is led out from the eleventh metal and used as a metal anode of the device.

6. The PWELL-isolated gated diode triggered SCR device for ESD protection as recited in claim 1, wherein when forward ESD stress occurs at the metal anode 2 of the device, avalanche breakdown occurs first at the junction of the second N-well and the third P + implant region, and the reverse gated diode D1 is immediately turned on; then, the ESD current reaches the metal cathode through the reverse gated diode D1 and the forward gated diode D2, and the ESD current in the second N well will be collected in the second N + injection region 109 that is floating;

in addition, an electrostatic discharge current will apply a voltage to the gate of the gated diode through the third P + implant region that is bridged.

7. The PWELL-isolated gated diode triggered SCR device for ESD protection of claim 1, wherein the potential of the second N-well increases when ESD is present on the metal anode; at a certain moment, avalanche breakdown starts to occur at the junction of the second N well and the third P + injection region due to the high electric fields of the two regions, and electron-hole pairs are generated; then, a hole current flows into the P-well through the parasitic PNP transistor Q1 and the parasitic PNP transistor Q2, which increases the potential of the P-well; an emitter-base junction of the parasitic NPN triode Q3 is positively biased through the potential of the P trap and is conducted; the current of Q3 from the collector of Q1 to the cathode provides a forward bias for Q1; the voltage at the anode 213 no longer needs to provide a bias for the Q1.

8. The PWELL isolated gated diode triggered SCR device for ESD protection of claim 1, wherein tuning of a holding voltage to meet different requirements can be achieved by adjusting the length of the P-well, the first P + implant region, the third P + implant region length, and the distance of the second P + implant region from the third P + implant region.

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