CN115602711A - A kind of diode device applied to HEMT, preparation method and HEMT - Google Patents

Abstract

The application belongs to the technical field of semiconductors and provides a diode device applied to an HEMT, a preparation method and the HEMT, wherein the diode device comprises: the device comprises a semiconductor substrate, a first channel layer, a first barrier layer, a plurality of second channel layers, a plurality of second barrier layers, a cap layer, an anode electrode layer, a cathode electrode layer and an insulating medium layer; the plurality of second channel layers and the plurality of second barrier layers are alternately arranged on the first barrier layer in a stacking mode, so that a step structure is formed on the first side of the first barrier layer, the anode electrode layer covering the step structure and the cap layer is arranged on the first side of the first barrier layer, the cathode electrode layer is arranged on the second side of the first barrier layer, and the insulating medium layer is arranged between the anode electrode layer and the cathode electrode layer, so that a capacitor between an anode and a cathode has a higher uniform electric field, the electric field can be improved from the transverse direction and the longitudinal direction to improve the breakdown voltage of the parasitic diode, and the problem that the HEMT device is unstable in a high-sensitivity application scene due to the lack of the body diode is solved.

Description

A kind of diode device applied to HEMT, preparation method and HEMT

technical field

The application belongs to the technical field of semiconductors, and in particular relates to a diode device applied to HEMT, a preparation method and HEMT.

Background technique

As a representative of the third-generation semiconductor material, gallium nitride (GaN) has many excellent characteristics, such as high critical breakdown electric field, high electron mobility, high two-dimensional electron gas concentration, and good high temperature working ability.

However, compared with silicon-based metal-oxide-semiconductor field-effect transistors (Si-MOSFETs), gallium nitride-based high electron mobility transistors (High Electron Mobility Transistor, HEMT) devices do not have body diodes, and in high-inductance application scenarios The resulting reverse current will increase the gate voltage of the device, resulting in damage to the device.

Contents of the invention

In order to solve the above technical problems, the embodiment of the present application provides a diode device, a preparation method and a HEMT applied to HEMT, aiming to solve the problem that the reverse current generated by HEMT in the application scenario of high inductance in the prior art will make the device The gate voltage rises, causing the problem of device damage.

The first aspect of the embodiment of the present application provides a diode device applied to HEMT, and the diode device includes:

semiconductor substrate;

a first channel layer disposed on the semiconductor substrate;

a first barrier layer disposed on the first channel layer;

A plurality of second channel layers and a plurality of second barrier layers, wherein the plurality of second channel layers and the plurality of second barrier layers are alternately stacked and arranged on the first barrier layer , the second channel layer at the bottom is disposed on the first barrier layer, and the widths of the plurality of second channel layers and the plurality of second barrier layers are sequentially reduced, so that The first sides of each of the second channel layers and the plurality of second barrier layers form a ladder structure;

a capping layer disposed on top of the second barrier layer;

an anode electrode layer disposed on the stepped structure and the capping layer;

a cathode electrode layer disposed on the first channel layer and disposed on the second side of the plurality of second channel layers and the plurality of second barrier layers;

an insulating medium layer, disposed on the second barrier layer at the top, and located between the anode electrode layer and the cathode electrode layer and between the capping layer and the cathode electrode layer; wherein, the The anode electrode layer and the cathode electrode layer are respectively connected to the source and drain of the HEMT.

In one embodiment, the second sides of the plurality of second channel layers and the plurality of second barrier layers are flush with the second sides of the first barrier layers.

In one embodiment, the cathode electrode layer is also disposed on the second side of the first barrier layer and penetrates deep into the first channel layer.

In one embodiment, the difference between the width of the second potential barrier layer and the width of the second channel layer on the back side of the second potential barrier layer is equal to the difference between the second potential barrier layer and the The difference between the widths of the second channel layer on the front side of the second barrier layer.

In one embodiment, the upper surface of the insulating dielectric layer is flush with the upper surface of the anode electrode layer.

In one embodiment, the second channel layer has the same thickness as the second barrier layer.

In one embodiment, the insulating dielectric layer is a high dielectric material.

The second aspect of the embodiment of the present application also provides a method for preparing a diode device applied to a HEMT, including:

sequentially forming a first channel layer and a first barrier layer on a semiconductor substrate;

A plurality of second channel layers and a plurality of second barrier layers alternately stacked on the first barrier layer; wherein, the second channel layer at the bottom is arranged on the first barrier layer , and the widths of the plurality of the second channel layers and the plurality of the second barrier layers are sequentially reduced, so that the widths of the plurality of the second channel layers and the plurality of the second barrier layers The first side forms a stepped structure;

forming a capping layer on top of said second barrier layer;

forming an anode electrode layer on the stepped structure and the capping layer;

A cathode electrode layer is formed on the first channel layer; wherein, the cathode electrode layer is disposed on the second side of the plurality of second channel layers and the plurality of second barrier layers;

An insulating dielectric layer is formed on the top second barrier layer, and the insulating dielectric layer is located between the anode electrode layer and the cathode electrode layer and between the capping layer and the cathode electrode layer.

The third aspect of the embodiments of the present application also provides a HEMT, wherein the HEMT integrates the diode device according to any one of the above embodiments; or includes the diode device prepared by the above-mentioned preparation method.

In one embodiment, the diode device applied to HEMT is arranged under the gate, drain or source of the HEMT, and the anode electrode layer is connected to the source of the HEMT, and the cathode electrode layer connected to the drain of the HEMT.

Compared with the prior art, the embodiment of the present application has the beneficial effect that: by alternately stacking a plurality of second channel layers and a plurality of second barrier layers on the first barrier layer, The side forms a ladder structure, and an anode electrode layer covering the ladder structure and the cap layer is set on the first side, a cathode electrode layer is set on the second side, and an insulating medium layer is set between the anode electrode layer and the cathode electrode layer, so that the anode The capacitance between the cathode and the cathode has a higher uniform electric field, and at the same time, the electric field can be improved from the horizontal and vertical directions to increase the breakdown voltage of the parasitic diode, which solves the problem of instability in high-inductance application scenarios caused by the lack of body diodes in HEMT devices.

Description of drawings

FIG. 1 is a schematic diagram of a vertical section structure of a gallium nitride-based diode device provided by an embodiment of the present application;

Fig. 2 is a schematic flow chart of a method for preparing a gallium nitride-based diode device provided by an embodiment of the present application;

FIG. 3 is a schematic structural diagram of sequentially forming a first channel layer 210 and a first barrier layer 220 on a semiconductor substrate 100 according to an embodiment of the present application;

FIG. 4 is a schematic structural diagram of forming a second channel layer 310 provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram for forming a second mask layer 202 provided by an embodiment of the present application;

FIG. 6 is a schematic structural diagram after forming a second barrier layer 320 provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram after forming a multilayer second channel layer 310 and a second barrier layer 320 provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of forming a capping layer 600 provided by an embodiment of the present application;

FIG. 9 is a schematic structural diagram for forming an anode electrode layer 520 provided by an embodiment of the present application.

detailed description

In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

It should be noted that when an element is referred to as being “fixed” or “disposed on” another element, it may be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

It is to be understood that the terms "length", "width", "top", "bottom", "front", "rear", "left", "right", "vertical", "horizontal", "top" , "bottom", "inner", "outer" and other indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the application and simplifying the description, rather than indicating or implying the referred device Or elements must have a certain orientation, be constructed and operate in a certain orientation, and thus should not be construed as limiting the application.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present application, "plurality" means one or more than one, unless otherwise specifically defined.

Reference to "one embodiment," "some embodiments," or "an embodiment" in the specification of this application means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. . Thus, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in other embodiments," "in some In a particular embodiment", "in a particular application", etc. do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments" unless specifically emphasized otherwise. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.

As a representative of the third-generation semiconductor materials, gallium nitride (GaN) has many excellent characteristics, such as high critical breakdown electric field, high electron mobility, high two-dimensional electron gas concentration, and good high temperature working ability. Gallium nitride-based third-generation semiconductor devices, such as high electron mobility transistors (HEMTs) and heterostructure field effect transistors (HFETs), have been applied, especially in fields requiring high power and high frequency such as radio frequency and microwave has obvious advantages.

Compared with MOSFETs, GaN HEMTs have no body diode. In high inductance applications, the reverse current will increase the gate voltage of the device and cause device damage.

In order to solve the above technical problems, the embodiment of the present application provides a diode device applied to HEMT, the diode device can be integrated in the HEMT, for example, in the interdigitated HEMT device, the drain, source or gate are all A large amount of space is reserved, and the diode device in this embodiment can be integrated in the space under the drain, source or gate of the device by using the same gallium nitride process, so as to prevent the wrong opening of the gate of the device under high inductance , the device is damaged.

In one embodiment, as shown in FIG. 1 , the diode device in this embodiment includes: a semiconductor substrate 100, a first channel layer 210, a first barrier layer 220, a plurality of second channel layers 310, a plurality of a second barrier layer 320 , a capping layer 600 , an anode electrode layer 520 , a cathode electrode layer 510 , and an insulating dielectric layer 400 .

In this embodiment, the first channel layer 210 is disposed on the semiconductor substrate 100, the first barrier layer 220 is disposed on the first channel layer 220; the plurality of second channel layers 310 and the plurality of second potential barrier layers The barrier layers 320 are alternately stacked on the first barrier layer 220, the second channel layer 310 at the bottom is provided on the first barrier layer 220, and the plurality of second channel layers 310 and the plurality of second barrier layers The layers 320 are sequentially reduced to form a stepped structure on the first sides of the plurality of second channel layers 310 and the plurality of second barrier layers 320 .

The capping layer 600 is disposed on the top second barrier layer 320; the anode electrode layer 520 covers the ladder structure and the capping layer 600; the cathode electrode layer 510 is disposed on the first channel layer 210, and is disposed on a plurality of second channel layers. The second side of the channel layer 310 and a plurality of second barrier layers 320; the insulating dielectric layer 400 is disposed on the top second barrier layer 320, and is located between the anode electrode layer 520 and the cathode electrode layer 510 and the capping layer 600 and the cathode electrode layer 510; wherein, the anode electrode layer 520 and the cathode electrode layer 510 are respectively connected to the source and drain of the HEMT.

In this embodiment, since a plurality of channel layers and a plurality of barrier layers are provided in the diode device, and the channel layers and the barrier layers are alternately stacked, there are a plurality of two-dimensional electron gas channels in the diode device. Under bias, multiple two-dimensional electron gas channels below that are depleted by the cap layer (the cap layer can be P-type gallium nitride) are reopened to form a multi-channel two-dimensional electron gas, reducing the on-resistance of the device; Under reverse bias, multiple field plates at the anode electrode layer form a stepped structure, respectively reducing the electric field peaks at the lower anode electrode layer, and at the same time, due to the depletion effect of the capping layer on the lower two-dimensional electron gas, the device can be improved The effect of the surface electric field.

In one embodiment, the insulating medium layer 400 between the anode electrode layer 520 and the cathode electrode layer 510 is a high dielectric material, since the capacitance formed between the anode electrode layer 520-the insulating medium layer 400-the cathode electrode layer 510 has a higher The high uniform electric field can also adjust the electric field under the insulating dielectric layer 400, thereby improving the electric field inside the device in both the horizontal and vertical directions inside the device, and greatly improving the withstand voltage of the device.

In one embodiment, the insulating dielectric layer 400 may be lanthanum oxide or silicon oxide.

In one embodiment, the first channel layer 210 and the second channel layer 310 may be N-type GaN layers.

In one embodiment, the first barrier layer 220 and the second barrier layer 320 may be AlGaN layers.

In one embodiment, as shown in FIG. 1 , the cathode electrode layer 510 is located on the second side of the first barrier layer 220 , the second channel layer 310 , and the second barrier layer 320 , and the first side of the cathode electrode layer 510 The side edges are flush with the second side edges of the first barrier layer 220, the second channel layer 310, and the second barrier layer 320, and the first barrier layer 220, the second channel layer 310, and the second barrier layer The distance between the first side edge of 320 and the cathode electrode layer 510 gradually decreases.

In one embodiment, a plurality of second channel layers 310 and a plurality of second barrier layers 320 are stacked alternately, and the distance between the left edge position and the cathode electrode layer 510 decreases layer by layer from the bottom to the top. , at this time a plurality of second channel layers 310 and a plurality of second barrier layers 320 form a ladder structure, since the anode electrode layer 510 covers the ladder structure, the anode electrode layer 510 may be composed of multilayer electrode field plates, Under reverse bias, the multilayer electrode field plates of the anode electrode layer 510 respectively reduce the electric field spikes at the lower anode, thereby adjusting the electric field in its direction.

In one embodiment, the cathode electrode layer 510 has a rectangular structure.

In one embodiment, being flush with the first side edge of the first channel layer 210 , the second side edge of the first barrier layer 220 is flush with the second side edge of the first channel layer 210 .

In one embodiment, the second sides of the plurality of second channel layers 310 and the plurality of second barrier layers 320 are flush with the second side of the first barrier layer 220 .

In one embodiment, the cathode electrode layer 510 is also disposed on the second side of the first barrier layer 220 and penetrates deep into the first channel layer 210 .

In this embodiment, the depth of the cathode electrode layer 510 deep into the first channel layer 210 is smaller than the thickness of the first barrier layer 220 .

In one embodiment, the distances between the first barrier layer 220 , the second channel layer 310 , the first side edge of the second barrier layer 320 and the cathode electrode layer 510 are arranged in an arithmetic progression.

In one embodiment, the difference between the width of the second barrier layer 320 and the width of the second channel layer 310 on the back side of the second barrier layer 320 is equal to the difference between the second barrier layer 320 and the second barrier layer 320 The difference between the widths of the second channel layer 310 on the front side.

In one embodiment, the upper surface of the insulating dielectric layer 400 is flush with the upper surface of the anode electrode layer 520 .

In one embodiment, the second channel layer 310 has the same thickness as the second barrier layer 320 .

In one embodiment, the number of the second channel layer 310 can be 2, the number of the second barrier layer 320 can be 2, the first barrier layer 220, the first channel layer 310, the second The barrier layer 320, the first channel layer 310, and the second barrier layer 320 are sequentially stacked on the first channel layer 210, and the first barrier layer 220, the first channel layer 310, and the second barrier layer 320 , the widths of the first channel layer 310 and the second barrier layer 320 decrease layer by layer, as shown in FIG. 1 .

The embodiment of the present application also provides a method for manufacturing a diode device applied to a HEMT, as shown in FIG. 2 , the method in this embodiment includes steps S10 to S60.

In step S10 , as shown in FIG. 3 , a first channel layer 210 and a first barrier layer 220 are sequentially formed on the semiconductor substrate 100 .

In this embodiment, the first channel layer 210 and the first barrier layer 220 have the same width, and the first channel layer 210 can be formed on the surface of the semiconductor substrate 100 by depositing a channel material, and then again The manner of depositing the material of the barrier layer forms the first barrier layer 220 on the surface of the first channel layer 210 .

In one embodiment, the thickness of the first channel layer 210 is greater than the thickness of the first barrier layer 220 .

In one embodiment, the thickness of the first channel layer 210 is three times the thickness of the first barrier layer 220 .

In one embodiment, the first channel layer 210 may be an N-type gallium nitride layer.

In one embodiment, the first barrier layer 220 may be an AlGaN layer.

In step S20 , as shown in FIG. 3 to FIG. 7 , a plurality of second channel layers 310 and a plurality of second barrier layers 320 alternately stacked on the first barrier layer 220 are formed.

In this embodiment, the second channel layer 310 at the bottom is disposed on the first barrier layer 220, and the widths of the plurality of second channel layers 310 and the plurality of second barrier layers 320 are sequentially reduced, so that First sides of the plurality of second channel layers 310 and the plurality of second barrier layers 320 form a stepped structure.

In one embodiment, in step S20 , forming a plurality of second channel layers 310 and a plurality of second barrier layers 320 alternately stacked on the first barrier layer 220 may specifically include steps S21 to S24 .

In step S21, as shown in FIG. 3, a first mask layer 201 is formed on the first barrier layer 220. The first mask layer 201 is located in the central area of the surface of the first barrier layer 220. The first mask The distance between the left edge of layer 201 and the left edge of first barrier layer 220 is equal to the distance between the right edge of first mask layer 201 and the right edge of first barrier layer 220 .

In one embodiment, the first mask layer 201 can be formed on the surface of the first barrier layer 220 by depositing silicon nitride material, and the silicon nitride material can be etched using a photomask or photoresist to make the first mask layer 201 Located in the central area of the surface of the first barrier layer 220 .

In step S22, as shown in FIG. 4 , the channel layer material is deposited to form the second channel layer 310 on the surface of the first barrier layer 220, and the second channel layer 310 is treated by chemical mechanical polishing, so that the second The thickness of the channel layer 310 is equal to the thickness of the first mask layer 201 .

Since the first mask layer 201 is located in the central region of the surface of the first barrier layer 220, the second channel layer 310 is provided on both sides of the first mask layer 201 at this time, and the second channel layer 310 on both sides of the first mask layer 201 The widths of the two channel layers 310 are equal.

In one embodiment, a gallium nitride layer may be formed on the surface of the first barrier layer 220 as the second channel layer 310 by depositing gallium nitride material.

In step S23, as shown in FIG. 5, a second mask layer 202 is formed on the surfaces of the first mask layer 201 and the second channel layer 310, and the second mask layer 202 is located on the first mask layer 201. , and the width of the second mask layer 202 is greater than the width of the first mask layer 201, the distance between the left edge of the second mask layer 202 and the left edge of the first mask layer 201 is equal to the second mask The distance between the right edge of layer 202 and the right edge of first mask layer 201 .

The distance between the left edge of the second mask layer 202 and the left edge of the first barrier layer 220 is equal to the distance between the right edge of the second mask layer 202 and the right edge of the first barrier layer 220. distance.

In one embodiment, the second mask layer 202 can be formed on the surface of the first mask layer 201 by depositing silicon nitride material, and the silicon nitride material is etched using a photomask or photoresist so that the second mask layer 202 The width is greater than the width of the first mask layer 201, and the distance between the left edge of the second mask layer 202 and the left edge of the first mask layer 201 is equal to the distance between the right edge of the second mask layer 202 and the first mask layer 202. A distance between the right edges of the mask layer 201 .

In step S24, as shown in FIG. 6, channel layer material is deposited to form a second barrier layer 320 on the surface of the second channel layer 310, and the second barrier layer 320 is treated by chemical mechanical polishing, so that the second The thickness of the barrier layer 320 is equal to the thickness of the second mask layer 202 .

The second mask layer 202 is located on the first mask layer 201, the second barrier layer 320 is provided on both sides of the second mask layer 202, and the second barrier layer 320 on both sides of the second mask layer 202 equal in width.

In one embodiment, an aluminum gallium nitride layer may be formed on the surface of the second channel layer 310 by depositing aluminum gallium nitride material as the second barrier layer 320 .

As shown in FIG. 7 , repeat the above step S21 to step S24, form the third mask layer 203 on the second mask layer 202 and then form the second channel layer 310 on the top, and then form the second channel layer 310 on the third mask layer 204. The fourth mask layer 205 forms the second barrier layer 320 on top.

In a specific application, the number of layers of the second channel layer 310 and the second barrier layer 320 is determined by the number of repetitions from step S21 to step S24, and the width of each subsequent mask layer is greater than that of the previous layer. The width of the layers is such that the alternately stacked second channel layers 310 and second barrier layers 320 form a ladder structure.

In one embodiment, the number of the second channel layer 310 can be 2, the number of the second barrier layer 320 can be 2, the first barrier layer 220, the first channel layer 310, the second The barrier layer 320, the first channel layer 310, and the second barrier layer 320 are sequentially stacked on the first channel layer 210, and the first barrier layer 220, the first channel layer 310, and the second barrier layer 320 , the widths of the first channel layer 310 and the second barrier layer 320 decrease layer by layer, as shown in FIG. 1 .

In one embodiment, the second channel layer 310 may be an N-type gallium nitride layer.

In one embodiment, the second barrier layer 320 may be an AlGaN layer.

In step S30 , as shown in FIG. 8 , a capping layer 600 is formed on the top second barrier layer 320 .

In this embodiment, the multi-layer mask layer in step S20 is removed, and then the barrier layer and channel layer formed in step S20 are cut and formed as shown in FIG. The barrier layer and the channel layer of the ladder structure.

A P-type GaN layer is formed by depositing a P-type GaN material on the top second barrier layer 320, and the P-type GaN layer is etched to remove part of the second side of the P-type GaN layer. P-type GaN material to form a capping layer 600 , the edge of the first side of the capping layer 600 is aligned with the edge of the first side of the second barrier layer 320 on top.

In step S40 , as shown in FIG. 9 , an anode electrode layer 520 is formed on the ladder structure and the capping layer 600 .

In this embodiment, the anode electrode layer 520 covers the stepped structure and the capping layer 600. Since the back of the anode electrode layer 520 matches the stepped structure, the back of the anode electrode layer 520 also has a stepped structure, and the anode electrode layer 520 can be equivalent to Multi-layer electrode field plates, each layer of electrode field plates corresponds to the second channel layer 310 or the second barrier layer 320 .

In one embodiment, the first side edge of the anode electrode layer 520 is flush with the first side edge of the first barrier layer 220, and the second side edge of the anode electrode layer 520 is flush with the second side edge of the capping layer 600. , the first side and the second side are opposite.

In step S50 , a cathode electrode layer 510 is formed on the first channel layer 210 .

In this embodiment, the cathode electrode layer 510 is disposed on the second side of the plurality of second channel layers 310 and the plurality of second barrier layers 320, between the edge of the first side of the cathode electrode layer 510 and the anode electrode layer 520 The distance is greater than the width of the cathode electrode layer 510 .

In one embodiment, the cathode electrode layer 510 is also disposed on the second side of the first barrier layer 220 and penetrates deep into the first channel layer 210 .

In this embodiment, the depth of the cathode electrode layer 510 deep into the first channel layer 210 is smaller than the thickness of the first barrier layer 220 .

In one embodiment, the distances between the first barrier layer 220 , the second channel layer 310 , the first side edge of the second barrier layer 320 and the cathode electrode layer 510 are arranged in an arithmetic progression.

In one embodiment, the difference between the width of the second barrier layer 320 and the width of the second channel layer 310 on the back side of the second barrier layer 320 is equal to the difference between the second barrier layer 320 and the second barrier layer 320 The difference between the widths of the second channel layer 310 on the front side.

In step S60, as shown in FIG. 1, an insulating dielectric layer 400 is formed on the top second barrier layer 320, and the insulating dielectric layer 400 is located between the anode electrode layer 520 and the cathode electrode layer 510 and between the cap layer 600 and the cathode electrode layer. between layers 510 .

In one embodiment, the upper surface of the insulating dielectric layer 400 is flush with the upper surface of the anode electrode layer 520 .

In one embodiment, a plurality of second channel layers 310 and a plurality of second barrier layers 320 are alternately stacked, and the distance between the left edge position and the cathode electrode layer 510 decreases layer by layer from the bottom to the top. , at this time a plurality of second channel layers 310 and a plurality of second barrier layers 320 form a stepped structure, and since the anode electrode layer 510 covers the stepped structure, the anode electrode layer 510 may be composed of a multilayer electrode field plate, Under reverse bias, the multilayer electrode field plates of the anode electrode layer 510 respectively reduce the electric field spikes at the lower anode, thereby adjusting the electric field in its direction.

In this embodiment, since a plurality of channel layers and a plurality of barrier layers are arranged in the diode device, and the channel layers and the barrier layers are alternately stacked, there are a plurality of two-dimensional electron gas channels in the diode device. Under bias, multiple two-dimensional electron gas channels below that are depleted by the cap layer (the cap layer can be P-type gallium nitride) are reopened to form multi-channel two-dimensional electron gas, reducing the on-resistance of the device; Under reverse bias, multiple field plates at the anode electrode layer form a stepped structure, respectively reducing the electric field peaks at the lower anode electrode layer, and at the same time due to the depletion effect of the capping layer on the lower two-dimensional electron gas, the device can be improved The effect of the surface electric field.

In one embodiment, the insulating medium layer 400 between the anode electrode layer 520 and the cathode electrode layer 510 is a high dielectric material, since the capacitance formed between the anode electrode layer 520-the insulating medium layer 400-the cathode electrode layer 510 has a higher The high uniform electric field can also adjust the electric field under the insulating dielectric layer 400, thereby improving the electric field inside the device in both the horizontal and vertical directions inside the device, and greatly improving the withstand voltage of the device.

In one embodiment, the insulating dielectric layer 400 may be lanthanum oxide or silicon oxide.

The embodiment of the present application also provides a gallium nitride HEMT, wherein the gallium nitride-based diode device as described in any one of the foregoing embodiments is integrated in the gallium nitride HEMT.

The embodiment of the present application also provides a gallium nitride HEMT, wherein the gallium nitride-based diode device prepared by the preparation method described in the above embodiment is integrated in the gallium nitride HEMT.

In a specific application, the gallium nitride-based diode device in the above embodiment shares the channel layer, the barrier layer and the semiconductor substrate with the gallium nitride HEMT.

In one embodiment, the gallium nitride-based diode device is disposed under the gate, drain or source of the gallium nitride HEMT, and the anode electrode layer is connected to the source of the gallium nitride HEMT, and the cathode electrode layer is connected to the gallium nitride HEMT. HEMT drain connection.

Compared with the prior art, the embodiment of the present application has the beneficial effect that: by alternately stacking a plurality of second channel layers and a plurality of second barrier layers on the first barrier layer, The side forms a ladder structure, and an anode electrode layer covering the ladder structure and the cap layer is set on the first side, a cathode electrode layer is set on the second side, and an insulating medium layer is set between the anode electrode layer and the cathode electrode layer, so that the anode The capacitance between the cathode and the cathode has a higher uniform electric field, and at the same time, the electric field can be improved from the horizontal and vertical directions to increase the breakdown voltage of the parasitic diode, which solves the problem of instability in high-inductance application scenarios caused by the lack of body diodes in HEMT devices.

Those skilled in the art can clearly understand that for the convenience and brevity of description, only the division of the above-mentioned doped regions is used as an example. In practical applications, the above-mentioned functional regions can be assigned to different doped regions according to needs. Completion means that the internal structure of the device is divided into different doped regions, so as to complete all or part of the functions described above.

Each doped region in the embodiment can be integrated in one functional region, or each doped region can exist separately physically, or two or more doped regions can be integrated in one functional region. The above-mentioned integrated functional region It can be realized by using the same kind of dopant ions, and can also be realized by using multiple dopant ions together. In addition, the specific names of the doped regions are only for the convenience of distinguishing each other, and are not used to limit the protection scope of the present application. For the specific working process of the medium-doped region in the above-mentioned device manufacturing method, reference may be made to the corresponding process in the foregoing method embodiments, and details will not be repeated here.

The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still implement the foregoing embodiments Modifications to the technical solutions described in the examples, or equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the application, and should be included in the Within the protection scope of this application.

Claims (10)

1. A diode device applied to HEMT, characterized in that, said diode device comprises: semiconductor substrate; a first channel layer disposed on the semiconductor substrate; a first barrier layer disposed on the first channel layer; A plurality of second channel layers and a plurality of second barrier layers, wherein the plurality of second channel layers and the plurality of second barrier layers are alternately stacked and arranged on the first barrier layer , the second channel layer at the bottom is disposed on the first barrier layer, and the widths of the plurality of second channel layers and the plurality of second barrier layers are sequentially reduced, so that The first sides of each of the second channel layers and the plurality of second barrier layers form a ladder structure; a capping layer disposed on top of the second barrier layer; an anode electrode layer disposed on the stepped structure and the capping layer; a cathode electrode layer disposed on the first channel layer and disposed on the second side of the plurality of second channel layers and the plurality of second barrier layers; an insulating medium layer, disposed on the second barrier layer at the top, and located between the anode electrode layer and the cathode electrode layer and between the capping layer and the cathode electrode layer; wherein, the The anode electrode layer and the cathode electrode layer are respectively connected to the source and drain of the HEMT. 2. The diode device according to claim 1, wherein the second sides of the plurality of second channel layers and the plurality of second barrier layers are connected to the second sides of the first barrier layers. side flush. 3. The diode device according to claim 2, wherein the cathode electrode layer is also disposed on the second side of the first barrier layer and penetrates deep into the first channel layer. 4. The diode device according to claim 2, wherein the difference between the width of the second barrier layer and the width of the second channel layer on the back side of the second barrier layer is equal to The difference between the width of the second barrier layer and the width of the second channel layer on the front side of the second barrier layer. 5. The diode device according to any one of claims 1-4, wherein the upper surface of the insulating medium layer is flush with the upper surface of the anode electrode layer. 6. The diode device according to any one of claims 1-4, wherein the thickness of the second channel layer is the same as the thickness of the second barrier layer. 7. The diode device according to any one of claims 1-4, wherein the insulating dielectric layer is a high dielectric material. 8. A method for preparing a diode device applied to a HEMT, comprising: sequentially forming a first channel layer and a first barrier layer on a semiconductor substrate; A plurality of second channel layers and a plurality of second barrier layers alternately stacked on the first barrier layer; wherein, the second channel layer at the bottom is arranged on the first barrier layer , and the widths of the plurality of the second channel layers and the plurality of the second barrier layers are sequentially reduced, so that the widths of the plurality of the second channel layers and the plurality of the second barrier layers The first side forms a stepped structure; forming a capping layer on top of said second barrier layer; forming an anode electrode layer on the stepped structure and the capping layer; A cathode electrode layer is formed on the first channel layer; wherein, the cathode electrode layer is disposed on the second side of the plurality of second channel layers and the plurality of second barrier layers; An insulating dielectric layer is formed on the top second barrier layer, and the insulating dielectric layer is located between the anode electrode layer and the cathode electrode layer and between the capping layer and the cathode electrode layer. 9. A HEMT, characterized in that, the diode device according to any one of claims 1-7 is integrated in the HEMT; or the diode device prepared by the preparation method according to claim 8 is included. 10. The HEMT according to claim 9, wherein the diode device applied to the HEMT is arranged under the gate, the drain or the source of the HEMT, and the anode electrode layer and the HEMT The source is connected, and the cathode electrode layer is connected to the drain of the HEMT.

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