CN115602605B - Interposer for packaging, preparation method of interposer and semiconductor packaging structure - Google Patents
Interposer for packaging, preparation method of interposer and semiconductor packaging structureInfo
- Publication number
- CN115602605B CN115602605B CN202110721421.3A CN202110721421A CN115602605B CN 115602605 B CN115602605 B CN 115602605B CN 202110721421 A CN202110721421 A CN 202110721421A CN 115602605 B CN115602605 B CN 115602605B
- Authority
- CN
- China
- Prior art keywords
- silicon substrate
- layer
- copper conductive
- substrate
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H10W20/023—
-
- H10W20/20—
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明提供一种用于封装的转接板及其制备方法、半导体封装结构，该制备方法包括：提供包括支撑基底、分离层及硅衬底的叠层结构，硅衬底中形成有TSV孔，TSV孔中有铜导电柱，铜导电柱与TSV孔侧壁之间有扩散阻挡层；研磨硅衬底的上表面至TSV孔完全露出；采用化学机械抛光工艺抛光叠层结构的上表面；采用湿法刻蚀工艺刻蚀铜导电柱预设深度，形成刻蚀凹槽；于刻蚀凹槽中填充满保护层；刻蚀硅衬底的上表面至裸露出铜导电柱；采用化学气相沉积工艺于硅衬底的上表面形成绝缘层。通过湿法刻蚀形成刻蚀凹槽并结合填充于其中的保护层，可有效避免整个转接板制备过程中所有铜导电柱的铜粒子扩散至硅衬底的可能性，有效提高了封装结构的性能。
This invention provides an adapter board for packaging, a method for fabricating the same, and a semiconductor packaging structure. The fabrication method includes: providing a stacked structure comprising a support substrate, a separation layer, and a silicon substrate; forming TSV vias in the silicon substrate; containing copper conductive pillars within the TSV vias; and a diffusion barrier layer between the copper conductive pillars and the sidewalls of the TSV vias; grinding the upper surface of the silicon substrate until the TSV vias are fully exposed; polishing the upper surface of the stacked structure using a chemical mechanical polishing process; etching the copper conductive pillars to a predetermined depth using a wet etching process to form etched grooves; filling the etched grooves with a protective layer; etching the upper surface of the silicon substrate until the copper conductive pillars are exposed; and forming an insulating layer on the upper surface of the silicon substrate using a chemical vapor deposition process. By forming etched grooves through wet etching and combining them with the protective layer filled therein, the possibility of copper particles from all copper conductive pillars diffusing to the silicon substrate during the entire adapter board fabrication process can be effectively avoided, thus effectively improving the performance of the packaging structure.
Description
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to an adapter plate for packaging, a preparation method of the adapter plate and a semiconductor packaging structure.
Background
With the development of miniaturization, high performance, high reliability and the like of electronic products, the system integration level is increasing, and in this case, the way of improving the performance by further reducing the feature size of the integrated circuit and the line width of the interconnection line is limited by the physical characteristics of materials and the device technology, so that the traditional moore's law is difficult to develop continuously. Currently, advanced packaging methods include wafer level Chip scale packaging (WAFER LEVEL CHIP SCALE PACKAGING, WLCSP), fan-Out wafer level packaging (Fan-Out WAFER LEVEL PACKAGE, FOWLP), flip Chip (Flip Chip), stacked packaging (Package on Package, POP), and the like. The 2.5D/3D integration technology with TSV as the core has been widely considered as the dominant technology in the future high density packaging field, and is an effective way to break through moore's law.
The conventional 2.5D/3D package structure generally includes a silicon interposer, in which through silicon vias (TSV holes for short) are provided, and copper conductive pillars are formed in the through silicon vias to interconnect the chip and the substrate. The process of exposing the copper conductive pillars in the backside TSV holes, referred to as BVR (backside VIA REVEAL), generally includes steps of silicon substrate grinding, silicon substrate surface Chemical Mechanical Polishing (CMP) and silicon substrate etching, which can cause copper in the TSV holes to diffuse into the silicon substrate, eventually resulting in reduced performance of the entire package structure.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an interposer for packaging, a method for manufacturing the interposer, and a semiconductor packaging structure, for solving the problems of reduced performance of the whole packaging structure and the like due to easy diffusion of copper in a TSV hole into a silicon substrate during the manufacturing process of a silicon interposer of a 2.5D/3D packaging structure in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing an interposer for packaging, the method comprising:
Providing a laminated structure, wherein the laminated structure sequentially comprises a supporting substrate, a separation layer and a silicon substrate from bottom to top, a TSV hole extending from bottom to top is formed in the silicon substrate, copper conductive columns are filled in the TSV hole, and a diffusion barrier layer is formed between the copper conductive columns and the side wall of the TSV hole;
grinding the upper surface of the silicon substrate until the TSV holes are completely exposed;
Polishing the upper surface of the laminated structure by adopting a chemical mechanical polishing process;
Etching the copper conductive column to a preset depth by adopting a wet etching process to form an etching groove, and removing copper ground to the surface of the silicon substrate by adopting a wet etching solution;
filling the etching groove with a protective layer;
etching the upper surface of the silicon substrate until the copper conductive posts are exposed;
And forming an insulating layer on the upper surface of the silicon substrate by adopting a chemical vapor deposition process.
Optionally, the wet etching solution is copper etching solution, including phosphoric acid and hydrogen peroxide.
Optionally, the step of forming the laminated structure includes:
Providing the silicon substrate and forming the TSV hole in the silicon substrate;
forming the diffusion barrier layer on the side wall of the TSV hole;
Filling copper material in the TSV hole to form the copper conductive column;
providing the support base and the separation layer, and bonding the support base and the side of the silicon substrate with the TSV hole based on the separation layer to form the laminated structure.
Optionally, the step of forming the protective layer includes:
Depositing a protective layer material on the upper surface of the laminated structure by adopting a chemical vapor deposition process until the etched groove is filled;
And polishing the upper surface of the laminated structure to the upper surface of the silicon substrate by adopting a chemical mechanical polishing process so as to form the protective layer covering the upper surface of the copper conductive column.
Optionally, the step of forming the insulating layer includes:
Depositing an insulating layer material on the upper surface of the laminated structure by adopting a chemical vapor deposition process;
And polishing the insulating layer material and the protective layer by adopting a chemical mechanical polishing process to expose the copper conductive column, so as to form an insulating layer covering the silicon substrate.
Optionally, the depth of the etched groove is between 1% and 2% of the length of the copper conductive column, and the material of the protective layer is silicon oxide.
The invention also provides an adapter plate for packaging, which can be prepared by adopting the preparation method of any adapter plate for packaging, and comprises the following steps:
support bases and silicon substrates adhered to the upper and lower side surfaces of the separation layer;
a TSV hole penetrating the silicon substrate;
Copper conductive posts filled in the TSV holes and protruding out of the TSV holes, wherein copper in the copper conductive posts is not diffused into the surface of the silicon substrate;
a diffusion barrier layer formed between the copper conductive pillar and the TSV hole sidewall and extending to be flush with the copper conductive pillar;
and the insulating layer is formed on the surface of the silicon substrate and completely covers the periphery side of the copper conductive column.
Optionally, the support substrate comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate, and the separation layer comprises a polymer layer or an adhesive layer.
Optionally, the diffusion barrier layer includes one or a stack of at least two of a tantalum nitride layer, a titanium nitride layer, a silicon nitride layer, and a silicon oxide layer.
Optionally, the insulating layer includes a stack of one or both of a silicon nitride layer and a silicon oxide layer.
The invention also provides a semiconductor packaging structure, which comprises the adapter plate for packaging.
As described above, the encapsulated adapter plate, the preparation method thereof and the semiconductor encapsulation structure can remove copper particles diffused into the surface of the silicon substrate in the previous process by forming the etching groove through wet etching, and lay a foundation for depositing the protective layer on the upper surface of the subsequent copper conductive column. Therefore, the possibility that all copper conductive columns are diffused to the silicon substrate is avoided in the whole preparation process of the adapter plate, and the performance of the packaging structure is effectively improved.
Drawings
Fig. 1 to 6 are schematic structural views showing steps in the manufacturing process of an interposer for packaging in the prior art.
Fig. 7 is a schematic flow chart of a method for manufacturing an interposer for packaging according to an embodiment of the invention.
Fig. 8 to 19 are schematic structural views showing steps in a method for manufacturing an interposer for packaging according to the first embodiment of the present invention. Fig. 19 is a schematic structural diagram of a interposer for packaging according to a second embodiment of the present invention.
Description of element reference numerals
100. 200 Laminated structure
101. 201 Support substrate
102. 202 Separation layer
103. 203 Silicon substrate
104. 204 TSV holes
105. 205 Copper conductive column
106. 206 Diffusion barrier
107. 210 Insulating layer material
108. 211 Insulating layer
207. Etched groove
208. Protective layer material
209. Protective layer
A copper particle
Depth of etched groove
S1 to S7 steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 19. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the types, numbers and proportions of the components in actual implementation may be changed according to actual needs, and the layout of the components may be more complex.
Example 1
As shown in fig. 1 to 6, the preparation process of the interposer for packaging in the prior art includes the following steps:
As shown in fig. 1, a stacked structure 100 is provided first, the stacked structure 100 includes a support substrate 101, a separation layer 102 and a silicon substrate 103 from bottom to top, a TSV hole 104 extending from bottom to top is formed in the silicon substrate 103, the TSV hole 104 is filled with a copper conductive column 105, and a diffusion barrier layer 106 is formed between the copper conductive column 105 and a sidewall of the TSV hole 104.
The silicon substrate 103 is generally thicker, and the TSV holes 104 cannot penetrate the silicon substrate 103, so the silicon substrate 103 needs to be thinned, as shown in fig. 2, and then the silicon substrate 103 is thinned. With the thinning of the silicon substrate 103 until the TSV hole 104 is completely exposed, copper particles in the copper conductive post 105 are ground into the silicon substrate 103 on the periphery of the TSV hole 104, such as copper particles a in fig. 2.
As shown in fig. 3, the upper surface of the stacked structure 100 is then polished using a chemical mechanical polishing process (CMP for short). The polishing process further causes copper particles in the copper conductive pillars 105 to be ground into the silicon substrate 103 on the periphery of the TSV holes 104, increasing the concentration of copper particles a in the silicon substrate.
As shown in fig. 4, the upper surface of the silicon substrate 103 is then etched until the copper conductive pillars 105 are exposed. As described above, since the copper particles a in the copper conductive pillars 105 are diffused in the silicon substrate 103 on the periphery of the TSV holes 104, the silicon substrate 103 on the periphery of the TSV holes 104 is not easily etched in the process of etching the silicon substrate 103, and at the same time, the etching of the silicon substrate 103 may further cause the copper particles in the copper conductive pillars 105 to diffuse into the silicon substrate 103 on the periphery of the TSV holes 104, so that the etching difficulty of the silicon substrate 103 on the periphery of the TSV holes 104 is increased, thereby generating silicon substrate etching defects.
As shown in fig. 5, an insulating layer material 107 is then deposited on the upper surface of the stacked structure 100 using a chemical vapor deposition process.
As shown in fig. 6, the insulating layer material 107 is finally polished using a chemical mechanical polishing process to expose the copper conductive pillars 105 while forming an insulating layer 108 covering the silicon substrate. As can be seen from the above steps, since the silicon substrate 103 on the periphery of the TSV 104 is not easily etched, polishing the insulating layer material 107 will result in the insulating layer material 107 on the periphery of the TSV 104 being polished, so that the insulating protection effect on the copper conductive pillars 105 is not achieved, the leakage risk is caused, and the performance of the whole package structure is finally reduced.
The inventor provides a preparation method of the interposer for packaging from the aspect of preventing copper conductive columns from diffusing to a silicon substrate based on research and analysis of the preparation process of the conventional interposer for packaging, wherein the preparation method comprises the following steps:
As shown in fig. 7 and 11, step S1 is first performed to provide a stacked structure 200, where the stacked structure 200 includes a support substrate 201, a separation layer 202 and a silicon substrate 203 from bottom to top, a TSV hole 204 extending from bottom to top is formed in the silicon substrate 203, the TSV hole 204 is filled with a copper conductive column 205, and a diffusion barrier layer 206 is formed between the copper conductive column 205 and a sidewall of the TSV hole 204.
As an example, the support substrate 201 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In this embodiment, the support substrate 201 is selected to be a glass substrate, which has low cost, is easy to form the separation layer 202 on the surface thereof, and can reduce the difficulty of the subsequent peeling process.
The separation layer 202 is preferably made of an adhesive material having a smooth surface, and must have a certain bonding force with the silicon substrate 203 so as to ensure that the silicon substrate 203 will not move in the subsequent process, and also has a strong bonding force with the support substrate 201, and generally, the bonding force with the support substrate 201 needs to be greater than the bonding force with the silicon substrate 203. As an example, the separation layer 202 includes a polymer layer or an adhesive layer, which is first coated on the surface of the support substrate 201 using a spin coating process, and then cured and formed using an ultraviolet curing or thermal curing process.
In this embodiment, the polymer layer includes an LTHC light-heat conversion layer, and then when the support substrate 201 is peeled off, the LTHC light-heat conversion layer may be heated based on laser light, so that the silicon substrate 203 and the support substrate 201 are separated from each other at the LTHC light-heat conversion layer.
As an example, the diffusion barrier layer 206 includes one layer or a stack of at least two layers of a tantalum nitride layer, a titanium nitride layer, a silicon nitride layer, and a silicon oxide layer.
As shown in fig. 8 to 11, the step of forming the laminated structure 200 includes, as an example:
as shown in fig. 8, the silicon substrate 203 is provided first, and the TSV hole 204 is formed in the silicon substrate 203, wherein the TSV hole 204 is a blind hole that does not penetrate the silicon substrate 203;
as shown in fig. 9, the diffusion barrier layer 206 is then formed on the sidewalls of the TSV hole 204;
As shown in fig. 10, the TSV hole 204 is then filled with copper material to form the copper conductive post 205;
As shown in fig. 11, the support base 201 and the separation layer 202 are finally provided, and the support base 201 and the side of the silicon substrate 203 having the TSV hole 204 are bonded based on the separation layer 202 to form the stacked structure 200.
As shown in fig. 8 and 12, step S2 is performed to polish the upper surface of the silicon substrate 203 until the TSV hole 204 is completely exposed. With the thinning of the silicon substrate 203 until the TSV hole 204 is completely exposed, copper particles in the copper conductive post 205 are ground into the silicon substrate 203 on the periphery of the TSV hole 204, such as copper particles a in fig. 12.
As shown in fig. 8 and 13, step S3 is performed to polish the upper surface of the laminated structure by using a chemical mechanical polishing process, so as to polish the surface of the laminated structure. Further, the polishing process may cause copper particles in the copper conductive pillars 205 to be polished into the silicon substrate 203 around the TSV holes 204, so that the concentration of copper particles a in the silicon substrate increases.
As shown in fig. 8 and 14, step S4 is performed to etch the copper conductive pillars 205 to a predetermined depth by a wet etching process, thereby forming etching grooves 207, and the wet etching solution removes copper from the surface of the silicon substrate 203.
The etching groove 207 is formed by adopting a wet etching process, so that copper particles diffused into the surface of the silicon substrate 203 in the previous process can be removed, and a foundation can be laid for the deposition of a protective layer on the upper surface of the subsequent copper conductive column 205. As an example, the etching solution used in the wet etching process may be any existing copper etching solution suitable for etching copper particles, and in this embodiment, the preferred wet etching solution includes phosphoric acid and hydrogen peroxide, and the hydrogen peroxide can oxidize copper into copper oxide, and simultaneously the phosphoric acid etches away the copper oxide, so as to achieve the etching of the copper conductive pillars 105. As an example, the depth D of the etched groove is between 1% and 2% of the length of the copper conductive pillar, for example, when the length of the copper conductive pillar is 100 μm, the depth D of the etched groove is typically between 1 μm and 2 μm.
As shown in fig. 8 and 16, step S5 is performed to fill the etching groove 207 with the protection layer 209. Based on the protective layer 209, the copper conductive pillars 205 can be fully protected from etching in the subsequent etching process of the silicon substrate 203, so that copper particles in the copper conductive pillars 205 are prevented from diffusing into the silicon substrate 203 in the etching process of the silicon substrate 203.
As shown in fig. 15 and 16, the step of forming the protective layer 209 includes, as an example:
As shown in fig. 15, a chemical vapor deposition process is used to deposit a protective layer material 208 on the upper surface of the stacked structure 200 until the etched recess 207 is filled;
As shown in fig. 16, the upper surface of the stacked structure 200 is polished to the upper surface of the silicon substrate 203 using a chemical mechanical polishing process to form the protective layer 209 covering the upper surface of the copper conductive pillars 205.
As an example, the material of the protective layer 209 may be selected from conventional silicon etching protective materials, so as to have a better etching selectivity ratio with silicon. In this embodiment, the material of the protective layer is preferably silicon oxide.
As shown in fig. 8 and 17, step S6 is performed to etch the upper surface of the silicon substrate 203 until the copper conductive pillars 205 are exposed. In the process of the step, as the side wall of the copper conductive column 205 is provided with the diffusion barrier layer 206 and the top surface is provided with the protective layer 209, the copper conductive column 205 is not affected in etching, and the diffusion of copper particles into the silicon substrate is avoided. Thereby ensuring the effectiveness of the silicon substrate etching process. As an example, the silicon substrate 203 may be etched using a dry method.
As shown in fig. 8 and 19, finally, step S7 is performed to form an insulating layer 211 on the upper surface of the silicon substrate 203 by using a chemical vapor deposition process.
The insulating layer 211 may be a single layer or a stacked layer, and for example, the insulating layer 211 may have a single layer structure of silicon nitride or silicon oxide or a stacked structure of silicon oxide and silicon nitride.
As shown in fig. 18 and 19, the step of forming the insulating layer 211 includes, as an example:
as shown in fig. 18, an insulating layer material 210 is first deposited on the upper surface of the stacked structure 200 by a chemical vapor deposition process;
as shown in fig. 19, the insulating layer material 210 and the protective layer 209 are then polished using a chemical mechanical polishing process to expose the copper conductive pillars 205 and form an insulating layer 211 overlying the silicon substrate 203.
In this embodiment, the etching groove 207 is formed by wet etching, so that copper particles diffused into the surface of the silicon substrate 203 in the previous process can be removed, a foundation is laid for depositing a protective layer on the upper surface of the subsequent copper conductive column 205, and in addition, the etching groove 207 is combined with the protective layer 209 filled therein, so that the diffusion of copper particles into the silicon substrate in the etching process of the silicon substrate 203 can be effectively avoided. Therefore, the possibility that all copper conductive columns are diffused to the silicon substrate is avoided in the whole preparation process of the adapter plate, and the performance of the packaging structure is effectively improved.
Example two
The present embodiment provides an interposer for packaging, which is manufactured by using the manufacturing method of the first embodiment, and the beneficial effects that can be achieved by the interposer can be seen in the first embodiment, and the following description is omitted.
As shown in fig. 19, the interposer for packaging includes:
a support base 201 and a silicon substrate 203 bonded to the upper and lower sides of the separation layer 202;
A TSV hole 204 penetrating the silicon substrate 203;
Copper conductive pillars 205 filling the TSV holes 204 and protruding out of the TSV holes 204, and copper in the copper conductive pillars 205 not diffusing into the surface of the silicon substrate 203;
a diffusion barrier layer 206 formed between the copper conductive pillars 205 and the TSV hole 204 sidewalls and extending to be flush with the copper conductive pillars 205;
An insulating layer 211 formed on the surface of the silicon substrate 203 and entirely covering the periphery of the copper conductive pillars 205.
As an example, the support substrate 201 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, and the separation layer 202 includes a polymer layer or an adhesive layer.
As an example, the diffusion barrier layer 206 includes one layer or a stack of at least two layers of a tantalum nitride layer, a titanium nitride layer, a silicon nitride layer, and a silicon oxide layer.
As an example, the insulating layer 211 includes a stack of one or two of a silicon nitride layer and a silicon oxide layer.
The present embodiment also provides a semiconductor package structure including the interposer for packaging as described above.
In summary, the invention provides an adapter plate for packaging, a preparation method thereof and a semiconductor packaging structure, wherein copper particles diffused into the surface of a silicon substrate in the previous process can be removed by forming the etching groove through wet etching, a foundation is laid for depositing a protective layer on the upper surface of a subsequent copper conductive column, and in addition, the etching groove is combined with the protective layer filled in the subsequent etching groove, so that the diffusion of copper particles into the silicon substrate in the etching process of the silicon substrate can be effectively avoided. Therefore, the possibility that all copper conductive columns are diffused to the silicon substrate is avoided in the whole preparation process of the adapter plate, and the performance of the packaging structure is effectively improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110721421.3A CN115602605B (en) | 2021-06-28 | 2021-06-28 | Interposer for packaging, preparation method of interposer and semiconductor packaging structure |
| US17/851,652 US20220415670A1 (en) | 2021-06-28 | 2022-06-28 | Adapter board for packaging and method manufacturing the same, and semiconductor packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110721421.3A CN115602605B (en) | 2021-06-28 | 2021-06-28 | Interposer for packaging, preparation method of interposer and semiconductor packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115602605A CN115602605A (en) | 2023-01-13 |
| CN115602605B true CN115602605B (en) | 2026-01-20 |
Family
ID=84841693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110721421.3A Active CN115602605B (en) | 2021-06-28 | 2021-06-28 | Interposer for packaging, preparation method of interposer and semiconductor packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115602605B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118866828B (en) * | 2024-09-27 | 2025-03-04 | 甬矽半导体(宁波)有限公司 | 2.5D packaging structure and 2.5D packaging method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219282A (en) * | 2013-05-03 | 2013-07-24 | 华进半导体封装先导技术研发中心有限公司 | Through silicon via (TSV) exposure process |
| CN111769075A (en) * | 2020-06-18 | 2020-10-13 | 复旦大学 | A TSV passive adapter board for system-in-package and its manufacturing method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10466572B2 (en) * | 2017-03-24 | 2019-11-05 | Zhuhai Crystal Resonance Technologies Co., Ltd. | Method of fabrication for single crystal piezoelectric RF resonators and filters |
| CN108054134B (en) * | 2017-12-15 | 2021-07-20 | 西安科锐盛创新科技有限公司 | TSV adapter board for system-in-package and preparation method thereof |
| CN112133821A (en) * | 2019-06-25 | 2020-12-25 | 中电海康集团有限公司 | Preparation method of bottom electrode on copper interconnect in novel MRAM |
-
2021
- 2021-06-28 CN CN202110721421.3A patent/CN115602605B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219282A (en) * | 2013-05-03 | 2013-07-24 | 华进半导体封装先导技术研发中心有限公司 | Through silicon via (TSV) exposure process |
| CN111769075A (en) * | 2020-06-18 | 2020-10-13 | 复旦大学 | A TSV passive adapter board for system-in-package and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115602605A (en) | 2023-01-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103545275B (en) | Silicon through hole encapsulating structure and formation method | |
| CN100367452C (en) | Semiconductor device and manufacturing method thereof | |
| CN100334723C (en) | Semiconductor device and manufacturing method thereof | |
| CN109148415B (en) | Multi-wafer stack structure and method of forming the same | |
| US20090189256A1 (en) | Manufacturing process of semiconductor device and semiconductor device | |
| KR20100134777A (en) | Die stacking with annular vias with recessed sockets | |
| CN102237300B (en) | Through-substrate via structure and manufacturing method thereof | |
| CN102468229A (en) | Integrated circuit structure and its manufacturing method | |
| CN102468284A (en) | Stacked semiconductor device and manufacturing method thereof | |
| TW201001645A (en) | Semiconductor device and method of manufacturing the same | |
| CN111883498B (en) | A DRAM chip three-dimensional integrated system and preparation method thereof | |
| CN107644838A (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
| CN107305840A (en) | A kind of semiconductor devices and its manufacture method and electronic installation | |
| CN104332455A (en) | Structure of silicon through hole based semiconductor device on chip, and preparation method of the semiconductor device | |
| CN115602605B (en) | Interposer for packaging, preparation method of interposer and semiconductor packaging structure | |
| CN103219303A (en) | Packaging structure and method of TSV (Through Silicon Vias) back leakage hole | |
| CN215578494U (en) | Adapter plate for packaging and semiconductor packaging structure thereof | |
| WO2024021356A1 (en) | Tsv electrical connection structure having high aspect ratio and manufacturing method therefor | |
| US20220415670A1 (en) | Adapter board for packaging and method manufacturing the same, and semiconductor packaging structure | |
| CN112397445B (en) | TSV conductive structure, semiconductor structure and preparation method | |
| CN114902406B (en) | Three-dimensional stacked semiconductor assembly with near-zero bond wire thickness | |
| US20210358889A1 (en) | Semiconductor assembly and method of manufacturing the same | |
| CN107644841A (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
| CN111769075A (en) | A TSV passive adapter board for system-in-package and its manufacturing method | |
| CN102496579B (en) | A method for realizing electrical insulation on an adapter plate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |