CN115601219A - Image processing method, device, reference monitor and medium - Google Patents

Abstract

The present application provides an image processing method, device, reference monitor and medium. Since in the embodiment of the present application, the corresponding relationship between the first number and the column of the first VBO signal line is pre-saved in the FPGA, so that for each The first transmission group, the FPGA determines the first target where each column of RGB data in the first transmission group is located according to the first VBO signal line corresponding to each column of RGB data included in the first transmission group and the pre-saved correspondence. Columns, avoiding problems such as pixel misalignment in the received image, and improving the accuracy of image transmission.

Description

Image processing method, device, reference monitor and medium

technical field

The present application relates to the technical field of image processing, in particular to an image processing method, device, reference monitor and medium.

Background technique

HS(VBO)信号线进行传输。In the prior art, when a System on Chip (SOC) performs image transmission with a Field Programmable Gate Array (Field Programmable Gate Array, FPGA), mainly through

HS (VBO) signal line for transmission.

Specifically, the corresponding pins of the SOC and the FPGA are connected through VBO signal lines, and the SOC groups the pixels in the image into columns, and the number of columns of pixels contained in each group is the same as the number of VBO signal lines. The SOC sequentially sends the RGB data of each column of pixels in each group to the FPGA according to the order of the pins. After the FPGA receives the RGB data, it takes the order of the pins as the order of the VBO signal lines, and combines and stitches the received RGB data to obtain a complete image.

However, in the design and production of each chip circuit board, in order to meet the requirements of the circuit board size or the equal length and equal spacing of the VBO signal lines, the connection sequence of the SOC and FPGA pins will be adjusted during the production process, which leads to the SOC The pins of the FPGA are not connected correspondingly. For example, the pin 1 of the SOC should be connected to the pin 1 of the FPGA, but in the production process, the pin 1 of the SOC is connected to the pin 3 of the FPGA. In turn, the image spliced by the FPGA is inconsistent with the original image, which reduces the accuracy of image transmission.

Contents of the invention

The present application provides an image processing method, device, reference monitor and medium, which are used to solve the problem that the pins of the SOC and the FPGA are not connected correspondingly due to the influence of the circuit board design in the prior art, thereby resulting in splicing of the FPGA. The image is inconsistent with the original image, and the accuracy of image transmission is low.

In the first aspect, the embodiment of the present application provides an image processing method applied to a Field Programmable Logic Gate Array FPGA, the method comprising:

Receiving each column of RGB data sent by the system-on-chip SOC through the first preset number of first VBO signal lines, and determining each column of RGB data contained in each first transmission group;

For each first transmission group, according to the first VBO signal line corresponding to each column of RGB data contained in the first transmission group, and the pre-saved correspondence between the first number of the first VBO signal line and the column, determine the first VBO signal line The first target column where each column of RGB data in a transmission group is located; wherein, each first transmission group contains the first preset number of columns of RGB data;

The target image is determined according to the first target column where each column of RGB data in each first transmission group is located and the order of the first transmission group.

In the second aspect, the embodiment of the present application also provides an image processing device, which is applied to a field programmable logic gate array FPGA, and the device includes:

The receiving module is used to receive each column of RGB data sent by the system-on-chip SOC through the first preset number of first VBO signal lines, and determine each column of RGB data contained in each first transmission group;

The determination module is configured to, for each first transmission group, according to the first VBO signal line corresponding to each column of RGB data included in the first transmission group, and the correspondence between the first number of the first VBO signal line and the column stored in advance Relationship, determine the first target column where each column of RGB data in the first transmission group is located; wherein, each first transmission group contains the first preset number of columns of RGB data; according to each first transmission group The order of the first target column where each column of RGB data is located and the order of the first transmission group determines the target image.

In a third aspect, an embodiment of the present application further provides a benchmark monitor, where the benchmark monitor includes an FPGA, and the FPGA is configured to execute the steps of the image processing method as described above.

In a fourth aspect, the embodiment of the present application further provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned image processing method are realized.

In this embodiment of the application, the FPGA receives each column of RGB data sent by the SOC through the first preset number of first VBO signal lines, and determines each column of RGB data contained in each first transmission group; for each first transmission group group, according to the first VBO signal line corresponding to each column of RGB data contained in the first transmission group, and the pre-saved correspondence between the first number of the first VBO signal line and the column, determine each column in the first transmission group The first target column where the RGB data is located; wherein, each first transmission group contains a first preset number of columns; according to the target column where each column of RGB data is located in each first transmission group and the order of the first transmission group , to determine the target image. Since in the embodiment of the present application, the corresponding relationship between the first serial number and the column of the first VBO signal line is pre-saved in the FPGA, so that for each first transmission group, the FPGA uses the RGB data of each column contained in the first transmission group The corresponding first VBO signal line and the pre-stored corresponding relationship determine the first target column where each column of RGB data in the first transmission group is located, avoiding problems such as pixel misalignment in the received image, and improving image transmission. the accuracy rate.

Description of drawings

In order to illustrate the technical solution of the present application more clearly, the accompanying drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. Ordinary technicians can also obtain other drawings based on these drawings on the premise of not paying creative work.

FIG. 1 is a schematic structural diagram of a reference monitor in a related art provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of an image processing process provided by an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a reference monitor provided in an embodiment of the present application;

FIG. 4 is a schematic diagram of a first test image and a first prediction image provided by an embodiment of the present application;

Fig. 5 is a schematic flow chart of determining the corresponding relationship between the first serial number and the column of the first VBO signal line provided by the embodiment of the present application;

FIG. 6 is a schematic diagram of the internal structure of the FPGA provided by the embodiment of the present application;

Fig. 7 is the internal structural representation of the data detection and comparison module of the FPGA provided by the embodiment of the application;

FIG. 8 is a schematic diagram of second test images of two second transmission groups provided by an embodiment of the present application;

FIG. 9 is a schematic diagram of predicted images corresponding to the second test images of the two second transmission groups provided in the embodiment of the present application;

FIG. 10 is a schematic flowchart of determining the correspondence between the second number and the column of the second VBO signal line provided in the embodiment of the present application;

FIG. 11 is a schematic structural diagram of an image processing device provided in an embodiment of the present application;

FIG. 12 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

detailed description

In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application. rather than all examples. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in this application belong to the protection scope of this application.

In the related art, the reference monitor includes SOC, FPGA and timing controller (Timer Control Register, TCON). FIG. 1 is a schematic structural diagram of a reference monitor in the related art. As shown in Figure 1, the pins of the SOC are connected to the pins on one side of the FPGA through the VBO signal line, and the pins on the other side of the FPGA are connected to the TCON. Among them, the RGB data of the image is transmitted from the SOC to the FPGA chip through the VBO signal line. After the FPGA chip processes the RGB data, it is then transmitted to the back-end TCON through the VBO signal line, and finally displayed.

Among them, SOC and FPGA, and FPGA and TCON are usually connected by 8 VBO signal lines, and each VBO signal line is used to transmit RGB data of a specific column in the image. In addition, the 8 VBO signal lines transmit RGB data independently. The order of the various routes of the VBO signal line will not affect the quality of data transmission, but will affect the arrangement order of RGB data. Based on this, if the back-end chip does not recombine the image data in the order transmitted by the front-end chip, then the image displayed on the back-end will have pixel misalignment and display errors.

Therefore, in order to solve the above-mentioned problems, the embodiment of the present application provides an image processing method, which is applied to FPGA, and the FPGA receives each column of RGB data sent by the SOC through the first preset number of first VBO signal lines, and determines Each column of RGB data contained in each first transmission group; for each first transmission group, according to the first VBO signal line corresponding to each column of RGB data contained in the first transmission group, and the pre-saved first VBO signal The corresponding relationship between the first number of the line and the column determines the first target column where each column of RGB data in the first transmission group is located; wherein, each first transmission group contains a first preset number of columns; according to each The first target column where each column of RGB data in the first transmission group is located and the order of the first transmission group determine the target image.

Fig. 2 is a schematic diagram of an image processing process provided by the embodiment of the present application, the process includes:

S201: Receive each column of RGB data sent by the SOC through a first preset number of first VBO signal lines, and determine each column of RGB data included in each first transmission group.

An image processing method provided by an embodiment of the present application is applied to an FPGA, and the FPGA is deployed on a reference monitor.

FIG. 3 is a schematic structural diagram of a reference monitor provided by an embodiment of the present application. As shown in FIG. 3 , the reference monitor includes: a Microcontroller Unit (MCU), SOC, PC, host computer, and TCON. Wherein, in the embodiment of the present application, the MCU can configure the parameters of the FPGA after the FPGA is powered on; the SOC is the core device of the benchmark monitor, and has abundant input and output interfaces, such as High Definition Multimedia Interface (HDMI) ) and VBO, etc. At the same time, the SOC also has digital signal processing functions; PC software is installed in the PC, and technicians can read and write the content stored in the FPGA in real time through the PC software installed in the PC; TCON is used to drive LCD The monitor displays the image; the FPGA is used to receive the image sent by the SOC, and perform image processing on the image, such as enhancing the image quality effect, etc., and send the processed image to TOCN.

In the embodiment of the present application, the FPGA and the SOC are connected through a first preset number of first VBO signal lines, and the SOC transmits each column of RGB data of the image to the FPGA through the first preset number of first VBO signal lines. Wherein, in the embodiment of the present application, when performing the RGB data transmission of the image, the SOC divides the image into at least one first transmission group, and each first VBO signal line is used to transmit the data of a specific column in each first transmission group. RGB data. Each first transmission group includes the first preset number of columns of RGB data.

Based on this, in this embodiment of the application, the FPGA receives each column of RGB data sent by the SOC through the first preset number of first VBO signal lines, and according to the transmission sequence of each column of RGB data in the corresponding first VBO signal line , to determine each column of RGB data contained in each first transmission group. Specifically, each column of RGB data with the same transmission order is located in a first transmission group. For example, in the embodiment of the present application, the first column of RGB data transmitted by each first VBO signal line is determined as a first transmission group, and the second column of RGB data transmitted by each first VBO signal line is determined as a first column of RGB data. A transport group, etc.

S202: For each first transmission group, according to the first VBO signal line corresponding to each column of RGB data included in the first transmission group, and the pre-saved correspondence between the first number of the first VBO signal line and the column, determine The first target column where each column of RGB data in the first transmission group is located; wherein, each first transmission group contains the first preset number of columns of RGB data.

Due to the design of the circuit board, the pins of the same serial number of the FPGA and the SOC may not be connected correspondingly. In order to prevent the FPGA from directly arranging each column of RGB data received according to the order of the pins, the pixel misalignment of the obtained image occurs. , in the embodiment of the present application, the corresponding relationship between the first number and the column of the first VBO signal line is saved in the FPGA, so that after the FPGA receives each column of RGB data, for each first transmission group, it can The relationship determines the first target column corresponding to each column of RGB data included in the first transmission group.

Wherein, in the embodiment of the present application, the columns in the corresponding relationship are the columns in the first transmission group, and the first serial number of each first VBO signal line is generally the FPGA pipe corresponding to the first VBO signal line. The serial number of the foot.

Specifically, in the embodiment of the present application, after the FPGA determines the RGB data contained in each first transmission group, the FPGA determines the first VBO signal line that transmits the RGB data of each column, and obtains the stored The first serial number corresponding to the first VBO signal line. The FPGA determines the first target column where the RGB data of each column is located according to the stored correspondence between the first number of the first VBO signal line and the column. Wherein, in the embodiment of the present application, the first target column corresponding to each column of RGB data is the column in which the column of RGB data is located in the first transmission group. FPGA will finally generate an image consistent with that sent by the SOC according to the order of the first transmission group where each column of RGB data is located and the first target column in the first transmission group where each column of RGB data is located.

Wherein, it should be noted that each first transmission group includes a first preset number of columns.

In addition, in the embodiment of the present application, a VBO signal line sequence adjustment module at the receiving end may be added inside the FGPA, and the corresponding relationship between the first serial number and the column of the first VBO signal line is stored in the adjustment module.

In the embodiment of the present application, the corresponding relationship between the first serial number and the column of the first VBO signal line can be stored in the MCU, and when the FPGA is powered on, the MCU will write the corresponding relationship into the FPGA, so that the FPGA can The corresponding relationship combines each column of RGB data received to generate an image, wherein the image generated by the FPGA is consistent with the image sent by the SOC.

S203: Determine a target image according to the first target column where each column of RGB data in each first transmission group is located and the order of the first transmission group.

In the embodiment of the present application, after the FPGA determines the first target column where each column of RGB data in each first transmission group is located, the FPGA determines the first target column where each column of RGB data is located in each first transmission group. The order of the columns and the first transmission group determines the target image.

Specifically, for each first transmission group, the FPGA determines the sub-target image corresponding to the first transmission group according to the first target column where each column of RGB data in the first transmission group is located. After the FPGA determines each sub-target image corresponding to each first transmission group, the FPGA stitches each sub-target image according to the order of the first transmission group to obtain a target image.

Since in the embodiment of the present application, the corresponding relationship between the first serial number and the column of the first VBO signal line is pre-saved in the FPGA, so that for each first transmission group, the FPGA uses the RGB data of each column contained in the first transmission group The corresponding first VBO signal line and the pre-stored corresponding relationship determine the first target column where each column of RGB data in the first transmission group is located, avoiding problems such as pixel misalignment in the received image, and improving image transmission. the accuracy rate.

In order to avoid problems such as pixel misalignment in the image obtained after image reconstruction based on the received RGB data, on the basis of the above-mentioned embodiments, in the embodiment of the present application, the RGB data of each column included in the first transmission group Corresponding to the first VBO signal line, and the correspondence between the first serial number and the column of the first VBO signal line saved in advance, determining the first target column where each column of RGB data in the first transmission group is located includes:

For each column of RGB data in the first transmission group, determine the target first VBO signal line corresponding to the column of RGB data; according to the correspondence, determine the column corresponding to the target first number of the target first VBO signal line , determining the column as the first target column where the RGB data of the column is located.

In the embodiment of the present application, when the FPGA determines the first target column where each column of RGB data in the first transmission group is located, for each column of RGB data in the first transmission group, the FPGA determines the target column for transmitting the column of RGB data. Target the first VBO signal line, and according to the stored correspondence, determine the column corresponding to the target first number of the target first VBO signal line, and determine this column as the first target column where the RGB data of the column is located.

For example, in the embodiment of the present application, the first transmission group sent by the SOC to the FPGA through the four first VBO signal lines includes four columns of RGB data. Wherein, the numbers of the four first VBO signal lines are divided into 1, 2, 3 and 4, and the four columns of RGB data are respectively RGB data A, RGB data B, RGB data C and RGB data D, and the numbered 1st One VBO signal line transmits RGB data A, the first VBO signal line numbered 2 transmits RGB data B, the first VBO signal line numbered 3 transmits RGB data C, and the first VBO signal line numbered 4 transmits RGB data D . Moreover, the corresponding relationship stored in the FPGA is that number 1 corresponds to the first column, number 2 corresponds to the fourth column, number 3 corresponds to the second column, and number 4 corresponds to the third column. Based on this, the FPGA determines that the first target column where RGB data A is located is the first column, the first target column where RGB data B is located is the fourth column, the first target column where RGB data C is located is the second column, and the first target column where RGB data C is located is the second column. The first target column where D is located is the third column.

In order to improve the accuracy of image transmission, on the basis of the above embodiments, in this embodiment of the application, the process of determining each first transmission group includes:

Determine the transmission order of each RGB data in the corresponding first VBO signal line;

Determine the RGB data with the same transmission sequence as a first transmission group.

In the embodiment of the present application, when the FPGA determines each first transmission group, the FPGA determines the transmission order of each RGB data in the corresponding first VBO signal line, and determines the RGB data with the same transmission order as one first transmission group. For example, the FPGA determines the first column of RGB data transmitted by each first VBO signal line as a transmission group.

In order to save the corresponding relationship between the first serial number and the column of the first VBO signal line in the FPGA, thereby improving the accuracy of image transmission, on the basis of the above-mentioned embodiments, in the embodiment of the present application, the first VBO The process of determining the corresponding relationship between the first number of the signal line and the column includes:

Send the generated first test image to the SOC through the host computer, wherein the first test RGB data of each column in the first test image is different, and the first test image contains a first preset number of columns ;

sending to the SOC a sending instruction carrying sending each column of RGB data, and receiving each column of second test RGB data sent by the SOC through the first preset number of first VBO signal lines;

For each column of the second test RGB data, determine the second target column corresponding to the column of the second test RGB data in the first test image, and combine the second target column with the column that transmits the column of the second test RGB data The first serial number of the first VBO signal line is stored correspondingly.

In the embodiment of the present application, the FPGA generates the first test image, and sends the first test image to the SOC. Wherein, since the corresponding relationship between the first number and the column of the first VBO signal line is applicable to all the first transmission groups, in order to save transmission resources, in the embodiment of the present application, the first test image can be composed of a first The configuration of the transmission group means that the number of columns contained in the first test image is consistent with the number of the first VBO signal lines.

Wherein, in order for the SOC to accurately receive the first test image generated by the FPGA, in the embodiment of the present application, the FPGA sends the generated first test image to the SOC through the host computer.

In the embodiment of the present application, after the FPGA sends the first test image to the SOC through the host computer, the FPGA sends a sending instruction to the SOC, so that the SOC passes the first preset number of first images after receiving the sending instruction. The VBO signal line sends the first test RGB data of each column of the first test image to the FPGA. Moreover, since the RGB data received by a pin of a certain serial number of the FPGA may not be in the same column as the RGB data sent by the pin of the same serial number of the SOC, for example, the pin with the serial number of the SOC being 1 is responsible for sending the first test image. A column of RGB data, but the RGB data received by the pin with FPGA serial number 1 is the third column of the first test image. Therefore, in the embodiment of this application, the RGB data received by the FPGA is called the second test RGB data.

In the embodiment of the present application, after the FPGA receives the second test RGB data, for each column of the second test RGB data, the FPGA determines the second target column corresponding to the column of second test data in the first test image, And store the second target column in correspondence with the first serial number of the first VBO signal line transmitting the second test RGB data of the column.

Specifically, in the embodiment of the present application, when the FPGA determines the second target column corresponding to the second test RGB data of each column, it can be determined in one or more of the following ways:

Mode 1: For each column of second test RGB data, according to the first test RGB data corresponding to each column of pixel points in the first test image, search for the second target column corresponding to the second test RGB data in the first test image .

Since each column of the first test RGB data of the first test image is different, therefore, for each column of the second test RGB data, the FPGA can search the first test image for the same target first test image as the numerical value of the second test RGB data. RGB data, and determine the column where the target first test RGB data is located as the second target column corresponding to the second test RGB data.

For example, there are 4 columns of first test RGB data in the first test image, and for a certain second test RGB data, the FPGA determines that the value of the second test RGB data is consistent with the first test RGB data of the third column in the first test image. If the values of the data are the same, the FPGA determines that the third column is the second target column corresponding to the second test RGB data.

Method 2: The FPGA sorts the pre-saved first numbers of each first VBO signal line, and according to the sorting result, splices the second test RGB data transmitted by each first VBO signal line to obtain the first predicted image. The FPGA compares the first predicted image with the first test image, and adjusts the order of the second test RGB data in the first predicted image according to the order of the first test RGB data in the first test image, The first predicted image is made to coincide with the first test image. For each second test RGB data, the FPGA determines the column where the second test RGB data is located in the adjusted first prediction image, and determines this column as the second target column corresponding to the second test RGB data.

Figure 4 is a schematic diagram of the first test image and the first predicted image provided by the embodiment of the present application. As shown in Figure 4, each column of first test RGB data in the first test image is different, and the first predicted image is different from the first predicted image. The second and third columns of test images are different.

In addition, in the embodiment of the present application, after the FPGA determines the correspondence between the first serial number and the column of the first VBO signal line, the FPGA saves the correspondence in a register, and sends the correspondence to the MCU, so that The MCU writes the corresponding relationship into the program of the power-on configuration parameters. When the FPGA is powered on again, the MCU can send the power-on configuration parameters to the FPGA, so that the FPGA can save the corresponding relationship.

Fig. 5 is a schematic flow chart for determining the corresponding relationship between the first number and the column of the first VBO signal line provided by the embodiment of the present application. As shown in Fig. 5, the process includes:

S501: The reference monitor is powered on.

S502: The MCU configures the parameters of the FPGA so that the reference monitor can work normally.

S503: The technician controls the FPGA to enter the VBO signal line detection mode through the host computer.

In the embodiment of the present application, the technician can send an instruction to the FPGA to enter the VBO signal line detection mode through the host computer, so that the FPGA enters the VBO signal line detection mode, and determine the correspondence between the first number and the column of the first VBO signal line .

S504: The FPGA generates a first test image.

S505: The host computer acquires the first test image generated by the FPGA, and sends the first test image to the SOC.

S506: The FPGA sends to the SOC a sending instruction carrying RGB data for each column, and receives second test RGB data for each column sent by the SOC through the first preset number of first VBO signal lines.

S507: The FPGA sorts the pre-saved first numbers of each first VBO signal line, and splices the second test RGB data transmitted by each first VBO signal line according to the sorting result to obtain a first prediction image.

S508: The FPGA compares the first predicted image with the first test image.

S509: Adjust the sequence of the second test RGB data in the first prediction image according to the sequence of the first test RGB data in the first test image, so that the first prediction image is consistent with the first test image.

S510: For each second test RGB data, the FPGA determines a column where the second test RGB data is located in the adjusted first prediction image, and determines this column as a second target column corresponding to the second test RGB data.

S511: Store the second target column in a register corresponding to the first number of the first VBO signal line transmitting the second test RGB data of the column.

S512: The upper computer reads the corresponding relationship stored in the register.

S513: The display screen displays the first test image and the first prediction image, and the technician verifies whether the corresponding relationship is correct according to the display.

S514: The technician writes the corresponding relationship into the program of the power-on configuration parameters of the MCU, and powers on the FPGA again.

In order to enable the image to be correctly displayed on the display screen of the reference monitor, on the basis of the above-mentioned embodiments, in the embodiment of the present application, the method further includes:

Obtaining the saved second preset number of the second VBO signal lines connected between the FPGA and the timing controller TCON, and grouping each column of RGB data in the target image according to the second preset number, and determining each second transmission group;

According to the correspondence between the second number and the column of the second VBO signal line saved in advance, determine the second VBO signal line of the second number corresponding to each column of each second transmission group in the target image;

Send each column of RGB data in the target image to the TCON by using the second numbered second VBO signal line corresponding to each column of RGB data in each second transmission group.

In the embodiment of the present application, the FPGA is also connected to the TCON and sends RGB data to the TCON, so that the TCON controls the display to display images.

Specifically, in this embodiment of the application, the FPGA acquires the saved second preset number of second VBO signal lines connected to the FPGA and TCON, and according to the second preset number, each The columns of RGB data are grouped to identify each second transmission group. Wherein, in this embodiment of the present application, the second preset number may be the same as or different from the first preset number.

Due to the design of the circuit board, the connection order of the pins of the FPGA and the TCON will be adjusted during the production process of the circuit board, which results in that the pins of the TCON and the FPGA are not connected correspondingly. For example, pin 1 of TCON should be connected to pin 1 of FPGA, but in the production process, pin 1 of TCON should be connected to pin 3 of FPGA. In turn, the image spliced by TCON is inconsistent with the target image, which reduces the accuracy of image transmission. Based on this, in the embodiment of the present application, the corresponding relationship between the second number and the column of the second VBO signal line is also saved in the FPGA, and the FPGA determines each second transmission group in the target image according to the corresponding relationship. The second number corresponding to each column, and using the second VBO signal line of the second number corresponding to each column of RGB data in each second transmission group, to send each column of RGB data in the target image to TCON, so that TCON can control The display shows the correct target image.

Figure 6 is a schematic diagram of the internal structure of the FPGA provided by the embodiment of the present application. As shown in Figure 6, the FPGA includes a serial-to-parallel conversion decoding module, a parallel-to-serial conversion encoding module, a receiving data reorganization module, a sending data reorganization module, and a data detection comparison Module and data read and write module. Among them, the serial-to-parallel conversion decoding module is used to perform serial-to-parallel conversion of each column of RGB data, and converts each column of RGB data sent by the SOC from a serial signal to a parallel digital signal; the parallel-to-serial conversion encoding module is used to perform parallel data conversion Serial conversion, converting each column of RGB data from parallel digital signals to serial signals, and sending them to TCON for display; the receiving data reorganization module is used to rearrange and combine each column of RGB data sent by SOC to form the target image; sending data The recombination module is used to re-split the target image, and sends each column of RGB data after splitting to TCON; the image processing module is used to process the image to achieve image quality enhancement and other effects; the data detection and comparison module is used to It is used to generate the test image and determine the corresponding relationship between the number of the VBO signal line and the column; the data reading and writing module is used to receive the parameters configured by the MCU after power-on, and perform parameter configuration, and receive the internal data of the FPGA through the host computer. read and write.

In order to save the corresponding relationship between the second number and the column of the second VBO signal line in the FPGA, thereby improving the accuracy of image transmission, on the basis of the above-mentioned embodiments, in the embodiment of the present application, the second VBO The process of determining the corresponding relationship between the second number of the signal line and the column includes:

Send the third test RGB data of the generated second test image to the TCON, so that the TCON sorts the received third test RGB data to obtain a predicted image, and sends the predicted image to the SOC; wherein The third test RGB data of each column in the second test image is different, and the second test image includes a second preset number of columns;

receiving the fourth test RGB data of each column of pixels of the predicted image sent by the SOC through the first VBO signal line;

For each column of the fourth test RGB data, determine the third target column corresponding to the column of the fourth test RGB data in the second test image, and combine the third target column with the column that transmits the column of the fourth test RGB data. The second number corresponding to the second VBO signal line is saved.

In the embodiment of the present application, the FPGA generates the second test image, and sends the third test RGB data of each column of the second test image to the TCON. Wherein, since the corresponding relationship between the second number and the column of the second VBO signal line is applicable to all the second transmission groups, in order to save transmission resources, in the embodiment of the present application, the second test image can be composed of a second The configuration of the transmission group means that the number of columns contained in the second test image is consistent with the number of the second VBO signal lines.

Among them, since the RGB data sent by a pin of a certain serial number of the FPGA may not be in the same column as the RGB data received by a pin of the same serial number of the TCON, for example, the pin of the FPGA serial number 1 is responsible for sending the first image of the second test image. Column RGB data, but the RGB data received by the pin with TCON serial number 1 is the third column of the second test image. Therefore, in the embodiment of this application, each column of RGB data received by TCON is called the fourth test RGB data. After receiving the third test RGB data of each column, the TCON will sort the third test RGB data of each column according to the order of the pins connected to each second VBO signal line to obtain a predicted image.

In order for the FPGA to determine whether the predicted image determined by the TCON is pixel-disordered, in the embodiment of this application, the FPGA sends the second predicted image to the TCON, and after the TCON determines the predicted image, the TCON will also forward the predicted image to FPGA. Wherein, in order to make the predicted image received by the FPGA consistent with the predicted image determined by the TCON, in the embodiment of the present application, the TCON sends the predicted image to the SOC through the host computer, and then the SOC sends the predicted image to the FPGA.

In the embodiment of the present application, after the FPGA receives the fourth test RGB data of each column through the host computer and the SOC, for each column of the fourth test RGB data, the FPGA determines the corresponding a third target column, and store the third target column in correspondence with the second serial number of the second VBO signal line that transmits the fourth test RGB data of the column.

Specifically, in the embodiment of the present application, when the FPGA determines the third target column corresponding to the fourth test RGB data of each column, it can be determined in one or more of the following ways:

Mode 1: For each column of the fourth test RGB data, according to the third test RGB data corresponding to each column of pixel points in the second test image, find the third target column corresponding to the fourth test RGB data in the second test image .

Since the third test RGB data of each column of the second test image is different, therefore, for each column of the fourth test RGB data, the FPGA can search the second test image for the same target third test with the numerical value of the fourth test RGB data. RGB data, and determine the column where the target third test RGB data is located as the third target column corresponding to the fourth test RGB data.

For example, there are 4 columns of the third test RGB data in the second test image, and for a certain column of the fourth test RGB data, the FPGA determines that the value of the column's fourth test RGB data is consistent with the third test value of the third column in the second test image. If the values of the RGB data are the same, the FPGA determines that the third column is the third target column corresponding to the fourth test RGB data.

Method 2: According to the correspondence between the first serial number and the column of the first VBO signal line saved in advance, the FPGA splices the fourth test RGB data transmitted by each second VBO signal line, so that the FPGA restores and obtains the predicted image determined by TCON . The FPGA compares the prediction image with the second test image, and adjusts the order of the fourth test RGB data in the prediction image according to the order of the third test RGB data in the second test image, so that the prediction The image agrees with the second test image. For each column of the fourth test RGB data, the FPGA determines the column where the fourth test RGB data is located in the adjusted predicted image, and determines this column as the third target column corresponding to the fourth test RGB data.

In addition, in the embodiment of the present application, after the TCON determines the predicted image, the TCON can also control the display screen to display the predicted image, and the technician can obtain the second test image generated by the FPGA from the FPGA through the host computer, and according to The second test image and the predictive image determine the correspondence between the second number and the column of the second VBO signal line. The technician writes the corresponding relationship into the FPGA through the MCU.

In addition, when the FPGA generates the second test image, the second test image may further include two second transmission groups or multiple second transmission groups. Wherein, in the embodiment of the present application, when the FPGA generates the second test images of the two second transmission groups, it may first generate two sub-test images, which are respectively the first sub-test image and the second sub-test image. The FPGA splices the first sub-test image and the second sub-test image to obtain a second test image. Wherein, in order to improve the display effect of the image, the sub-test RGB data of one second transmission group in the first sub-test image is the RGB data corresponding to the white pixel, and the other second transmission group in the second sub-test image The sub-test RGB data is RGB data corresponding to black pixels; the sub-test RGB data of the two second transmission groups in the second sub-test image are the same, but the sub-RGB data of different columns of the same second transmission group are different.

Fig. 7 is the internal structure schematic diagram of the data detection comparison module of the FPGA that the embodiment of the present application provides, as shown in this Fig. 7, the data detection comparison module includes VBO RX test chart generation module, VBO RX test chart card extraction module inside , VBO RX data comparison module, VBO TX reference chart generation module, VBO TX detection chart generation module and chart splicing combination module. Wherein, the VBO RX test pattern card generating module is used to generate the first test image, and the first test image is read out to the PC through the host computer, and sent to the SCO chip; the VBO RX test pattern card extraction module is used to receive the Analyze the second test RGB data sent by the SOC to extract image recognition information; the VBO RX data comparison module is used to compare the second test RGB data and the first test RGB data generated by the VBO RX test chart generation module, and automatically identify The corresponding relationship between the first serial number and the column of the second VBO signal line of the FPGA, and write the corresponding relationship into the receiving data recombination module in the form of a register; the VBO TX reference image card generation module is used to generate the first sub-test image ; The VBO TX detection chart generation module is used to generate the second sub-test image; the chart splicing and combination module is used to splice the first sub-test image and the second sub-test image to obtain the second test image.

FIG. 8 is a schematic diagram of the second test images of the two second transmission groups provided by the embodiment of the present application. As shown in FIG. 8, the second test image is composed of two sub-test images, which are respectively the first sub-test image and The second subtest image. Wherein, the sub-test RGB data of a second transmission group in the first sub-test image is RGB data corresponding to white pixels, and the sub-test RGB data of another second transmission group in the second sub-test image is black pixels The RGB data corresponding to the point; the sub-test RGB data of the two second transmission groups in the second sub-test image are the same, but the sub-RGB data of different columns of the same second transmission group are different.

On the basis of Fig. 8, Fig. 9 is a schematic diagram of the predicted images corresponding to the second test images of the two second transmission groups provided by the embodiment of the present application. As shown in Fig. 9, each second transmission group of the predicted images Different from the second and third columns of each second transmission group of the first test image.

Fig. 10 is a schematic flowchart of determining the corresponding relationship between the second number and the column of the second VBO signal line provided by the embodiment of the present application. As shown in Fig. 10 , the process includes:

S1001: The host computer sends a VBO TX signal line sequential debugging command to the FPGA.

S1002: The VBO TX reference image card generating module of the FPGA generates a first sub-test image.

S1003: The VBO TX detection pattern generation module of the FPGA generates a second sub-test pattern.

S1004: The picture card splicing and combining module splices the first sub-test image and the second sub-test image together to obtain a second test image.

S1005: Receive the fourth test RGB data of each column of pixels of the prediction image sent by the SOC through the first VBO signal line.

S1006: For each column of fourth test RGB data, determine the third target column corresponding to the column of fourth test RGB data in the second test image, and transmit the third target column and the column of fourth test RGB data The data corresponding to the second number of the second VBO signal line is stored.

In order to send RGB data to TCON, on the basis of the above-mentioned embodiments, in the embodiment of the present application, the second VBO signal of the second number corresponding to each column of RGB data in each second transmission group line, sending each column of RGB data in the target image to the TCON includes:

Sorting each second transmission group according to a column of RGB data with the smallest sequence number contained in each second transmission group; wherein, the sequence number is the sequence of each column of RGB data in the target image;

According to the sorting result, for each second transmission group in turn, according to the second VBO signal line of the second number corresponding to each column of RGB data in the second transmission group, send each column in the second transmission group to the TCON RGB data.

In the embodiment of the present application, when the FPGA sends each column of RGB data in the target image to TCON according to the second VBO signal line of the second number corresponding to each column of RGB data in each second transmission group, the FPGA transmits each column of RGB data in the target image according to each A column of RGB data with the smallest sequence number included in the second transmission group, sorting each second transmission group, so that the FPGA determines the sorting result as each column of RGB data in each second transmission group in the corresponding first The transmission sequence in the two VBO signal lines.

Specifically, according to the sorting result, the FPGA sends the second transmission group to the TCON according to the second VBO signal line of the second number corresponding to each column of RGB data in the second transmission group for each second transmission group in turn. Each column of RGB data in .

Fig. 11 is a schematic structural diagram of an image processing device provided in an embodiment of the present application, the device includes:

The receiving module 1101 is used to receive each column of RGB data sent by the system-on-chip SOC through the first preset number of first VBO signal lines, and determine each column of RGB data contained in each first transmission group;

The determining module 1102 is configured to, for each first transmission group, according to the first VBO signal line corresponding to each column of RGB data included in the first transmission group, and the pre-saved first serial number of the first VBO signal line and the number of the column Correspondence, determine the first target column where each column of RGB data in the first transmission group is located; wherein, each first transmission group contains the first preset number of columns of RGB data; according to each first transmission The first target column where each column of RGB data in the group is located and the order of the first transmission group determine the target image.

In a possible implementation manner, the determining module 1102 is specifically configured to, for each column of RGB data in the first transmission group, determine the target first VBO signal line corresponding to the column of RGB data; according to the corresponding relationship , determining the column corresponding to the target first number of the target first VBO signal line, and determining the column as the first target column where the RGB data of the column is located.

In a possible implementation manner, the determining module 1102 is further configured to send the generated first test image to the SOC through the host computer, wherein each column of the first test RGB data in the first test image different, and the first test image contains a first preset number of columns; send a sending instruction carrying RGB data for each column to the SOC, and receive the first preset number of columns passed by the SOC Each column of the second test RGB data sent by a VBO signal line; for each column of the second test RGB data, determine the corresponding second target column of the column of the second test RGB data in the first test image, and the The second target column is correspondingly stored with the first serial number of the first VBO signal line transmitting the second test RGB data of the column.

In a possible implementation manner, the determination module 1102 is further configured to determine the transmission order of each RGB data in the corresponding first VBO signal line; determine the RGB data with the same transmission order as a first transmission group .

In a possible implementation manner, the determination module 1102 is further configured to acquire the saved second preset number of second VBO signal lines connecting the FPGA to the timing controller TCON, and Set the number, group each column of RGB data in the target image, and determine each second transmission group; according to the correspondence between the second number and the column of the second VBO signal line saved in advance, determine the data in the target image A second numbered second VBO signal line corresponding to each column of each second transmission group;

The device also includes:

The sending module 1103 is configured to send each column of RGB data in the target image to the TCON by using the second VBO signal line with the second number corresponding to each column of RGB data in each second transmission group.

In a possible implementation manner, the determining module 1102 is further configured to send the generated third test RGB data of the second test image to the TCON, so that the TCON performs Sorting to obtain predicted images, and sending the predicted images to the SOC; wherein each column of third test RGB data in the second test image is different, and the second test image contains a second preset number of column; receiving the fourth test RGB data of each column pixel point of the predicted image sent by the SOC through the first VBO signal line; for each column of the fourth test RGB data, determine the column of the fourth test RGB data in The corresponding third target column in the second test image, and store the third target column in correspondence with the second number of the second VBO signal line transmitting the fourth test RGB data of the column.

In a possible implementation manner, the sending module 1103 is specifically configured to sort each second transmission group according to a column of RGB data with the smallest sequence number contained in each second transmission group; wherein, the The serial number is the sorting of each column of RGB data in the target image; according to the sorting result, for each second transmission group in turn, according to the second VBO signal of the second number corresponding to each column of RGB data in the second transmission group line, sending each column of RGB data in the second transmission group to the TCON.

In the embodiment of the present application, the data transmission device is deployed in the FPGA of the reference monitor.

On the basis of the above embodiments, the embodiment of the present application also provides an electronic device. FIG. 12 is a schematic structural diagram of an electronic device provided in the embodiment of the present application. As shown in FIG. 12 , it includes: a processor 1201, a communication interface 1202, a memory 1203 and a communication bus 1204, wherein the processor 1201, the communication interface 1202, and the memory 1203 complete mutual communication through the communication bus 1204;

A computer program is stored in the memory 1203, and when the program is executed by the processor 1201, the processor 1201 is made to perform the following steps:

Receiving each column of RGB data sent by the system-on-chip SOC through the first preset number of first VBO signal lines, and determining each column of RGB data contained in each first transmission group;

For each first transmission group, according to the first VBO signal line corresponding to each column of RGB data contained in the first transmission group, and the pre-saved correspondence between the first number of the first VBO signal line and the column, determine the first VBO signal line The first target column where each column of RGB data in a transmission group is located; wherein, each first transmission group contains the first preset number of columns of RGB data;

The target image is determined according to the first target column where each column of RGB data in each first transmission group is located and the order of the first transmission group.

In a possible implementation manner, the processor is further configured to:

For each column of RGB data in the first transmission group, determine the target first VBO signal line corresponding to the column of RGB data; according to the correspondence, determine the column corresponding to the target first number of the target first VBO signal line , determining the column as the first target column where the RGB data of the column is located.

In a possible implementation manner, the processor is further configured to:

Send the generated first test image to the SOC through the host computer, wherein the first test RGB data of each column in the first test image is different, and the first test image contains a first preset number of columns ;

sending to the SOC a sending instruction carrying sending each column of RGB data, and receiving each column of second test RGB data sent by the SOC through the first preset number of first VBO signal lines;

For each column of the second test RGB data, determine the second target column corresponding to the column of the second test RGB data in the first test image, and combine the second target column with the column that transmits the column of the second test RGB data The first serial number of the first VBO signal line is stored correspondingly.

In a possible implementation manner, the processor is further configured to:

Determine the transmission order of each RGB data in the corresponding first VBO signal line;

Determine the RGB data with the same transmission sequence as a first transmission group.

In a possible implementation manner, the processor is further configured to:

Obtaining the saved second preset number of the second VBO signal lines connected between the FPGA and the timing controller TCON, and grouping each column of RGB data in the target image according to the second preset number, and determining each second transmission group;

According to the correspondence between the second number and the column of the second VBO signal line saved in advance, determine the second VBO signal line of the second number corresponding to each column of each second transmission group in the target image;

Send each column of RGB data in the target image to the TCON by using the second numbered second VBO signal line corresponding to each column of RGB data in each second transmission group.

In a possible implementation manner, the processor is further configured to:

Send the third test RGB data of the generated second test image to the TCON, so that the TCON sorts the received third test RGB data to obtain a predicted image, and sends the predicted image to the SOC; wherein The third test RGB data of each column in the second test image is different, and the second test image includes a second preset number of columns;

receiving the fourth test RGB data of each column of pixels of the predicted image sent by the SOC through the first VBO signal line;

For each column of the fourth test RGB data, determine the third target column corresponding to the column of the fourth test RGB data in the second test image, and combine the third target column with the column that transmits the column of the fourth test RGB data. The second number corresponding to the second VBO signal line is saved.

In a possible implementation manner, the processor is further configured to:

Sorting each second transmission group according to a column of RGB data with the smallest sequence number contained in each second transmission group; wherein, the sequence number is the sequence of each column of RGB data in the target image;

According to the sorting result, for each second transmission group in turn, according to the second VBO signal line of the second number corresponding to each column of RGB data in the second transmission group, send each column in the second transmission group to the TCON RGB data.

Since the problem-solving principle of the above-mentioned electronic device is similar to that of the image processing method, the implementation of the above-mentioned electronic device can refer to the embodiment of the method, and the repetition will not be repeated.

The communication bus mentioned in the above electronic device may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus or the like. The communication bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. The communication interface 1202 is used for communication between the electronic device and other devices. The memory may include a random access memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-Volatile Memory, NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

Above-mentioned processor can be general-purpose processor, comprises central processing unit, network processor (NetworkProcessor, NP) etc.; Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

On the basis of the above-mentioned embodiments, an embodiment of the present invention also provides a computer-readable storage medium, in which a computer program executable by a processor is stored, and when the program is run on the processor, the The following steps are implemented when the processor executes:

Receiving each column of RGB data sent by the system-on-chip SOC through the first preset number of first VBO signal lines, and determining each column of RGB data contained in each first transmission group;

For each first transmission group, according to the first VBO signal line corresponding to each column of RGB data contained in the first transmission group, and the pre-saved correspondence between the first number of the first VBO signal line and the column, determine the first VBO signal line The first target column where each column of RGB data in a transmission group is located; wherein, each first transmission group contains the first preset number of columns of RGB data;

The target image is determined according to the first target column where each column of RGB data in each first transmission group is located and the order of the first transmission group.

In a possible implementation manner, according to the first VBO signal line corresponding to each column of RGB data included in the first transmission group, and the pre-saved correspondence between the first serial number and the column of the first VBO signal line, Determining the first target column where each column of RGB data is located in the first transmission group includes:

For each column of RGB data in the first transmission group, determine the target first VBO signal line corresponding to the column of RGB data; according to the correspondence, determine the column corresponding to the target first number of the target first VBO signal line , determining the column as the first target column where the RGB data of the column is located.

In a possible implementation manner, the process of determining the correspondence between the first serial number and the column of the first VBO signal line includes:

Send the generated first test image to the SOC through the host computer, wherein the first test RGB data of each column in the first test image is different, and the first test image contains a first preset number of columns ;

sending to the SOC a sending instruction carrying sending each column of RGB data, and receiving each column of second test RGB data sent by the SOC through the first preset number of first VBO signal lines;

For each column of the second test RGB data, determine the second target column corresponding to the column of the second test RGB data in the first test image, and combine the second target column with the column that transmits the column of the second test RGB data The first serial number of the first VBO signal line is stored correspondingly.

In a possible implementation manner, the process of determining each first transmission group includes:

Determine the transmission order of each RGB data in the corresponding first VBO signal line;

Determine the RGB data with the same transmission sequence as a first transmission group.

In a possible implementation manner, the method also includes:

Obtaining the saved second preset number of the second VBO signal lines connected between the FPGA and the timing controller TCON, and grouping each column of RGB data in the target image according to the second preset number, and determining each second transmission group;

According to the correspondence between the second number and the column of the second VBO signal line saved in advance, determine the second VBO signal line of the second number corresponding to each column of each second transmission group in the target image;

Send each column of RGB data in the target image to the TCON by using the second numbered second VBO signal line corresponding to each column of RGB data in each second transmission group.

In a possible implementation manner, the process of determining the correspondence between the second number and the column of the second VBO signal line includes:

Send the third test RGB data of the generated second test image to the TCON, so that the TCON sorts the received third test RGB data to obtain a predicted image, and sends the predicted image to the SOC; wherein The third test RGB data of each column in the second test image is different, and the second test image includes a second preset number of columns;

receiving the fourth test RGB data of each column of pixels of the predicted image sent by the SOC through the first VBO signal line;

For each column of the fourth test RGB data, determine the third target column corresponding to the column of the fourth test RGB data in the second test image, and combine the third target column with the column that transmits the column of the fourth test RGB data. The second number corresponding to the second VBO signal line is saved.

In a possible implementation manner, according to the second VBO signal line with the second number corresponding to each column of RGB data in each second transmission group, each column in the target image is sent to the TCON RGB data includes:

Sorting each second transmission group according to a column of RGB data with the smallest sequence number contained in each second transmission group; wherein, the sequence number is the sequence of each column of RGB data in the target image;

According to the sorting result, for each second transmission group in turn, according to the second VBO signal line of the second number corresponding to each column of RGB data in the second transmission group, send each column in the second transmission group to the TCON RGB data.

Since the problem-solving principle of the above-mentioned computer-readable storage medium is similar to that of the image processing method, the implementation of the above-mentioned computer-readable storage medium can refer to the embodiment of the method, and repeated descriptions will not be repeated.

Those skilled in the art should understand that the embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the present application. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

Obviously, those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims (10)

1. An image processing method is applied to a Field Programmable Gate Array (FPGA), and is characterized by comprising the following steps of:

receiving each column of RGB data sent by the SOC through a first preset number of first VBO signal lines, and determining each column of RGB data contained in each first transmission group;

for each first transmission group, determining a first target column of each column of RGB data in the first transmission group according to a first VBO signal line corresponding to each column of RGB data included in the first transmission group and a pre-stored corresponding relation between a first number and the column of the first VBO signal line; each first transmission group comprises the first preset number of rows of RGB data;

and determining a target image according to the sequence of the first target column where each column of RGB data in each first transmission group is located and the first transmission group.

2. The method of claim 1, wherein the determining the first target column of the first transmission group where the RGB data in each column is located according to the first VBO signal line corresponding to the RGB data in each column included in the first transmission group and a pre-stored correspondence relationship between a first number and a column of the first VBO signal line comprises:

determining a target first VBO signal line corresponding to each column of RGB data in the first transmission group; and determining a column corresponding to the target first number of the target first VBO signal line according to the corresponding relation, and determining the column as a first target column where the RGB data of the column is located.

3. The method of claim 1, wherein the determining the first number to column correspondence of the first VBO signal line comprises:

sending the generated first test image to the SOC through an upper computer, wherein the first test RGB data of each column in the first test image are different, and the first test image comprises a first preset number of columns;

sending a sending instruction carrying RGB data of each column to the SOC, and receiving second test RGB data of each column sent by the SOC through the first VBO signal lines of the first preset number;

and for each column of second test RGB data, determining a second target column corresponding to the column of second test RGB data in the first test image, and correspondingly storing the second target column and a first number of a first VBO signal line for transmitting the column of second test RGB data.

4. The method of claim 1, wherein the determining for each first transmission group comprises:

determining the transmission sequence of each RGB data in the corresponding first VBO signal line;

the RGB data having the same transmission order is determined as a first transmission group.

5. The method of claim 1, further comprising:

acquiring a second preset number of second VBO signal lines connected with the FPGA and the time sequence controller TCON, grouping RGB data of each column in the target image according to the second preset number, and determining each second transmission group;

determining a second VBO signal line with a second number corresponding to each column of each second transmission group in the target image according to a pre-stored corresponding relationship between the second number and the column of the second VBO signal line;

and sending each column of RGB data in the target image to the TCON by adopting a second VBO signal line with a second number corresponding to each column of RGB data in each second transmission group.

6. The method of claim 5, wherein determining the correspondence of the second number to the column of the second VBO signal line comprises:

sending third test RGB data of the generated second test image to the TCON, enabling the TCON to carry out sequencing according to the received third test RGB data to obtain a predicted image, and sending the predicted image to the SOC; each column of third test RGB data in the second test image is different, and the second test image comprises a second preset number of columns;

receiving fourth test RGB data of each column of pixel points of the prediction image, which are sent by the SOC through the first VBO signal line;

and for each column of fourth test RGB data, determining a third target column corresponding to the column of fourth test RGB data in the second test image, and correspondingly storing the third target column and a second number of a second VBO signal line for transmitting the column of fourth test RGB data.

7. The method of claim 5, wherein the sending each column of RGB data in the target image to the TCON according to the second numbered second VBO signal lines corresponding to each column of RGB data in each second transmission group comprises:

sequencing each second transmission group according to a column of RGB data with the minimum sequence number in each second transmission group; the sequence number is the sequence of each column of RGB data in the target image;

and according to the sorting result, sequentially aiming at each second transmission group, and sending each column of RGB data in the second transmission group to the TCON according to the second VBO signal line of the second number corresponding to each column of RGB data in the second transmission group.

8. An image processing device applied to a Field Programmable Gate Array (FPGA), the device comprising:

the receiving module is used for receiving each column of RGB data sent by the system-on-chip SOC through a first VBO signal lines with a first preset number and determining each column of RGB data contained in each first transmission group;

the determining module is used for determining a first target column where each column of RGB data in each first transmission group is located according to a first VBO signal line corresponding to each column of RGB data included in the first transmission group and a pre-stored corresponding relation between a first number and the column of the first VBO signal line; each first transmission group comprises the first preset number of rows of RGB data; and determining a target image according to the sequence of the first target column where each column of RGB data in each first transmission group is located and the first transmission group.

9. A reference monitor, characterized in that it comprises an FPGA for performing the steps of the image processing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that it stores a computer program which, when being executed by a processor, carries out the steps of the image processing method according to any one of claims 1 to 7.

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