CN115598395B

CN115598395B - Hall sensing circuit

Info

Publication number: CN115598395B
Application number: CN202211082343.8A
Authority: CN
Inventors: 秦文辉; 盛云
Original assignee: Suzhou Novosense Microelectronics Co ltd
Current assignee: Suzhou Novosense Microelectronics Co ltd
Priority date: 2020-11-20
Filing date: 2020-11-20
Publication date: 2024-01-30
Anticipated expiration: 2040-11-20
Also published as: CN115290957A; CN112526191A; CN112526191B; CN115598395A

Abstract

The invention belongs to the field of measurement, and discloses a Hall sensing circuit which comprises a Hall sensor; the rotary switch circuit is connected with the Hall sensor and periodically excites two ports in the Hall sensor and simultaneously receives output signals of the other two ports; the rotary switch circuit outputs the output voltage of the Hall switch to the Wen wave elimination chopper amplifier at the same time; the chopper amplifier for eliminating the cultural waves and the rotary switch circuit use a synchronous clock signal generator as a clock signal source, and the chopper amplifier for eliminating the cultural waves comprises a circuit for eliminating the cultural waves and is used for inhibiting the cultural waves. The technical scheme realizes high bandwidth, high response speed, high measurement accuracy, low noise and small offset voltage.

Description

Hall sensing circuit

Technical Field

The invention belongs to the field of measurement, and particularly relates to an improvement on a Hall sensing circuit.

Background

Current monitoring is widely used in high power circuit systems, such as motor or load control, inverter circuits, power factor correction and power monitoring systems, and the like. In these systems, current of several amperes to hundreds or even thousands of amperes is required to be monitored, and the conventional current monitoring method for monitoring the voltage across the resistor in series can cause great energy loss.

High current systems are typically monitored using hall sensors. According to the magnetic effect of current, a magnetic field proportional to the current is formed around a wire with current, the magnitude of the magnetic field can be detected through the Hall effect, and then the magnitude of the current in the wire is monitored, and the current monitoring system based on the electromagnetic effect is widely applied to high-power circuit systems. Hall sensors are an important component in magnetic sensors among others. Compared with other magnetic sensors, the Hall sensor has the characteristics of high linearity and good consistency, but has the advantages of general sensitivity, large offset voltage relative to induction signals and serious limitation on the measurement accuracy of the Hall sensor.

Methods for reducing the influence of offset voltage of a hall sensor on measurement are mainly divided into two types, namely a static method and a dynamic method. The static method adopts a mode that a plurality of Hall sensors are connected in parallel to offset the offset voltages of the Hall sensors, but the effect is general, and the offset voltage close to the amplitude of the induction signal is remained in the method. The dynamic method can modulate the offset voltage of the hall sensor to high frequency to become a high-frequency Ripple superimposed on the signal, and some methods are still needed to eliminate the Ripple (Ripple).

The dynamic method is divided into two types according to the processing method of the cultural wave signal. There are two main approaches to the common approach, the first using a low pass filter for filtering and the second using a sample-based trap for removal.

Referring to fig. 1 and 2, using a low pass filter LPF scheme, the dynamic approach employs a rotary switch circuit 104 to energize two of the four ports of the hall sensor 102 with a clock CLK/CLKN or periodic rotation, and correspondingly voltage detect the other two ports. The excitation port is driven by the CLK clock signal and the output port is driven using the CLK clock inversion signal CLKN.

The output waveform Vo1 includes two parts. The first part is the signal voltage Vh induced by the Hall, the other part is the offset voltage Vos modulated by the Hall, which is converted into a high-frequency signal, the high-frequency signal is represented as a square wave at the rotating frequency, and the effective signal frequency of the Hall sensor is unchanged by Vh. Vo1 is amplified by a Low Offset Amp 106 (Low Offset Amp) at the subsequent stage to output Vo2, and Vo2 is filtered by a Low Pass Filter (LPF) at the subsequent stage to output (via the VOP/VON port). A Low Pass Filter (LPF) 108 filters out the modulated offset voltage and retains the signal Vo3.

In order to suppress the ripple caused by Vos cleanly, the bandwidth of the LPF needs to be much smaller than the rotation frequency, which limits the signal bandwidth, and also slows down the response speed of the signal path and has long response time. In order to suppress the ripple better, a second-order or higher-order low-pass filter is required, which worsens the response speed even more.

Referring to fig. 3, a low pass Filter is used to employ a Notch Filter (NF) 110 scheme. Unlike low pass filters, which filter out ripple with a trap rather than a low pass filter, the trap filters out ripple with a much higher efficiency than the low pass filter.

The notch filter 110 has an effect on notch frequency points, and when notch frequency and SPIN Freq are identical, the notch can be effectively filtered, and if the two frequencies have a difference, the filtering effect is greatly reduced. Therefore, the notch filter is generally realized by using a switched capacitor sampling method, and the sampling frequency is synchronous with the SPIN Freq, so that the notch frequency and the SPIN Freq are identical. However, switched capacitor sampling can cause noise aliasing, exacerbate in-band noise, and limit response time, which is limited by the sampling frequency and slow in response, to change when the sampling clock is flipped.

Disclosure of Invention

In order to solve the technical problems, the invention aims to realize a Hall sensor circuit which has the advantages of no limitation of response speed, no aliasing noise, low offset voltage, low noise and high response speed while removing ripples.

The Hall sensing circuit of the present invention comprises: the device comprises a Hall sensor, a rotary switch circuit, a synchronous clock signal generator and a chopper amplifier for eliminating the Wen waves;

the rotary switch circuit is connected with the Hall sensor, and periodically excites two ports in the Hall sensor and simultaneously receives output signals of the other two ports;

the rotary switch circuit outputs the output signal of the Hall sensor to the venturi wave elimination chopper amplifier; the chopper amplifier for eliminating the Wen wave and the rotary switch circuit use a synchronous clock signal generator as a clock signal source;

the chopper amplifier for eliminating the Wen wave comprises a Wen wave eliminating loop and a differential amplifier which is composed of a first operational amplifier and a second operational amplifier;

the first operational amplifier or the second operational amplifier comprises a first feedback port, and the first feedback port is connected with the output end of the Wen wave elimination loop;

and the input end of the cultural wave elimination loop is connected with the output ends of the first operational amplifier and the second operational amplifier.

As a further improvement of an embodiment of the present invention, the first operational amplifier and the second operational amplifier include a first amplifier, a second amplifier, and a first negative feedback transconductance amplifier;

the first amplifier comprises a first transconductance amplifier and a first chopper connected with the input end of the first transconductance amplifier; the second amplifier comprises a second transconductance amplifier and a second chopper connected with the input end of the second transconductance amplifier;

the input end of the first chopper is used as the input end of the operational amplifier, and the input end of the second chopper is connected with the output end of the first transconductance amplifier; the input end of the first negative feedback transconductance amplifier is connected with the first feedback port of the operational amplifier, and the output end of the first negative feedback transconductance amplifier is connected with the output end of the first transconductance amplifier.

As a further improvement of one embodiment of the invention, the rotary switch circuit periodically 2-phase energizes the hall sensor.

As a further improvement of an embodiment of the present invention, the first operational amplifier and the second operational amplifier further include a second negative feedback transconductance amplifier, a third chopper, and a second feedback port;

the input end of the second negative feedback transconductance amplifier is connected with the second feedback port, and the second negative feedback transconductance amplifier is connected with the input end of the second transconductance amplifier through a third chopper.

As a further improvement of an embodiment of the present invention, the chopper amplifier for removing the cultural waves includes a cultural wave removing loop, and the second feedback port is connected with the output end of the cultural wave removing loop;

As a further improvement of an embodiment of the present invention, the rotary switch circuit periodically 4-phase energizes the hall sensor; or periodically 2-phase excited hall sensors, wherein the ripple cancellation loop, the second transconductance amplifier, and the third chopper are electrically shielded.

As a further improvement of an embodiment of the present invention, for "periodic 4-phase excitation hall sensor", the synchronous clock signal generator generates: a first clock and a first clock inversion signal drive the first chopper and the second chopper;

for a "periodically 2-phase excited hall sensor", the synchronous clock signal generator generates: a first clock and a first clock inversion signal drive the first chopper and the second chopper and a second clock inversion signal drive the third chopper;

wherein the clock period of the second clock is twice the clock period of the first clock.

As a further improvement of an embodiment of the present invention, the output ends of the first operational amplifier and the second operational amplifier are connected in series with three resistors; the input end of the first operational amplifier is connected with the first end of the second resistor, and the input end of the second operational amplifier is connected with the first end of the third resistor.

As a further improvement of an embodiment of the present invention, the venturi cancellation loop includes:

the first Wen wave elimination loop comprises a chopper and an integrator, wherein the chopper ch is connected with the input end of the integrator Int;

or comprises:

the second venturi cancellation loop comprises a chopper, an integrator and a preamplifier; the chopper is connected with the input end of the integrator Int; the output end of the preamplifier is connected with the input end of the chopper;

or comprises:

the third venturi cancellation loop comprises a chopper, an integrator, a preamplifier and a high-pass filter, wherein the high-pass filter is connected with the input end of the preamplifier; the output end of the preamplifier is connected with the input end of the chopper; the chopper is connected with the input end of the integrator;

or comprises:

the fourth venturi cancellation loop comprises a chopper, a transconductance amplifier and a transconductance integrator, wherein the output end of the chopper is connected with the input end of the transconductance amplifier, and the output end of the transconductance amplifier is connected with the input end of the transconductance integrator;

or comprises:

the fifth venturi cancellation loop comprises a chopper, a transconductance amplifier and a transconductance integrator, wherein the input end of the chopper is connected with the output end of the transconductance amplifier, and the output end of the chopper is connected with the input end of the transconductance integrator.

As a further improvement of an embodiment of the present invention, the chopper includes a first switch group connected to the input/output end in the forward direction and a second switch group connected to the input/output end in the reverse direction, where the driving clock source of the first switch group is a first clock or a second clock; the second switch group drives the clock source to be a first clock inversion signal or a second clock inversion signal, and the chopper output signal is continuously commutated along with the clock signal.

Compared with the prior art, the invention realizes the effect of removing the ripple signal by the chopper amplifying circuit and the synchronous clock without limiting the response speed and aliasing noise at the same time, and realizes a Hall sensor circuit with low offset voltage, low noise and high response speed.

Drawings

FIG. 1 is a schematic block diagram of a prior art Hall sensor rotation excitation combined with a low pass filter and low pass amplifier;

FIG. 2 is a signal timing diagram of a prior art Hall sensor rotation excitation combined with a low pass filter and low pass amplifier;

FIG. 3 is a prior art Hall sensor rotation excitation combined low pass filter and trap scheme frame diagram;

FIG. 4 is a frame diagram of a Hall sensor rotational excitation scheme of the present application;

FIG. 5 is a schematic diagram of a rotary switch circuit configuration of the present application;

FIG. 6 is a timing diagram of a two-phase excitation clock signal and switch control of the present application;

FIG. 7 is a timing diagram of a four-phase excitation clock signal and switch control of the present application;

FIG. 8 is a schematic diagram of a first embodiment of a Wen wave cancellation chopper amplifier;

FIG. 9 is a schematic diagram of five embodiments of a Wenwave cancellation loop;

FIG. 10 is a schematic view of a chopper structure;

FIG. 11 is a schematic diagram of a second embodiment of a Wen wave cancellation chopper amplifier;

fig. 12 is a schematic diagram of an operational amplifier implementation in a venturi-elimination chopper amplifier.

Detailed Description

The following detailed description of preferred embodiments of the present invention is provided in connection with the accompanying drawings to assist those skilled in the art in understanding the present invention. "group" is used in this application to represent multiple same type of electronic device, e.g., a sampling capacitor group represents multiple sampling capacitors, and a switch group represents multiple switches that are functionally identical or switches that are driven by the same clock. In this application, "input" means a positive input port and a negative input port, and "output" means a positive output port and a negative output port.

Referring to the Hall sensing circuit frame structure shown in fig. 4, a Hall sensor (Hall) 402 and associated circuitry coupled to the Hall sensor 402, and circuitry for processing the Hall sensor 402 signal are included. A hall sensing circuit, a venturi cancellation chopper amplifier 406, shown as a single hall sensor 402, is included, and a plurality of hall sensors 402 may optionally be connected in parallel by one skilled in the art to further reduce offset signals.

The hall sensing circuit includes a hall sensor 402, a rotary switching circuit 404, and a ripple cancellation chopper amplifier 406 in combination. The hall sensor 402 includes four ports, two of which are used for inputting excitation signals and the other two ports are used for outputting sensing signals. The four ports of the hall sensor 402 are connected to the first, second, third, and fourth ports (a, b, c, d) of the rotary switch circuit 404, respectively. The rotary switch circuit 404 periodically energizes two ports in the hall sensor 402 while receiving output signals of the other two ports; the rotary switch circuit 404 outputs signals output from the other two ports to the chopper amplifier 406 for eliminating the venturi; the ripple cancellation chopper amplifier 406 and rotary switch circuit 404 use a synchronous clock signal generator 408 as a clock signal source.

At least one chopper circuit in the chopper amplifier 406 can eliminate the chopper signal, and the chopper amplifier 406 and the rotary switch circuit 404 use synchronous clock signals as driving signal source signals to generate and process synchronous response speed is good.

Referring to fig. 5, a schematic diagram of an embodiment of a rotary switch circuit 404 is shown, wherein switches with the same reference number are switch groups with the same operation timing, i.e., are simultaneously on or simultaneously off. The operation sequence of the label with the S suffix is the same as that of the label without the S suffix, for example, the operation sequence of P1/P1S, P/P2S is the same.

The rotary switch circuit 404 is composed of an excitation switch group 502 that controls the excitation signal and a sense signal output switch group 504. The hall sensor 402 includes a first port a, a second port b, a third port c, and a fourth port d; the excitation switch group 502 includes: a first switch group P1 for forming an excitation signal loop at a first port a and a third port c, and a second switch group P2 for forming an excitation loop at a second port b and a fourth port d; a third group of switches P3 for forming an excitation signal loop at the third port c and the first port a and a fourth group of switches P4 for forming an excitation signal loop at the fourth port d and the second port b; the output switch group 504 includes: a first output switch group P1S for forming an output loop at the second port b and the fourth port d, and a second output switch group P2S for forming an output loop at the third port c and the first port a; a third output switch group P3S for forming an output loop at the fourth port d and the second port and a fourth switch group P4S for forming an output loop at the first port a and the third port c. The first to fourth switch groups respectively comprise a switch connected with the excitation signal port and a ground switch. The specific connection modes of the excitation switch group 502 and the output switch group 504 and the switches are as follows: (for brevity, only the switch labels are identified) a first port a is connected to P1, P3, P4S, P S, a second port b is connected to P2, P4, P1S, P S, a third port c is connected to P3, P1, P2S, P S, and a fourth port d is connected to P4, P2, P3S, P S.

The output switch group 504 of the rotary switch circuit 404 is connected to an output capacitor Cs, a first pole of the output capacitor Cs is the positive output terminal VOP of the rotary switch circuit 404, and a second pole of the output capacitor Cs is the negative output terminal VON of the rotary switch. The output capacitor Cs is configured to sample an output voltage generated by the hall sensor 402, where the output voltage Vo1 is a summation value of the Vh voltage and Vos of the effective signal of the hall sensor 402.

The rotary switch circuit 404 performs four-phase or two-phase excitation on the hall sensor 402 under the action of the excitation switch group 502 and the output switch group 504 under the action of the switch control timing sequence, and receives signals through two other ports except the excitation ports. The following table is prepared according to the mapping relation between the phase and the excitation port and direction, the sampling port and direction, the signal direction and the offset voltage direction:

in the table, "+," indicates the directions of the table hall voltage Vh and offset voltage Vos, and "- >" indicates the voltage direction of the excitation port or the output port.

Fig. 5 and 6 are clock signals generated by the synchronous clock signal generator 408, and control timings of the above-described switch components. The synchronous clock signal generator 408 generates a first clock C1 and a second clock C2, the clock C2 period of the second clock being twice the clock C1 period of the first clock. The activation process of the rotary switch circuit 404 is further described below in conjunction with a clock and control timing.

Fig. 6 shows a control sequence of the two-phase rotary switch, and the synchronous clock signal generator 408 generates the clock signal C1 and the clock signal inversion driving signal C1N. In the first clock period t1, the switches P1 and P1S are closed, the excitation ports and directions are a-c, the first port a and the third port c form an excitation loop, the output ports and directions are b-d, and the Hall voltage Vh and the offset voltage Vos are both output in the forward direction. In the second clock period t2, the switches P1 and P1S are opened, the switches P2 and P2S are closed, the excitation ports and the directions are b-d, namely, the second port b and the fourth port d form an excitation loop, the output ports and the directions c-a are output, the direction of the Hall voltage Vh is positive output, and the direction of the offset voltage Vos is negative output.

Therefore, the offset voltage Vos changes along with the direction of the clock signal C1, the signal is modulated into a high-frequency signal with the same frequency as the clock signal, and the high-frequency signal is superimposed on the hall voltage Vh signal in a mode of a text wave signal to form a rotary switch circuit output signal Vo1, and the high-frequency signal is convenient for processing in modes of filtering and the like.

In fig. 6, the switches P3, P4, P3S and P4S are always kept in an off state, i.e. the excitation signals of the two phases c- > a.d- > b and their corresponding output signals are shielded by means of control timing. The four-phase rotary switch circuit 404 in fig. 7 further includes the two-phase excitation signal and the corresponding output signal.

Four different timings are included in the four-phase rotary switch circuit 404. The operation timing of the excitation switch group 502 and the output switch group 504 in the first clock period t1 and the second clock period t2 is different from that of the two-phase rotary switch shown in fig. 3. In a third clock period t3, the P3 and the P3S are closed, the excitation port and the direction are c- > a output port and the direction is d- > b; and in the four clock period t4, the P4 and P4S closed excitation ports and directions are d- > b, and the output ports and directions are a- > c. It can be seen that the sign of the offset signal Vos output from the 4-phase rotary switch circuit 404 changes with the direction of the clock signal, and is superimposed on the hall voltage Vh signal in the manner of a text wave signal to form a four-phase rotary switch circuit output signal Vo1.

It should be noted that, whether it is a two-phase rotary switch circuit or a four-phase rotary switch circuit, there is a certain time delay for the control timing of the excitation and output switch groups (as indicated by the reference numerals d1 to d4 in fig. 6 and 7). The falling edge of the output switch set P1S-P4S is slightly ahead of the corresponding stimulus P1-P4, and the rising edge is slightly behind the corresponding stimulus P1-P4. Since the falling/rising edges of P1-P4 mean that the switch is in the switching process, and the output of the HALL is not established at this time, the P1S-P4S has a dead time at the position corresponding to the edges of P1-P4, so that the error caused by the amplification of the non-established output of the HALL by the later sampling is avoided. At the same time, the clock of the post-stage ripple cancellation chopper amplifier needs to be aligned with the falling edges of P1S-P4S, so that the modulated Vh can be well suppressed by the ripple cancellation loop of the post-stage amplifier.

Referring to fig. 4 and 8, positive and negative input ports (VIP, VIN) of the venturi-removing chopper amplifier 406 are respectively connected to positive and negative output ports (VOP, VON) of the rotary switch circuit 404. The Wen wave cancellation chopper amplifier 406 includes a variety of implementations, two exemplary implementations being illustrated.

Fig. 8 is a schematic diagram of a first implementation of the Wen wave cancellation chopper amplifier 406. Which includes a first amplifier 802, a second amplifier 804, and a first negative feedback circuit 806 in series; the first amplifier 802 includes a first transconductance amplifier GM1 and a first chopper ch1 connected to an input terminal of the first transconductance amplifier GM1, where the input terminal of the first chopper ch1 is used as an input terminal of the chopper amplifier 406 for eliminating the ripple wave, and the chopper ch1 is used to eliminate the offset voltage of the first transconductance amplifier GM 1.

The second amplifier 804 includes a second transconductance amplifier GM2 and a second chopper ch2 connected to an input terminal of the second transconductance amplifier GM 2; the input end of the second chopper ch2 is connected with the output end of the first transconductance amplifier GM 1; an input terminal of the first negative feedback circuit 806 is connected to an output terminal of the second transconductance amplifier GM2.

The first negative feedback circuit 806 is configured to suppress the output of the second transconductance amplifier GM2 ripple. The output end of the transconductance amplifier GMa is used as the output end 806 of the first negative feedback circuit. The input end of the transconductance amplifier GMa is connected with the output end of the ripple cancellation loop RRL, the ripple signal in the output signal is acquired by the ripple cancellation loop RRL to be demodulated and amplified, and the ripple signal is negatively fed back to the output port of the first transconductance amplifier GM1 through the transconductance amplifier GMa to inhibit the ripple output by the second transconductance amplifier GM2.

In fig. 8, if the rotary switch circuit 404 performs four-phase sampling, the chopper amplifier 406 for removing the ripple should further include a second negative feedback circuit 808, where an input terminal of the second negative feedback circuit 808 is connected to an output terminal of the second transconductance amplifier GM2, and an output terminal of the second negative feedback circuit 808 is connected to an input terminal of the second transconductance amplifier GM2. The structure of the second negative feedback circuit 808 is the same as that of the first negative feedback circuit 806, the output end of the cultural wave eliminating circuit RRL is connected with the input end of the third chopper ch3, and the output end of the third chopper ch3 is connected with the input end of the second-stage transconductance amplifier GM2.

For the four-phase rotary switch circuit, the first chopper ch1 and the second chopper ch2 are driven by the first clock C1 and the first clock inversion signal C1N, the clock period of the second clock signal C2 is twice that of the first clock signal C1, and the second clock signal C2 and the second clock inversion signal C2N are used for driving the third chopper. So that the ripple cancellation path of the second negative feedback circuit 808 can effectively suppress the ripple at the rotation frequency of one half. For a dual phase rotary switch circuit, the second negative feedback circuit 808 may be eliminated or electrically turned off.

Referring to fig. 9, which illustrates a typical implementation of a ripple cancellation loop RRL, the common feature of the implementation is that the implementation is mainly composed of a chopper and an integrator, the chopper can demodulate the ripple in the output signal back to DC, the integrator amplifies the ripple and feeds back the ripple to the signal path, and the RRL can suppress the output ripple of the amplifier to be negligible relative to the hall signal through the negative feedback effect.

With continued reference to fig. 9, the first venturi-elimination loop 902 includes a chopper ch and an integrator Int, the chopper ch being connected to an input of the integrator Int. The second arable cancellation loop 904 adds a preamplifier GM2 with its output connected to the input of the chopper ch on the basis of the first arable cancellation loop RRL.

For the first ripple cancellation loop 902, the residual ripple is determined by the offset voltage of the amplifier in the integrator Int, and a pre-amplifier GM2 is added before the chopper ch, so that the ripple can be further reduced to the extent that the ripple is suppressed by the gain of the pre-amplifier GM2 at the chopping frequency.

The third venturi cancellation loop 906 adds a high pass filter HPF in addition to the second venturi cancellation loop 904, the high pass filter HPF being connected to the pre-amplifier AO input. The high pass filter HPF is an RC structure as shown in the figure. The high pass filter HPF may allow the high frequency ripple signal to pass and block the hall signal Vh before the pre-amplifier so that the RRL processes the hall signal Vh less, only the ripple. As for the hall signal Vh, since the frequency thereof is lower than the chopping frequency, it is modulated to the chopping frequency by the chopper ch and is suppressed by the low-pass characteristic of the integrator Int when passing through the integrator, so that the RRL does not feed back the useful hall signal Vh, but feeds back the ripple and suppresses the ripple.

The fourth arable cancellation loop 908 arable cancellation loop comprises a chopper ch, a transconductance amplifier GM1' and a transconductance integrator Int ', wherein the output end of the chopper ch is connected with the input end of the transconductance amplifier GM1', and the output end of the transconductance amplifier GM1' is connected with the input end of the transconductance integrator Int '.

The fifth venturi cancellation loop 910 includes a chopper ch, a transconductance amplifier GM1', and a transconductance integrator Int', where an input terminal of the chopper ch is connected to an output terminal of the transconductance amplifier GM1', and an output terminal of the chopper ch is connected to an input terminal of the transconductance integrator Int'. The chopper ch of the fifth venturi cancellation loop 910 may be moved from the input to the output across the amplifier to help reduce the residual ripple amplitude.

Referring to the implementation manner of the chopper shown in fig. 10, the implementation manner includes a first switch group S1 connected to the input and output terminal in a forward direction and a second switch group S2 connected to the input and output terminal in a reverse direction, the driving clock source of the first switch group is C1 or C2, the driving clock source of the second switch group is C1N or C2N correspondingly, and the switching action output signal of the chopper is continuously commutated along with the clock signal.

Fig. 11 shows a second implementation of the venturi-elimination chopper amplifier 406, wherein the implementation of the chopper and the venturi-elimination loop RRL is the same as the implementation of the first-mentioned venturi-elimination chopper amplifier 406.

The chopper amplifier 406 includes a differential amplifier composed of a first operational amplifier OPAMP1 and a second operational amplifier OPAMP2, and a chopper loop RRL. The output ends of the first operational amplifier OPAMP1 and the second operational amplifier OPAMP2 are connected in series with three resistors (R1, R2 and R3); the input end of the first operational amplifier OPAMP1 is connected with the second resistor R2, and the input end of the second operational amplifier OPAMP2 is connected with the third resistor R3; the first operational amplifier OPAMP1 or the second operational amplifier OPAMP2 includes a first feedback port VIP1/VIN1, the positive input terminal VIP1 and the negative input terminal VIN1 of the first feedback port VIP1/VIN1 are respectively connected with the positive output terminal VOP and the negative output terminal VON of the venturi-eliminating loop RRL, and the positive input terminal VIP and the negative input terminal VIN of the venturi-eliminating loop RRL are connected with the output terminals of the first operational amplifier OPAMP1 and the second operational amplifier OPAMP 2.

The first operational amplifier OPAMP1 and the second operational amplifier OPAMP2 described with reference to fig. 12 include a first amplifier 1202, a second amplifier 1204, and a first negative feedback transconductance amplifier GMa; the first amplifier 1202 includes a first transconductance amplifier GM1 and a first chopper ch1 connected to an input terminal of the first transconductance amplifier GM1, and the second amplifier 1204 includes a second transconductance amplifier GM2 and a second chopper ch2 connected to an input terminal of the second transconductance amplifier GM 2; the input end of the first chopper ch1 is used as the input end of an operational amplifier, and the input end of the second chopper ch2 is connected with the output end of the first transconductance amplifier GM 1; the input end of the first negative feedback transconductance amplifier Gma is connected with a first feedback port VIP1/VIN1 of the operational amplifier, and the output end of the first negative feedback transconductance amplifier Gma is connected with the output end of the first transconductance amplifier GM 1.

Referring to fig. 11 and 2, if the rotary switch circuit is 4-phase excited, the operational amplifier further includes a cultural wave cancellation loop RRL 'connected to the second feedback port VIP2/VIN2, and an input terminal of the cultural wave cancellation loop RRL' is connected to the output terminals of the first operational amplifier OPAMP1 and the second operational amplifier OPAMP 2. Correspondingly, the first operational amplifier OPAMP1 and the second operational amplifier OPAMP2 comprise a second negative feedback transconductance amplifier GMb with an input end connected with the second feedback port VIP2/VIN2, and the second negative feedback transconductance amplifier GMb is connected with an input end of the second transconductance amplifier Gm2 through a third chopper ch 3; a first clock C1 and a first clock inversion signal C1N drive the first chopper ch1 and the second chopper ch2; the second clock C2 and the second clock inversion signal C2N drive the third chopper ch3. The cultural wave cancellation loop RRL', the second transconductance amplifier Gmb and the third chopper ch3 may be electrically shielded or deleted from the circuit if the rotary switch circuit is 2-phase excited.

In summary, the invention uses the ripple cancellation loop in the post-stage ripple cancellation chopper amplifier to cancel the offset voltage modulated by the hall element in cooperation with the switching clock and clock edge of the post-stage ripple cancellation chopper amplifier. The two-phase rotary switch circuit and the four-phase rotary switch circuit can be compatible through reasonable switching sequences. Ripple waves at the rotation frequency and half the rotation frequency are respectively restrained through 2 loops, and ripple waves caused by four-phase rotation can be effectively eliminated.

The invention has the advantages that the low-pass or high-order low-pass filter with low cut-off frequency is not added in the signal path, the switch sampling circuit is not added, the bandwidth and delay time of the signal path are not influenced, the noise aliasing effect caused by the switch sampling is not generated, the high bandwidth is realized, the response speed is high, the measurement precision is high, the noise is small, and the offset voltage is small. The measuring precision and the delay time are short enough, when the detected system current flows excessively, the system can quickly receive an overcurrent signal and start protective measures to protect the safety of the whole system.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.

Claims

1. A hall sensing circuit comprising: a hall sensor (402), a rotary switch circuit (404), a synchronous clock signal generator (408) and a chopper amplifier (406) for eliminating the ripple;

the rotary switch circuit (404) is connected with the Hall sensor (402), and the rotary switch circuit (404) periodically excites two ports in the Hall sensor (402) and simultaneously receives output signals of the other two ports;

the rotary switch circuit (404) outputs an output signal of the Hall sensor (402) to the venturi cancellation chopper amplifier (406); the venturi cancellation chopper amplifier (406) and rotary switching circuit (404) use a synchronous clock signal generator (408) as a clock signal source;

the chopper amplifier (406) for removing the cultural waves comprises a cultural wave removing loop (RRL), and a differential amplifier composed of a first operational amplifier (OPAMP 1) and a second operational amplifier (OPAMP 2);

the first operational amplifier (OPAMP 1) or the second operational amplifier (OPAMP 2) comprises a first feedback port (VIP 1/VIN 1), and the first feedback port (VIP 1/VIN 1) is connected with the output end of the cultural wave elimination loop (RRL);

the input end of the cultural wave elimination loop (RRL) is connected with the output ends of the first operational amplifier (OPAMP 1) and the second operational amplifier (OPAMP 2);

the first operational amplifier and the second operational amplifier comprise a first amplifier (1202), a second amplifier (1204) and a first negative feedback transconductance amplifier (GMa);

the first amplifier (1202) comprises a first transconductance amplifier (GM 1) and a first chopper (ch 1) connected with the input end of the first transconductance amplifier (GM 1); the second amplifier 1204 comprises a second transconductance amplifier (GM 2) and a second chopper (ch 2) connected to the input terminal of the second transconductance amplifier (GM 2);

an input end of the first chopper (ch 1) is used as an input end of an operational amplifier (OPAMP 1/OPAMP 2), and an input end of the second chopper (ch 2) is connected with an output end of the first transconductance amplifier (GM 1); the input end of the first negative feedback transconductance amplifier (GMa) is connected with a first feedback port (VIP 1/VIN 1) of the operational amplifier (OPAMP 1/OPAMP 2), and the output end of the first negative feedback transconductance amplifier (GMa) is connected with the output end of the first transconductance amplifier (GM 1);

the first operational amplifier and the second operational amplifier further comprise a second negative feedback transconductance amplifier (GMb), a third chopper (ch 3) and a second feedback port VIP2/VIN2;

the input end of the second negative feedback transconductance amplifier (GMb) is connected with the second feedback port (VIP 2/VIN 2), and the second negative feedback transconductance amplifier (GMb) is connected with the input end of the second transconductance amplifier (GM 2) through the third chopper (ch 3).

2. The hall sensing circuit of claim 1, wherein the rotary switch circuit (404) periodically 2-phase energizes the hall sensor (402).

3. The hall sensing circuit according to claim 1, wherein the venturi cancellation chopper amplifier (406) comprises a venturi cancellation loop (RRL '), the second feedback port (VIP 2/VIN 2) being connected to the venturi cancellation loop (RRL') output;

the input end of the cultural wave elimination loop (RRL') is connected with the output ends of the first operational amplifier (OPAMP 1) and the second operational amplifier (OPAMP 2).

4. A hall sensing circuit according to claim 3, wherein the rotary switch circuit (404) periodically 4-phase energizes the hall sensor (402); or periodically 2-phase excited hall sensor (402), wherein the ripple cancellation loop (RRL'), the second transconductance amplifier (GMb), and the third chopper (ch 3) are electrically shielded.

5. The Hall sensing circuit according to claim 4, wherein,

for "periodically 4-phase excited hall sensor (402)", the synchronous clock signal generator (408) generates: a first clock (C1) and a first clock inversion signal (C1N) driving the first chopper (ch 1) and the second chopper (ch 2);

for "periodically 2-phase excited hall sensor (402)", the synchronous clock signal generator (408) generates: a first clock (C1) and a first clock inversion signal (C1N) drive the first chopper (ch 1) and the second chopper (ch 2), and a second clock (C2) and a second clock inversion signal (C2N) drive the third chopper (ch 3);

wherein the clock period of the second clock (C2) is twice the clock period of the first clock (C1).

6. A hall sensing circuit according to claim 3, characterized in that the output terminals of the first operational amplifier (OPAMP 1) and the second operational amplifier (OPAMP 2) are connected in series with three resistors (R1, R2, R3); the input end of the first operational amplifier (OPAMP 1) is connected with the first end of the second resistor (R2), and the input end of the second operational amplifier (OPAMP 2) is connected with the first end of the third resistor (R3).

7. A hall sensing circuit according to claim 1 or 3, wherein the venturi cancellation loop (RRL/RRL') comprises:

a first venturi cancellation loop (902) comprising a chopper (ch) and an integrator (Int), the chopper (ch) being connected to an input of the integrator (Int);

or comprises:

a second venturi cancellation loop (904) comprising a chopper (ch), and an integrator (Int) and a preamplifier (GM 2'); the chopper (ch) is connected with the input end of the integrator (Int); the output end of the preamplifier (GM 2') is connected with the input end of the chopper (ch);

or comprises:

a third venturi cancellation loop (906) comprising a chopper (ch), and integrator (Int), a pre-Amplifier (AO) and a High Pass Filter (HPF); a High Pass Filter (HPF) is connected to the input of the pre-Amplifier (AO); the output end of the preamplifier (AO) is connected with the input end of the chopper (ch); the chopper (ch) is connected with the input end of the integrator (Int);

or comprises:

a fourth venturi cancellation loop (908) comprising a chopper (ch), a transconductance amplifier (GM 1 ') and a transconductance integrator (Int'); the output end of the chopper (ch) is connected with the input end of the transconductance amplifier (GM 1 '), and the output end of the transconductance amplifier (GM 1 ') is connected with the input end of the transconductance integrator (Int ');

or comprises:

the fifth venturi cancellation loop (910) comprises a chopper (ch), a transconductance amplifier (GM 1 ') and a transconductance integrator (Int'), wherein the input end of the chopper (ch) is connected with the output end of the transconductance amplifier (GM 1 '), and the output end of the chopper (ch) is connected with the input end of the transconductance integrator (Int').

8. The hall sensing circuit according to claim 7, wherein the chopper (ch) comprises a first switch group (S1) connected to the input/output terminal in the forward direction and a second switch group (S2) connected to the input/output terminal in the reverse direction, and the first switch group (S1) drives the clock source to be the first clock (C1) or the second clock (C2); the second switch group (S2) drives the clock source to be a first clock inversion signal (C1N) or a second clock inversion signal (C2N), and the chopper output signal is continuously commutated along with the clock signal.