CN115580241B - Power amplifier and bias circuit thereof - Google Patents
Power amplifier and bias circuit thereof Download PDFInfo
- Publication number
- CN115580241B CN115580241B CN202211576053.9A CN202211576053A CN115580241B CN 115580241 B CN115580241 B CN 115580241B CN 202211576053 A CN202211576053 A CN 202211576053A CN 115580241 B CN115580241 B CN 115580241B
- Authority
- CN
- China
- Prior art keywords
- transistor
- circuit
- electrically connected
- current
- pole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000003321 amplification Effects 0.000 claims abstract description 41
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 41
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 38
- 230000006641 stabilisation Effects 0.000 claims abstract description 6
- 238000011105 stabilization Methods 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 27
- 230000001105 regulatory effect Effects 0.000 claims description 22
- 230000033228 biological regulation Effects 0.000 claims description 3
- 230000006835 compression Effects 0.000 description 13
- 238000007906 compression Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 6
- 230000003247 decreasing effect Effects 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 102100039435 C-X-C motif chemokine 17 Human genes 0.000 description 1
- 101000889048 Homo sapiens C-X-C motif chemokine 17 Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a power amplifier and a bias circuit thereof, comprising a micro-current source circuit, a current amplifying circuit, a differential amplifying circuit and a voltage stabilizing output circuit; the direct current power supply is used for outputting a direct current voltage signal to the micro-current power supply circuit, the current amplifying circuit, the differential amplifying circuit and the voltage stabilizing output circuit; the micro-current source circuit outputs a reference current signal to a current input end of the current amplifying circuit according to the direct-current voltage signal and outputs a bias voltage signal to a control end of the current amplifying circuit; the current amplifying circuit outputs a first voltage signal to a first input end of the differential amplifying circuit according to the reference current signal, the bias voltage signal and the direct current voltage signal; the differential amplification circuit outputs a second voltage signal to the input end of the voltage stabilization output circuit according to the direct current voltage signal, the first voltage signal and a feedback signal received by the second input end; and the voltage stabilizing output circuit outputs a voltage stabilizing signal to the output end of the biasing circuit according to the second voltage signal and the direct current voltage signal.
Description
Technical Field
The invention relates to the technical field of radio frequency integrated circuits, in particular to a power amplifier and a bias circuit thereof.
Background
In recent years, high performance rf power amplifiers based on CMOS process have been the hot and difficult point of research. On one hand, the radio frequency circuit based on the CMOS process is easy to integrate with a digital circuit, so that the cost of the whole chip is reduced; on the other hand, as the CMOS process enters the deep sub-micron region, the breakdown voltage of the device decreases, limiting the output power of the CMOS power amplifier. The bias voltage of the power amplifier is to provide proper bias voltage or current for each amplifier, determine the static operating point of each stage, and determine its operating state. Conventionally, a bias circuit is commonly used, which has a voltage division type and a reference source type.
In the conventional situation, the voltage division type bias circuit has obvious advantages that the voltage division type bias circuit is simple and easy to implement, but has the defects that the precision is not high, and the bias voltage provided by the bias circuit or the bias current provided by a resistor is influenced by the power supply voltage; for the reference source type bias circuit, the bias circuit has the advantages of high-precision reference voltage and current, and the circuit structure is relatively complex. However, these bias circuits have poor stability and cannot effectively improve the linearity of the power amplifier.
Disclosure of Invention
The invention provides a power amplifier and a bias circuit thereof, which are used for improving the linearity of the power amplifier.
According to an aspect of the present invention, there is provided a bias circuit including: the micro-current source circuit, the current amplifying circuit, the differential amplifying circuit and the voltage stabilizing output circuit are connected in series;
the input end of the micro-current source circuit, the power supply end of the current amplifying circuit, the power supply end of the differential amplifying circuit and the power supply end of the voltage stabilizing output circuit are all electrically connected with a direct-current power supply;
the output end of the micro-current source circuit is also electrically connected with the current input end and the control end of the current amplifying circuit, the output end of the current amplifying circuit is electrically connected with the first input end of the differential amplifying circuit, the second input end of the differential amplifying circuit is electrically connected with the output end of the voltage-stabilizing output circuit, and the output end of the differential amplifying circuit is electrically connected with the input end of the voltage-stabilizing output circuit; the output end of the voltage stabilizing output circuit is electrically connected with the output end of the biasing circuit;
the direct current power supply is used for outputting direct current voltage signals to the micro current source circuit, the current amplifying circuit, the differential amplifying circuit and the voltage stabilizing output circuit;
the micro-current source circuit is used for outputting a reference current signal to the current input end of the current amplifying circuit according to the direct-current voltage signal and outputting a bias voltage signal to the control end of the current amplifying circuit;
the current amplifying circuit is used for outputting a first voltage signal to a first input end of the differential amplifying circuit according to the reference current signal, the bias voltage signal and the direct current voltage signal;
the differential amplification circuit is used for outputting a second voltage signal to the input end of the voltage stabilization output circuit according to the direct current voltage signal, the first voltage signal and a feedback signal received by the second input end;
the voltage stabilizing output circuit is used for outputting the voltage stabilizing signal to the output end of the bias circuit according to the second voltage signal and the direct current voltage signal.
Optionally, the micro-current source circuit includes: the circuit comprises a first resistor, a second resistor, a first transistor and a second transistor;
a first end of the first resistor is electrically connected with the direct current power supply, and a second end of the first resistor is electrically connected with a first end of the second resistor and a control electrode of the first transistor;
the second end of the second resistor is electrically connected with the first pole of the first transistor and the control pole of the second transistor, the first pole of the second transistor is electrically connected with the current input end and the control end of the current amplifying circuit, and the second pole of the first transistor and the second pole of the second transistor are both grounded.
Optionally, the current amplifying circuit includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;
a first pole of the third transistor and a first pole of the fourth transistor are both electrically connected to the dc power supply;
a second pole of the third transistor is electrically connected with a first pole of the fifth transistor, a control pole of the third transistor is electrically connected with a control pole of the fourth transistor, a second pole of the fifth transistor and an output end of the micro-current source circuit, and a control pole of the fifth transistor and a control pole of the sixth transistor are electrically connected with a first reference voltage source;
a second pole of the fourth transistor is electrically connected to the first pole of the sixth transistor, the second pole of the sixth transistor is electrically connected to the first input terminal of the differential amplifier circuit, and the second pole of the sixth transistor is grounded.
Optionally, the current amplifying circuit further includes: a third resistor;
a first end of the third resistor is electrically connected to the second pole of the sixth transistor and the first input end of the differential amplification circuit, and a second end of the third resistor is grounded.
Optionally, the differential amplifier circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;
a first electrode of the seventh transistor and a first electrode of the eighth transistor are both electrically connected with a direct current power supply;
a second pole of the seventh transistor is electrically connected to the first pole of the ninth transistor, and the second pole of the seventh transistor is also electrically connected to the control electrode of the seventh transistor and the control electrode of the eighth transistor;
a second pole of the eighth transistor is electrically connected to the first pole of the tenth transistor, and the second pole of the eighth transistor is also electrically connected to the input terminal of the voltage regulation output circuit;
a second pole of the ninth transistor is electrically connected to the second pole of the tenth transistor and the first pole of the eleventh transistor, and a control pole of the ninth transistor is electrically connected to the output terminal of the current amplification circuit;
a control electrode of the tenth transistor is electrically connected with an output end of the voltage stabilization output circuit;
the second pole of the eleventh transistor is grounded, and the control pole of the eleventh transistor is electrically connected with the second reference voltage source.
Optionally, the voltage regulation output circuit includes a twelfth transistor, a thirteenth transistor and a fourth resistor;
a first electrode of the twelfth transistor is electrically connected with a control electrode of the thirteenth transistor and the output end of the differential amplification circuit, a second electrode of the twelfth transistor is grounded, and a control electrode of the twelfth transistor is electrically connected with a first end of the fourth resistor;
a first pole of the thirteenth transistor is electrically connected to a dc power supply, and a second pole of the thirteenth transistor is electrically connected to the output terminal of the bias circuit, the second input terminal of the differential amplifier circuit, and the second terminal of the fourth resistor.
Optionally, the bias circuit further includes: a fifth resistor;
a first end of the fifth resistor is electrically connected to a second end of the fourth resistor and a second pole of the thirteenth transistor, and a second end of the fifth resistor is electrically connected to an output end of the bias circuit.
According to another aspect of the present invention, there is provided a power amplifier including: a power amplification circuit and the bias circuit described above.
Optionally, the power amplifying circuit includes: the power amplifier comprises a first capacitor, a second capacitor, a power amplification transistor, a sixth resistor, a seventh resistor, a fourteenth transistor and a first inductor;
the base electrode of the power amplification transistor is electrically connected with the radio frequency signal input end through the first capacitor, and the base electrode of the power amplification transistor is also electrically connected with the output end of the bias circuit;
a first end of the first inductor is electrically connected with the direct current power supply, a second end of the first inductor is electrically connected with a radio frequency signal output end and a collector of a fourteenth transistor, an emitter of the fourteenth transistor is electrically connected with a collector of the power amplification transistor, and an emitter of the power amplification transistor is grounded; the base of the fourteenth transistor is electrically connected with the direct current power supply through the sixth resistor, the base of the fourteenth transistor is also grounded through the seventh resistor, and the base of the fourteenth transistor is also grounded through the second capacitor.
Optionally, the power amplifying circuit includes: the circuit comprises a first capacitor, a second capacitor, a first power amplification transistor, a second power amplification transistor, a sixth resistor, a seventh resistor, a fourteenth transistor, a fifteenth transistor, a first inductor and a second inductor;
a first end of the first inductor is electrically connected with the direct-current power supply, a second end of the first inductor is electrically connected with a radio-frequency signal output end and a collector of a fourteenth transistor, a base of the fourteenth transistor is electrically connected with a third reference voltage source, an emitter of the fourteenth transistor is electrically connected with a collector of the first power amplifying transistor, an emitter of the first power amplifying transistor is grounded, a base of the first power amplifying transistor is electrically connected with a radio-frequency signal input end through the first capacitor, and a base of the first power amplifying transistor is also electrically connected with an output end of the bias circuit through the sixth resistor;
the first end of the second inductor is electrically connected with the direct current power supply, the second end of the second inductor is electrically connected with a radio frequency signal output end and a collector of a fifteenth transistor, a base of the fifteenth transistor is electrically connected with a fourth reference voltage source, an emitter of the fifteenth transistor is electrically connected with a collector of the second power amplifying transistor, an emitter of the second power amplifying transistor is grounded, a base of the second power amplifying transistor is electrically connected with a radio frequency signal input end through the second capacitor, and the base of the second power amplifying transistor is further electrically connected with an output end of the bias circuit through the seventh resistor.
The bias circuit provided by the embodiment of the invention is provided with the direct-current power supply for providing direct-current voltage signals for each circuit, and micro-current with smaller current value is provided by the micro-current source circuit, so that the current amplification circuit can amplify the micro-current signals and output first voltage signals to the differential amplification circuit according to the amplified micro-current signals, the differential amplification circuit is used as the feedback circuit, so that the differential amplification circuit can output second voltage signals according to the first voltage signals and the voltage stabilizing signals provided to the output end of the bias circuit on the basis of receiving the direct-current voltage signals, the stability of the voltage stabilizing signals can be ensured, the voltage stabilizing output circuit can further output the voltage stabilizing signals according to the second voltage signals, and the voltage signals at the output end of the bias circuit are used as the feedback signals to regulate the output voltage stabilizing signals, the stability of the voltage stabilizing signals is further ensured, and the linearity of the power amplifier can be effectively improved when the bias circuit is applied to the power amplifier.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a circuit diagram of a bias circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of another bias circuit provided by an embodiment of the present invention;
FIG. 3 is a circuit diagram of yet another bias circuit provided by an embodiment of the present invention;
fig. 4 is a circuit diagram of a power amplifier provided by an embodiment of the invention;
fig. 5 is a graph comparing the output power of a power amplifier provided by an embodiment of the invention;
fig. 6 is a circuit diagram of another power amplifier provided by an embodiment of the invention;
fig. 7 is a graph comparing output power of another power amplifier provided by the embodiment of the invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in other sequences than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a circuit diagram of a bias circuit according to an embodiment of the present invention, and as shown in fig. 1, the bias circuit 10 includes: a micro-current source circuit 11, a current amplifying circuit 12, a differential amplifying circuit 13 and a voltage stabilizing output circuit 14; an input end IN1 of the micro-current source circuit 11, a power supply end VCC1 of the current amplifying circuit 12, a power supply end VCC2 of the differential amplifying circuit 13 and a power supply end VCC3 of the voltage stabilizing output circuit 14 are all electrically connected with a direct current power supply VCC; the output end OUT1 of the micro-current source circuit 11 is electrically connected with the current input end IN2 and the control end CIN of the current amplifying circuit 12, the output end OUT2 of the current amplifying circuit 12 is electrically connected with the first input end IN3 of the differential amplifying circuit 13, the second input end IN4 of the differential amplifying circuit 13 is electrically connected with the output end OUT4 of the voltage stabilizing output circuit, the output end OUT3 of the differential amplifying circuit 13 is electrically connected with the input end IN5 of the voltage stabilizing output circuit 14, and the output end OUT4 of the voltage stabilizing output circuit 14 is electrically connected with the output end VOUT of the bias circuit 10.
The direct current power supply VCC is used for outputting a direct current voltage signal to the micro current source circuit 11, the current amplifying circuit 12, the differential amplifying circuit 13 and the voltage stabilizing output circuit 14; the micro-current source circuit 11 is configured to output a reference current signal to a current input terminal IN2 of the current amplifier circuit 12 according to the dc voltage signal, and output a bias voltage signal to a control terminal CIN of the current amplifier circuit 12; the current amplifying circuit 12 is configured to output a first voltage signal to a first input terminal IN3 of the differential amplifying circuit 13 according to the reference current signal, the bias voltage signal, and the dc voltage signal; the differential amplifying circuit 13 is configured to output a second voltage signal to the input terminal IN5 of the regulated output circuit 14 according to the dc voltage signal, the first voltage signal, and the regulated signal received by the second input terminal IN 4; the regulated output circuit 14 is configured to output a regulated signal to the output terminal VOUT of the bias circuit 10 according to the second voltage signal and the dc voltage signal.
Specifically, the dc power supply VCC can provide a stable dc voltage signal for each circuit, and the micro-current source circuit 11 can output a micro-current signal with a smaller current value to the current input terminal IN2 of the current amplifying circuit 12 according to the dc voltage signal, and can output a bias voltage signal to the control terminal CIN of the current amplifying circuit 12, so that the current amplifying circuit 12 can receive the dc voltage signal provided by the dc power supply VCC according to the bias voltage signal, and can amplify the micro-current signal after receiving the dc voltage signal, so as to output a first voltage signal to the first input terminal IN3 of the differential amplifying circuit 13 according to the amplified micro-current signal. Generally, the base of the power amplifying transistor M1 can receive a radio frequency signal through the first capacitor C1, and the output terminal VOUT of the bias circuit 10 is electrically connected to the base of the power amplifying transistor M1 to be able to provide a bias voltage thereto, so that if the radio frequency signal increases, the voltage signal at the output terminal VOUT of the bias circuit 10 also increases, and if the radio frequency signal decreases, the voltage signal at the output terminal VOUT of the bias circuit 10 also decreases synchronously, thus affecting the base-emitter voltage of the power amplifying transistor M1, and thus affecting the linearity of the power amplifier. IN order to ensure that the bias voltage (i.e. the regulated voltage signal) provided to the input terminal of the power amplifier is relatively stable, i.e. not affected by the rf signal, the differential amplifier circuit 13 may be used as a feedback circuit, and the second input terminal IN4 may be used as a feedback input terminal, which is capable of collecting the regulated voltage signal at the output terminal VOUT of the bias circuit 10, so that the second voltage signal may be output according to the first voltage signal and the regulated voltage signal on the basis that the power supply terminal thereof receives the dc voltage signal, and when the regulated voltage signal is too large, the output second voltage signal may be appropriately reduced, or when the regulated voltage signal is too small, the output second voltage signal may be appropriately increased, so that the regulated voltage signal at the output terminal VOUT of the bias circuit 10 tends to be stable. The voltage stabilizing output circuit 14 can output a voltage stabilizing signal according to the second voltage signal and the dc voltage signal, and meanwhile, can use the signal of the output terminal VOUT of the bias circuit 10 as a feedback signal to adjust the output voltage stabilizing signal, so that the output voltage stabilizing signal is more stable, the stability of the output signal of the bias circuit is further improved, and when the bias circuit is applied to a power amplifier, the linearity of the power amplifier can be effectively improved.
The bias circuit provided by the embodiment of the invention is provided with the direct-current power supply for providing direct-current voltage signals for each circuit, and the micro-current with a smaller current value is provided through the micro-current source circuit, so that the current amplification circuit can amplify the micro-current signals, and output first voltage signals to the differential amplification circuit according to the amplified micro-current signals, and the differential amplification circuit is used as the feedback circuit, so that the differential amplification circuit can output second voltage signals according to the first voltage signals and the voltage stabilizing signals provided to the output end of the bias circuit on the basis of receiving the direct-current voltage signals, so that the stability of the voltage stabilizing signals can be ensured, the voltage stabilizing output circuit can further output the voltage stabilizing signals according to the second voltage signals, and the voltage signals at the output end of the bias circuit are used as the feedback signals to regulate the output voltage stabilizing signals, so that the stability of the voltage stabilizing signals can be further ensured, and when the bias circuit is applied to the power amplifier, the linearity of the power amplifier can be effectively improved.
Alternatively, fig. 2 is a circuit diagram of another bias circuit provided in an embodiment of the present invention, and as shown in fig. 2, the micro-current source circuit 11 includes: the circuit comprises a first resistor R1, a second resistor R2, a first transistor Q1 and a second transistor Q2; a first end of the first resistor R1 is electrically connected to the dc power VCC, and a second end of the first resistor R1 is electrically connected to a first end of the second resistor R2 and a control electrode of the first transistor Q1; a second terminal of the second resistor R2 is electrically connected to a first terminal of the first transistor Q1 and a control terminal of the second transistor Q2, a first terminal of the second transistor Q2 is electrically connected to the current input terminal IN2 and the control terminal CIN of the current amplifying circuit 12, and a second terminal of the first transistor Q1 and a second terminal of the second transistor Q2 are both grounded GND.
Specifically, the first transistor Q1 and the second transistor Q2 are preferably N-type triodes, a first pole of the first transistor Q1 and a first pole of the second transistor Q2 are both collectors, a second pole of the first transistor Q1 and a second pole of the second transistor Q2 are both emitters, and a control pole of the first transistor Q1 and a control pole of the second transistor Q2 are both bases. Assuming that a connection node of the first resistor R1 and the second resistor R2 is a first node a, a connection node of the second resistor R2 and the first transistor Q1 and the second transistor Q2 is a second node b, the first resistor R1, the second resistor R2 and the first transistor Q1 can divide a dc voltage signal provided by the dc power source VCC, and the first node a is electrically connected to a base of the first transistor Q1 to control the first transistor Q1 to be IN a conducting state, and the second node b is connected to a base of the second transistor Q2 to control the second transistor Q2 to be IN a conducting state, so that a micro current can flow through a collector and an emitter of the second transistor Q2, so that the micro current can be transmitted to the current input terminal IN2 of the current amplifying circuit 12, and a voltage is provided between the collector and the emitter of the conducting second transistor Q2, and the inter-electrode voltage can be transmitted to the control terminal CIN of the current amplifying circuit 12 as an inter-electrode bias voltage to control the current amplifying circuit to be IN a conducting state to amplify the micro current.
It can be understood that the current I flowing through the second resistor R2 R2 =(V BE Q1 –V BE Q2 ) R2, wherein V BE Q1 Is the voltage difference between the base and emitter of the first transistor Q1, V BE Q2 Is the voltage difference between the base and emitter of the second transistor Q2. Due to (V) BE Q1 –V BE Q2 ) Is small, so that the current I flowing through the second resistor R2 R2 And is also smaller. Due to I R2 =I C Q1 +I B Q2 In which I C Q1 Is the collector current, I, of the first transistor Q1 B Q2 Is the base current of the second transistor Q2, due to the current I flowing through the second resistor R2 R2 Is small, thereby enabling the collector current I of the first transistor Q1 C Q1 And base current I of second transistor Q2 B Q2 Is also small, so the collector current I of the second transistor Q2 C Q2 And is also small, i.e., capable of supplying a minute current having a small current value.
Alternatively, referring to fig. 2, the current amplifying circuit includes: a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, and a sixth transistor Q6; a first pole of the third transistor Q3 and a first pole of the fourth transistor Q4 are both electrically connected to a dc power supply VCC; a second pole of the third transistor Q3 is electrically connected to a first pole of the fifth transistor Q5, a control pole of the third transistor Q3 is electrically connected to a control pole of the fourth transistor Q4, a second pole of the fifth transistor Q5 and the output terminal OUT1 of the micro-current source circuit 11, and a control pole of the fifth transistor Q5 and a control pole of the sixth transistor Q6 are both electrically connected to the first reference voltage source VB 1; a second pole of the fourth transistor Q4 is electrically connected to a first pole of the sixth transistor Q6, a second pole of the sixth transistor Q6 is electrically connected to the first input terminal IN3 of the differential amplifier circuit 13, and a second pole of the sixth transistor Q6 is grounded GND.
Specifically, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 are preferably P-type MOS transistors, a first electrode of each transistor may be a source electrode, a second electrode of each transistor may be a drain electrode, and a control electrode of each transistor is a gate electrode. The minute current source circuit 11 supplies a bias voltage to the gates of the third transistor Q3 and the fourth transistor Q4, thereby causing the gate-source voltage V of the third transistor Q3 GS Q3 ≤ V TH Q3 Gate-source voltage V of fourth transistor Q4 GS Q4 ≤ V TH Q4 Wherein, V TH Q3 Is the threshold voltage, V, of the third transistor Q3 TH Q4 Is the threshold voltage of the fourth transistor Q4. Thereby enabling the third transistor Q3 and the fourth transistor Q4 to be in a turned-on state. The gates of the fifth transistor Q5 and the sixth transistor Q6 receive a first reference voltage signal provided by a first reference voltage source VB1, which is set to control the fifth transistor Q5 and the sixth transistor Q6 to be in a conducting state. The third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 form a current mirror structure, and can amplify the micro-current flowing through the third transistor Q3 and the fifth transistor Q5, that is, the current flowing through the fourth transistor Q4 and the sixth transistor Q6 is the amplified current signal.
Illustratively, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 constitute a cascode current mirror structure, wherein the third transistor Q3 and the fourth transistor Q4 may be set to have a size ratio of 1: n, capable of amplifying the micro-current signal by N times, and also capable of releasing the gate-source voltage V of the third transistor Q3 in the conventional current mirror, compared to the conventional current mirror structure including only the third transistor Q3 and the fourth transistor Q4 GS Q3 So that the drain-source voltage V of the third transistor Q3 DS Q3 Can reach V GS Q3 -V TH Q3 . By providing the fifth transistor Q5 and the sixth transistor Q6, the fifth transistor Q5 and the sixth transistor Q6 can drain the third transistor Q3The voltage of the electrode is balanced with the voltage of the drain electrode of the fourth transistor Q4, namely the drain-source voltage V of the third transistor Q3 can be ensured DS Q3 And the drain-source voltage V of the fourth transistor Q4 DS Q4 Same, and makes the gate-source voltage V of the third transistor Q3 GS Q3 And the gate-source voltage V of the fourth transistor Q4 GS Q4 Also, the micro-current can be more accurately reproduced and amplified.
Optionally, with continued reference to fig. 2, the current amplifying circuit 12 further includes: a third resistor R3; a first end of the third resistor R3 is electrically connected to the second pole of the sixth transistor Q6 and the first input terminal IN3 of the differential amplifier circuit 13, and a second end of the third resistor R3 is grounded GND.
Specifically, the current flowing from the dc power source VCC through the fourth transistor Q4, the sixth transistor Q6 and the third resistor R3 and grounded is the micro-current amplified by N times, that is, the micro-current is amplified by N times and then output by the sixth transistor Q6, and if the micro-current amplified by N times is the amplified current I0, the voltage provided to the first input terminal IN3 of the differential amplifier circuit 13 is I0 × R3, that is, the value of the first voltage signal is I0 × R3.
Optionally, with continued reference to fig. 2, the differential amplifying circuit 13 includes: a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10, and an eleventh transistor Q11; a first pole of the seventh transistor Q7 and a first pole of the eighth transistor Q8 are both electrically connected to the dc power supply VCC; a second pole of the seventh transistor Q7 is electrically connected to the first pole of the ninth transistor Q9, and the second pole of the seventh transistor Q7 is also electrically connected to the control pole of the seventh transistor Q7 and the control pole of the eighth transistor Q8; a second pole of the eighth transistor Q8 is electrically connected to the first pole of the tenth transistor Q10, and the second pole of the eighth transistor Q8 is also electrically connected to the input terminal IN5 of the regulated output circuit 14; a second pole of the ninth transistor Q9 is electrically connected to a second pole of the tenth transistor Q10 and a first pole of the eleventh transistor Q11, and a control pole of the ninth transistor Q9 is electrically connected to the output terminal OUT2 of the current amplifying circuit 12; a control electrode of the tenth transistor Q10 is electrically connected to the output terminal OUT4 of the voltage stabilization output circuit 14; the second pole of the eleventh transistor Q11 is grounded GND, and the control pole of the eleventh transistor Q11 is electrically connected to the second reference voltage source VB 2.
Specifically, the seventh transistor Q7 and the eighth transistor Q8 are preferably P-type MOS transistors, and the first electrodes of the seventh transistor Q7 and the eighth transistor Q8 are both source electrodes, the second electrodes are both drain electrodes, and the control electrodes are both gate electrodes. The ninth transistor Q9, the tenth transistor Q10 and the eleventh transistor Q11 are preferably N-type MOS transistors, and each transistor has a drain electrode as a first electrode, a source electrode as a second electrode, and a gate electrode as a control electrode. The gate of the ninth transistor Q9 as the first input terminal IN3 of the differential amplification circuit 13 is electrically connected to the output terminal OUT2 of the current amplification circuit, and the gate voltage V of the ninth transistor Q9 G Q9 Stable at I0 x R3. The gate potential V of the ninth transistor Q9 can be set under normal conditions G Q9 Greater than the gate potential V of the tenth transistor Q10 G Q10 When the rf signal at the output terminal VOUT of the bias circuit 10 increases, the voltage-stabilized signal at the output terminal VOUT of the bias circuit 10 also increases, which results in the gate potential V of the tenth transistor Q10 G Q10 Is also increased so that V G Q9 And V G Q10 So that the second voltage signal output by the differential amplifying circuit 13 is reduced, and the regulated voltage signal output by the regulated voltage output circuit 14 is reduced, and it can be ensured that the bias voltage provided to the base of the power amplifying transistor M1 is kept stable when the radio frequency signal at the base of the power amplifying transistor M1 is increased, so as to improve the linearity of the power amplifier.
Optionally, with continued reference to fig. 2, the regulated output circuit 14 includes a twelfth transistor Q12, a thirteenth transistor Q13, and a fourth resistor R4; a first pole of the twelfth transistor Q12 is electrically connected to a control pole of the thirteenth transistor Q13 and the output end OUT3 of the differential amplifier circuit 13, a second pole of the twelfth transistor Q12 is grounded GND, and a control pole of the twelfth transistor Q12 is electrically connected to a first end of the fourth resistor R4; a first pole of the thirteenth transistor Q13 is electrically connected to the dc power source VCC, and a second pole of the thirteenth transistor Q13 is electrically connected to the output terminal VOUT of the bias circuit 10, the second input terminal IN4 of the differential amplifier circuit 13, and the second terminal of the fourth resistor R4.
Specifically, the twelfth transistor Q12 and the thirteenth transistor Q13 are preferably N-type triodes, and the first poles of the twelfth transistor Q12 and the thirteenth transistor Q13 are both collectors, the second poles are both emitters, and the control poles are both bases. When the rf signal at the output terminal VOUT of the bias circuit 10 increases, so that the regulated signal at the output terminal VOUT of the bias circuit 10 also increases, the base voltage and the base current of the twelfth transistor Q12 are caused to increase, so that the collector current of the twelfth transistor Q12 increases, the base current of the thirteenth transistor Q13 decreases, so that the collector current of the thirteenth transistor Q13 decreases. Based on the above embodiment, when the radio frequency signal at the output terminal VOUT of the bias circuit 10 increases, the second voltage signal output by the differential amplifier circuit 13 is also decreased, so that the current signal output by the differential amplifier circuit 13 to the regulated output circuit 14 is also decreased, and therefore, on the basis that the output current of the differential amplifier circuit 13 is decreased, the regulated output circuit 14 further decreases the output current, so that the decreasing speed of the regulated signal provided to the output terminal of the bias circuit 10 is increased, and the regulated signal at the output terminal of the bias circuit 10 can be recovered and stabilized at a faster speed. That is, when the radio frequency signal at the input end of the power amplifier increases, the bias voltage (voltage stabilization signal) output to the base of the power amplifying transistor M1 by the bias circuit 10 may be kept unchanged, so as to ensure that the base-emitter voltage of the power amplifying transistor M1 is kept unchanged, and the linearity of the power amplifier may be effectively improved.
For example, the voltage value of the regulated signal output by the regulated output circuit 14 may be adjusted by adjusting the resistance value of the fourth resistor R4.
Optionally, with continued reference to fig. 2, the bias circuit 10 further includes a fifth resistor R5; a first terminal of the fifth resistor R5 is electrically connected to a second terminal of the fourth resistor R4 and a second terminal of the thirteenth transistor Q13, and a second terminal of the fifth resistor R5 is electrically connected to the output terminal VOUT of the bias circuit 10.
Specifically, assuming that the connection node of the fourth resistor R4 and the thirteenth and tenth transistors Q13 and Q10 is the third node c, a fifth resistor R5 may be further disposed between the third node c and the output terminal VOUT of the bias circuit 10, so that the input impedance of the power amplifying transistor M1 may be adjusted by adjusting the resistance value of the fifth resistor R5. In addition, it is also possible to make the gate potential of the tenth transistor Q10 lower than the gate potential of the ninth transistor Q9 by setting the resistance value of the fifth resistor R5.
In another possible embodiment of the present invention, the gate of the tenth transistor Q10 may also be electrically connected to the base of the twelfth transistor Q12, and referring to the circuit diagram of another bias circuit shown in fig. 3, then the gate of the tenth transistor Q10 is electrically connected to the output terminal VOUT of the bias circuit 10 through the fourth resistor R4 and the fifth resistor R5 connected in series, so that the gate potential of the tenth transistor Q10 can be further reduced, and the gate potential of the tenth transistor Q10 can be further ensured to be lower than the gate potential of the ninth transistor Q9.
Based on the same inventive concept, an embodiment of the present invention further provides a power amplifier, where the power amplifier includes a power amplification circuit and a bias circuit provided in any embodiment of the present invention, and therefore the power amplifier provided in the embodiment of the present invention includes technical features of the bias circuit provided in any embodiment of the present invention, and can achieve beneficial effects of the bias circuit provided in any embodiment of the present invention, and for the same points, reference may be made to the above description of the bias circuit provided in the embodiment of the present invention, and details are not repeated here.
Optionally, fig. 4 is a circuit diagram of a power amplifier according to an embodiment of the present invention, and as shown in fig. 4, the power amplifier includes a power amplification circuit 20 and a bias circuit 10, where the power amplification circuit 20 includes a first capacitor C1, a second capacitor C2, a power amplification transistor M1, a sixth resistor R6, a seventh resistor R7, a fourteenth transistor Q14, and a first inductor L1; the base electrode of the power amplifying transistor M1 is electrically connected with the radio frequency signal input end RFin through a first capacitor C1, and the base electrode of the power amplifying transistor M1 is also electrically connected with the output end VOUT of the bias circuit 10; a first end of the first inductor L1 is electrically connected to a dc power supply VCC, a second end of the first inductor L1 is electrically connected to a radio frequency signal output end RFout and a collector of the fourteenth transistor Q14, an emitter of the fourteenth transistor Q14 is electrically connected to a collector of the power amplifying transistor M1, and an emitter of the power amplifying transistor M1 is grounded GND; the base of the fourteenth transistor Q14 is electrically connected to the dc power supply VCC through a sixth resistor R6, the base of the fourteenth transistor Q14 is further grounded to GND through a seventh resistor R7, and the base of the fourteenth transistor Q14 is further grounded to GND through a second capacitor C2.
Specifically, the power amplifying transistor M1 and the fourteenth transistor Q14 form a cascode circuit structure, and the bias circuit 10 provides a bias voltage to the cascode transistor (i.e., the power amplifying transistor M1) therein. With reference to the output power comparison diagram of a power amplifier shown in fig. 5, if the operating frequency is 915MHz, taking the output power 1dB compression point of the power amplifier as an example, comparing the power amplifier using the bias circuit provided in the embodiment of the present invention with the power amplifier using the existing resistance voltage-dividing bias circuit, the output power 1dB compression point of the power amplifier using the existing resistance voltage-dividing bias circuit is 4.62dBm, and the output power 1dB compression point of the power amplifier using the bias circuit provided in the embodiment of the present invention is 18.45dBm, that is, the linearity of the power amplifier using the existing resistance voltage-dividing bias circuit begins to deteriorate after the output power reaches a smaller compression value, while the linearity of the power amplifier using the bias circuit provided in the embodiment of the present invention begins to deteriorate after the output power reaches a larger compression value, that is, the linearity of the power amplifier using the bias circuit provided in the embodiment of the present invention is significantly improved.
In fig. 5, a curve L11 is an ideal curve of 1dBm compression when the output power of the power amplifier using the existing resistance voltage-dividing bias circuit is linear, and a curve L12 is an actual curve of the output power of the power amplifier using the existing resistance voltage-dividing bias circuit; the curve L21 is an ideal curve of 1dBm compression when the output power of the power amplifier using the bias circuit provided by the embodiment of the present invention is linear, and the curve L22 is an actual curve of the output power of the power amplifier using the bias circuit provided by the embodiment of the present invention.
Optionally, fig. 6 is a circuit diagram of another power amplifier provided in an embodiment of the present invention, and as shown in fig. 6, the power amplifier includes a power amplifying circuit 20 and a bias circuit 10, where the power amplifying circuit 20 includes a first capacitor C1, a second capacitor C2, a first power amplifying transistor M1, a second power amplifying transistor M2, a sixth resistor R6, a seventh resistor R7, a fourteenth transistor Q14, a fifteenth transistor Q15, a first inductor L1, and a second inductor L2; a first end of the first inductor L1 is electrically connected to a direct current power supply VCC, a second end of the first inductor L1 is electrically connected to a radio frequency signal output end RFout and a collector of a fourteenth transistor Q14, a base of the fourteenth transistor Q14 is electrically connected to a third reference voltage source VB3, an emitter of the fourteenth transistor Q14 is electrically connected to a collector of the first power amplifying transistor M1, an emitter of the first power amplifying transistor M1 is grounded GND, a base of the first power amplifying transistor M1 is electrically connected to a radio frequency signal input end RFin through a first capacitor C1, and the base of the first power amplifying transistor M1 is also electrically connected to an output end VOUT of the bias circuit 10 through a sixth resistor R6; a first end of the second inductor L2 is electrically connected to the dc power supply VCC, a second end of the second inductor L2 is electrically connected to the rf signal output terminal RFout and the collector of the fifteenth transistor Q15, a base of the fifteenth transistor Q15 is electrically connected to the fourth reference voltage source VB4, an emitter of the fifteenth transistor Q15 is electrically connected to the collector of the second power amplifying transistor M2, an emitter of the second power amplifying transistor M2 is grounded GND, a base of the second power amplifying transistor M2 is electrically connected to the rf signal input terminal RFin through the second capacitor C2, and a base of the second power amplifying transistor M2 is further electrically connected to the output terminal VOUT of the bias circuit 10 through the seventh resistor R7.
Specifically, a branch formed by the first inductor L1, the fourteenth transistor Q14, the first power amplifying transistor M1, the sixth resistor R6, and the first capacitor C1 may be a first branch, and a branch formed by the second inductor L2, the fifteenth transistor Q15, the second power amplifying transistor M2, the seventh resistor R7, and the second capacitor C2 may be a second branch, so that the power amplifying circuit formed by the first branch and the second branch has a symmetrical differential structure. With reference to another output power comparison diagram of the power amplifier shown in fig. 7, if the operating frequency of the power amplifier is set to 2.45GHz, taking the output power 1dB compression point of the power amplifier as an example, when comparing the power amplifier using the bias circuit provided in the embodiment of the present invention with the power amplifier using the existing resistance voltage division bias circuit, the output power 1dB compression point of the power amplifier using the existing resistance voltage division bias circuit is 3.1dBm, and the output power 1dB compression point of the power amplifier using the bias circuit provided in the embodiment of the present invention is 14.62dBm, that is, the linearity of the power amplifier using the existing resistance voltage division bias circuit begins to deteriorate after the output power reaches a smaller compression point, whereas the linearity of the power amplifier using the bias circuit provided in the embodiment of the present invention begins to deteriorate after the output power reaches a larger compression point, that is the linearity of the power amplifier using the bias circuit provided in the embodiment of the present invention is obviously improved.
In fig. 7, a curve L11 is an ideal curve of compressing 1dBm when the output power of the power amplifier using the conventional resistance voltage division biasing circuit is linear, and a curve L12 is an actual curve of the output power of the power amplifier using the conventional resistance voltage division biasing circuit; the curve L21 is an ideal curve of 1dBm compression when the output power of the power amplifier using the bias circuit provided by the embodiment of the present invention is linear, and the curve L22 is an actual curve of the output power of the power amplifier using the bias circuit provided by the embodiment of the present invention.
The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made, depending on design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A bias circuit, comprising: the micro-current source circuit, the current amplifying circuit, the differential amplifying circuit and the voltage stabilizing output circuit are connected in series;
the input end of the micro-current source circuit, the power supply end of the current amplifying circuit, the power supply end of the differential amplifying circuit and the power supply end of the voltage stabilizing output circuit are all electrically connected with a direct-current power supply;
the output end of the micro-current source circuit is also electrically connected with the current input end and the control end of the current amplifying circuit, the output end of the current amplifying circuit is electrically connected with the first input end of the differential amplifying circuit, the second input end of the differential amplifying circuit is electrically connected with the output end of the voltage-stabilizing output circuit, and the output end of the differential amplifying circuit is electrically connected with the input end of the voltage-stabilizing output circuit; the output end of the voltage stabilizing output circuit is electrically connected with the output end of the biasing circuit;
the direct current power supply is used for outputting direct current voltage signals to the micro current source circuit, the current amplifying circuit, the differential amplifying circuit and the voltage stabilizing output circuit;
the micro-current source circuit is used for outputting a reference current signal to the current input end of the current amplifying circuit according to the direct-current voltage signal and outputting a bias voltage signal to the control end of the current amplifying circuit;
the current amplifying circuit is used for outputting a first voltage signal to a first input end of the differential amplifying circuit according to the reference current signal, the bias voltage signal and the direct current voltage signal;
the differential amplification circuit is used for outputting a second voltage signal to the input end of the voltage stabilization output circuit according to the direct current voltage signal, the first voltage signal and a feedback signal received by the second input end;
the voltage stabilizing output circuit is used for outputting the voltage stabilizing signal to the output end of the bias circuit according to the second voltage signal and the direct current voltage signal.
2. The bias circuit of claim 1, wherein the micro-current source circuit comprises: the circuit comprises a first resistor, a second resistor, a first transistor and a second transistor;
a first end of the first resistor is electrically connected with the direct current power supply, and a second end of the first resistor is electrically connected with a first end of the second resistor and a control electrode of the first transistor;
the second end of the second resistor is electrically connected with the first pole of the first transistor and the control pole of the second transistor, the first pole of the second transistor is electrically connected with the current input end and the control end of the current amplifying circuit, and the second pole of the first transistor and the second pole of the second transistor are both grounded.
3. The bias circuit of claim 1, wherein the current amplification circuit comprises: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;
a first pole of the third transistor and a first pole of the fourth transistor are both electrically connected to the dc power supply;
a second pole of the third transistor is electrically connected to a first pole of the fifth transistor, a control pole of the third transistor is electrically connected to a control pole of the fourth transistor, a second pole of the fifth transistor, and an output terminal of the micro-current source circuit, and a control pole of the fifth transistor and a control pole of the sixth transistor are both electrically connected to a first reference voltage source;
a second pole of the fourth transistor is electrically connected to the first pole of the sixth transistor, the second pole of the sixth transistor is electrically connected to the first input terminal of the differential amplifier circuit, and the second pole of the sixth transistor is grounded.
4. The bias circuit of claim 3, wherein the current amplification circuit further comprises: a third resistor;
a first end of the third resistor is electrically connected to the second pole of the sixth transistor and the first input end of the differential amplification circuit, and a second end of the third resistor is grounded.
5. The bias circuit of claim 1, wherein the differential amplification circuit comprises: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;
a first pole of the seventh transistor and a first pole of the eighth transistor are both electrically connected with a direct current power supply;
a second pole of the seventh transistor is electrically connected to the first pole of the ninth transistor, and the second pole of the seventh transistor is also electrically connected to the control pole of the seventh transistor and the control pole of the eighth transistor;
a second pole of the eighth transistor is electrically connected to the first pole of the tenth transistor, and the second pole of the eighth transistor is also electrically connected to the input terminal of the voltage regulation output circuit;
a second pole of the ninth transistor is electrically connected to the second pole of the tenth transistor and the first pole of the eleventh transistor, and a control pole of the ninth transistor is electrically connected to the output terminal of the current amplification circuit;
a control electrode of the tenth transistor is electrically connected with an output end of the voltage-stabilizing output circuit;
the second pole of the eleventh transistor is grounded, and the control pole of the eleventh transistor is electrically connected with the second reference voltage source.
6. The bias circuit according to claim 1, wherein the regulated output circuit comprises a twelfth transistor, a thirteenth transistor, and a fourth resistor;
a first electrode of the twelfth transistor is electrically connected with a control electrode of the thirteenth transistor and the output end of the differential amplification circuit, a second electrode of the twelfth transistor is grounded, and a control electrode of the twelfth transistor is electrically connected with a first end of the fourth resistor;
a first pole of the thirteenth transistor is electrically connected to a dc power supply, and a second pole of the thirteenth transistor is electrically connected to the output terminal of the bias circuit, the second input terminal of the differential amplifier circuit, and the second terminal of the fourth resistor.
7. The bias circuit of claim 6, further comprising: a fifth resistor;
a first terminal of the fifth resistor is electrically connected to a second terminal of the fourth resistor and a second terminal of the thirteenth transistor, and a second terminal of the fifth resistor is electrically connected to an output terminal of the bias circuit.
8. A power amplifier, comprising: a power amplifier circuit and a bias circuit as claimed in any one of claims 1 to 7.
9. The power amplifier of claim 8, wherein the power amplification circuit comprises: the power amplifier comprises a first capacitor, a second capacitor, a power amplification transistor, a sixth resistor, a seventh resistor, a fourteenth transistor and a first inductor;
the base electrode of the power amplification transistor is electrically connected with the radio frequency signal input end through the first capacitor, and the base electrode of the power amplification transistor is also electrically connected with the output end of the bias circuit;
a first end of the first inductor is electrically connected with the direct current power supply, a second end of the first inductor is electrically connected with a radio frequency signal output end and a collector of a fourteenth transistor, an emitter of the fourteenth transistor is electrically connected with a collector of the power amplification transistor, and an emitter of the power amplification transistor is grounded; the base of the fourteenth transistor is electrically connected with the direct current power supply through the sixth resistor, the base of the fourteenth transistor is also grounded through the seventh resistor, and the base of the fourteenth transistor is also grounded through the second capacitor.
10. The power amplifier of claim 8, wherein the power amplification circuit comprises: the first capacitor, the second capacitor, the first power amplifying transistor, the second power amplifying transistor, the sixth resistor, the seventh resistor, the fourteenth transistor, the fifteenth transistor, the first inductor and the second inductor;
a first end of the first inductor is electrically connected with the direct-current power supply, a second end of the first inductor is electrically connected with a radio-frequency signal output end and a collector of a fourteenth transistor, a base of the fourteenth transistor is electrically connected with a third reference voltage source, an emitter of the fourteenth transistor is electrically connected with a collector of the first power amplifying transistor, an emitter of the first power amplifying transistor is grounded, a base of the first power amplifying transistor is electrically connected with a radio-frequency signal input end through the first capacitor, and a base of the first power amplifying transistor is also electrically connected with an output end of the bias circuit through the sixth resistor;
the first end of the second inductor is electrically connected with the direct current power supply, the second end of the second inductor is electrically connected with a radio frequency signal output end and a collector of a fifteenth transistor, a base of the fifteenth transistor is electrically connected with a fourth reference voltage source, an emitter of the fifteenth transistor is electrically connected with a collector of the second power amplifying transistor, an emitter of the second power amplifying transistor is grounded, a base of the second power amplifying transistor is electrically connected with a radio frequency signal input end through the second capacitor, and the base of the second power amplifying transistor is further electrically connected with an output end of the bias circuit through the seventh resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211576053.9A CN115580241B (en) | 2022-12-09 | 2022-12-09 | Power amplifier and bias circuit thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211576053.9A CN115580241B (en) | 2022-12-09 | 2022-12-09 | Power amplifier and bias circuit thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115580241A CN115580241A (en) | 2023-01-06 |
| CN115580241B true CN115580241B (en) | 2023-02-24 |
Family
ID=84590290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211576053.9A Active CN115580241B (en) | 2022-12-09 | 2022-12-09 | Power amplifier and bias circuit thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115580241B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116545400B (en) * | 2023-06-26 | 2023-12-19 | 宜确半导体（苏州）有限公司 | Differential clamp circuit, method for controlling differential clamp circuit, power amplifier and radio frequency system |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101557164A (en) * | 2009-05-27 | 2009-10-14 | 深圳市明微技术有限公司 | Low-voltage power-generating circuit and device thereof |
| JP2010056889A (en) * | 2008-08-28 | 2010-03-11 | Elpida Memory Inc | Differential amplifier, reference voltage generating circuit, differential amplification method, and reference voltage generating method |
| CN202634371U (en) * | 2012-06-13 | 2012-12-26 | 南通大学 | Power amplifier with adjustable bias current |
| CN204740523U (en) * | 2015-03-27 | 2015-11-04 | 西安华芯半导体有限公司 | Utilize load changes signal conditioning bias current's device |
| CN110971201A (en) * | 2019-12-31 | 2020-04-07 | 中电国基南方集团有限公司 | Power amplifier bias circuit |
| CN213990604U (en) * | 2020-10-30 | 2021-08-17 | 锐石创芯(重庆)科技有限公司 | Amplifier bias circuit and radio frequency power amplifier |
| CN113872528A (en) * | 2021-09-29 | 2021-12-31 | 上海华虹宏力半导体制造有限公司 | A gain variable amplifier |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150139089A (en) * | 2014-06-02 | 2015-12-11 | 한국전자통신연구원 | Current-voltage conversion amplifier circuit including multiplier and multi input amplifier |
-
2022
- 2022-12-09 CN CN202211576053.9A patent/CN115580241B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010056889A (en) * | 2008-08-28 | 2010-03-11 | Elpida Memory Inc | Differential amplifier, reference voltage generating circuit, differential amplification method, and reference voltage generating method |
| CN101557164A (en) * | 2009-05-27 | 2009-10-14 | 深圳市明微技术有限公司 | Low-voltage power-generating circuit and device thereof |
| CN202634371U (en) * | 2012-06-13 | 2012-12-26 | 南通大学 | Power amplifier with adjustable bias current |
| CN204740523U (en) * | 2015-03-27 | 2015-11-04 | 西安华芯半导体有限公司 | Utilize load changes signal conditioning bias current's device |
| CN110971201A (en) * | 2019-12-31 | 2020-04-07 | 中电国基南方集团有限公司 | Power amplifier bias circuit |
| CN213990604U (en) * | 2020-10-30 | 2021-08-17 | 锐石创芯(重庆)科技有限公司 | Amplifier bias circuit and radio frequency power amplifier |
| CN113872528A (en) * | 2021-09-29 | 2021-12-31 | 上海华虹宏力半导体制造有限公司 | A gain variable amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115580241A (en) | 2023-01-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6437645B1 (en) | Slew rate boost circuitry and method | |
| EP2652872B1 (en) | Current mirror and high-compliance single-stage amplifier | |
| US8797100B2 (en) | Circuit unit, bias circuit with circuit unit and differential amplifier circuit with first and second circuit unit | |
| TW200929859A (en) | High-swing operational amplifier output stage using adaptive biasing | |
| US4901031A (en) | Common-base, source-driven differential amplifier | |
| CN113411055B (en) | Bias current control device, radio frequency amplifier, electronic device and chip | |
| WO2024141091A1 (en) | Power amplifier and electronic device | |
| US5028881A (en) | Highly linear operational transconductance amplifier with low transconductance | |
| US6091300A (en) | Method and apparatus for adjusting the input common mode voltage of a differential amplifier | |
| US7295071B1 (en) | High speed, high DC gain and wide dynamic range amplifier | |
| CN115580241B (en) | Power amplifier and bias circuit thereof | |
| US6788143B1 (en) | Cascode stage for an operational amplifier | |
| US20080290945A1 (en) | Class ab output stage and method for providing wide supply voltage range | |
| CN107994897A (en) | A kind of bias current control circuit, method and power amplification control circuit | |
| US6317000B1 (en) | Overload recovery circuit and method | |
| CN216774725U (en) | Differential pair for input stage and operational amplifier | |
| US3987369A (en) | Direct-coupled FET amplifier | |
| CN115276207A (en) | Wide-range high-adaptability power supply conversion circuit | |
| US4529948A (en) | Class AB amplifier | |
| CN108471295A (en) | Linear amplifier | |
| CN107896096A (en) | Sampling hold circuit front-end wideband amplifier | |
| CN118413202A (en) | Charge sensitive amplifier and electronic device | |
| CN116346047B (en) | Rail-to-rail operational amplifier and input stage structure thereof | |
| US20060139096A1 (en) | Apparatus and method for biasing cascode devices in a differential pair using the input, output, or other nodes in the circuit | |
| CN116192071A (en) | Operational amplifier circuit, linear voltage regulator, chip and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |