CN115565566B

CN115565566B - Read-out circuit structure

Info

Publication number: CN115565566B
Application number: CN202110751226.5A
Authority: CN
Inventors: 池性洙; 金书延; 张凤琴
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-07-02
Filing date: 2021-07-02
Publication date: 2024-09-13
Anticipated expiration: 2041-07-02
Also published as: CN115565566A

Abstract

The embodiment of the application provides a read-out circuit structure, which comprises the following components: a structural layer, a first interconnect layer, and a second interconnect layer; the structure layer is provided with a first sensing amplifying structure, a second sensing amplifying structure, a first balancing structure and a second balancing structure; wherein one of the first bit line or the first complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; one of the second bit line or the second complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; the first equalization structure is directly connected with the first bit line or the first complementary bit line and is used for precharging the first bit line, the first complementary bit line and the first sense amplifying structure; the second equalization structure is directly connected with the second bit line or the second complementary bit line and is used for precharging the second bit line, the second complementary bit line and the second sensing amplification structure, so that the problem of low precharge speed is solved, and the layout area of the read-out circuit structure is reduced.

Description

Read-out circuit structure

Technical Field

The application relates to the field of memory layout design, in particular to a read-out circuit structure.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory device commonly used in computers and consists of many repeated memory cells. Each memory cell typically includes a capacitor and a transistor having a gate connected to a word line, a drain connected to a bit line, and a source connected to the capacitor, a voltage signal on the word line being capable of controlling the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information to the capacitor through the bit line for storage.

The DRAM may be classified into a Double Data Rate (DDR) dynamic random access memory, GDDR (Graphics Double Data Rate) dynamic random access memory, and a low power Double Data Rate (Low Power Double Data Rate, LPDDR) dynamic random access memory. As the fields of DRAM applications become more and more, such as DRAM being more and more applied to the mobile field, the requirements of users on the power consumption index of DRAM become higher and higher.

However, current DRAM performance is still to be improved.

Disclosure of Invention

The embodiment of the application provides a read-out circuit structure, and provides a layout structure and a wiring mode on the basis of solving the problem of low memory precharge speed so as to reduce the layout area of the read-out circuit structure.

To solve the above technical problem, an embodiment of the present application provides a readout circuit structure, disposed in a gap of a memory array, including: the structure layer, the first interconnection layer and the second interconnection layer which are stacked on top of the structure layer; the structure layer is provided with a first sensing amplifying structure, a second sensing amplifying structure, a first balancing structure and a second balancing structure; the first sense amplifying structure is connected with one of the adjacent memory arrays through a first bit line, the first sense amplifying structure is connected with the other of the adjacent memory arrays through a first complementary bit line, the second sense amplifying structure is connected with one of the adjacent memory arrays through a second bit line, and the second sense amplifying structure is connected with the other of the adjacent memory arrays through a second complementary bit line; wherein one of the first bit line or the first complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; one of the second bit line or the second complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; the first equalization structure is directly connected with the first bit line or the first complementary bit line and is used for precharging the first bit line, the first complementary bit line and the first sense amplifying structure; the second equalization structure is directly connected to the second bit line or the second complementary bit line for precharging the second bit line, the second complementary bit line and the second sense amplifying structure.

Compared with the related art, the first equalization structure is directly connected with the first bit line or the first complementary bit line and is used for precharging the first bit line and the first complementary bit line, the second equalization structure is directly connected with the second bit line or the second complementary bit line and is used for precharging the second bit line and the second complementary bit line, the bit line is directly precharged through the equalization structure, the condition that the bit line can be precharged only by switching on a switching transistor in the precharge process is avoided, and therefore the charging speed of the bit line is accelerated; further, at least a portion of one of the first bit line or the first complementary bit line is disposed in the second interconnect layer, the other is disposed in the first interconnect layer, at least a portion of one of the second bit line or the second complementary bit line is disposed in the second interconnect layer, the other is disposed in the first interconnect layer, and by the stacked arrangement of the first interconnect layer and the second interconnect layer, the structure of the layout required in each layer of layout is reduced, thereby reducing the layout area of the sense circuit structure.

In addition, a first bit line is arranged in the first interconnection layer, at least part of a first complementary bit line is arranged in the second interconnection layer, the first complementary bit line is coupled with the first sense amplifying structure after passing through the area where the second sense amplifying structure is arranged in the second interconnection layer, at least part of a second bit line is arranged in the second interconnection layer, the second bit line is coupled with the second sense amplifying structure after passing through the area where the first sense amplifying structure is arranged in the second interconnection layer, and the second complementary bit line is arranged in the first interconnection layer. The first complementary bit line passes through the area where the second sense amplifying structure is located and is coupled with the first sense amplifying structure, namely the first complementary bit line does not need to occupy an extra layout area to finish wiring, so that the layout area of the read-out circuit structure is reduced, and the second bit line passes through the area where the first sense amplifying structure is located and is coupled with the second sense amplifying structure, namely the second bit line does not need to occupy an extra layout area to finish wiring, so that the layout area of the read-out circuit structure is reduced.

In addition, the first equalization structure is arranged on one side of the first sense amplifying structure far away from the second sense amplifying structure, and the first equalization structure is directly connected with the first bit line; the second equalization structure is arranged on one side of the second sense amplifying structure far away from the first sense amplifying structure, and the second equalization structure is directly connected with the second complementary bit line.

In addition, the first equalization structure comprises a first equalization tube, wherein the grid electrode of the first equalization tube is used for receiving a first equalization signal, one of the source electrode or the drain electrode is connected with the first bit line or the first complementary bit line, the other one of the source electrode or the drain electrode is used for receiving a first precharge voltage, and the first bit line, the first complementary bit line and the first sense amplifying structure are precharged to the first precharge voltage based on the first equalization signal; the second equalization structure includes a second equalization pipe having a gate for receiving a second equalization signal, one of a source or a drain connected to the second bit line or the second complementary bit line, and the other for receiving a second precharge voltage for precharging the second bit line, the second complementary bit line, and the second sense amplifying structure to the second precharge voltage based on the second equalization signal.

The first equalization signal and the second equalization signal are the same equalization signal, and the first precharge voltage and the second precharge voltage are the same precharge voltage.

In addition, a third sensing amplifying structure, a fourth sensing amplifying structure, a third equalizing structure and a fourth equalizing structure are further arranged in the structural layer; the third sense amplifying structure is connected with one of the adjacent memory arrays through a third bit line, the third sense amplifying structure is connected with the other of the adjacent memory arrays through a third complementary bit line, the fourth sense amplifying structure is connected with one of the adjacent memory arrays through a fourth bit line, and the fourth sense amplifying structure is connected with the other of the adjacent memory arrays through a fourth complementary bit line; wherein one of the third bit line or the third complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; one of the fourth bit line or the fourth complementary bit line is disposed in the second interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; the third equalization structure is directly connected with the third bit line or the third complementary bit line and is used for precharging the third bit line, the third complementary bit line and the third sense amplifying structure; the fourth equalization structure is directly connected with the fourth bit line or the fourth complementary bit line and is used for precharging the fourth bit line, the fourth complementary bit line and the fourth sense amplifying structure; the third equalization structure is directly connected with a third bit line or a third complementary bit line and is used for precharging the third bit line and the third complementary bit line, the fourth equalization structure is directly connected with a fourth bit line or the fourth complementary bit line and is used for precharging the fourth bit line and the fourth complementary bit line, the bit line is directly precharged through the equalization structure, and the situation that the bit line can be precharged only by switching on a switching transistor in the precharge process is avoided, so that the charging speed of the bit line is accelerated; further, at least a portion of one of the third bit line or the third complementary bit line is disposed in the second interconnect layer, the other is disposed in the first interconnect layer, at least a portion of one of the fourth bit line or the fourth complementary bit line is disposed in the second interconnect layer, the other is disposed in the first interconnect layer, and the structure of the layout required in each layer of layout is reduced by the stacked arrangement of the first interconnect layer and the second interconnect layer, thereby reducing the layout area of the sense circuit structure.

In addition, a first data reading module and a second data reading module are also arranged in the structural layer; a first data readout module comprising: a first input/output pipe, a third input/output pipe, a fifth input/output pipe, and a seventh input/output pipe; the source electrode of the first input/output tube is connected with the first input/output line, the drain electrode is connected with the first bit line, the source electrode of the third input/output tube is connected with the third input/output line, the drain electrode is connected with the second bit line, the source electrode of the fifth input/output tube is connected with the fifth input/output line, the drain electrode is connected with the third bit line, the source electrode of the seventh input/output tube is connected with the seventh input/output line, and the drain electrode is connected with the fourth bit line; the first bit line, the second bit line, the third bit line and the fourth bit line are four adjacent bit lines in the same memory array; the grid electrode of the first input/output tube, the grid electrode of the third input/output tube, the grid electrode of the fifth input/output tube and the grid electrode of the seventh input/output tube are connected together and used for receiving a column selection signal and conducting the first input/output tube, the third input/output tube, the fifth input/output tube and the seventh input/output tube based on the column selection signal; the second data reading module comprises a second input/output pipe, a fourth input/output pipe, a sixth input/output pipe and an eighth input/output pipe; the source electrode of the second input/output tube is connected with the second input/output line, the drain electrode is connected with the first complementary bit line, the source electrode of the fourth input/output tube is connected with the fourth input/output line, the drain electrode is connected with the second complementary bit line, the source electrode of the sixth input/output tube is connected with the sixth input/output line, the drain electrode is connected with the third complementary bit line, the source electrode of the eighth input/output tube is connected with the eighth input/output line, and the drain electrode is connected with the fourth complementary bit line; the first complementary bit line, the second complementary bit line, the third complementary bit line and the fourth complementary bit line are four adjacent bit lines in the same memory array; the grid electrode of the second input/output tube, the grid electrode of the fourth input/output tube, the grid electrode of the sixth input/output tube and the grid electrode of the eighth input/output tube are connected together and used for receiving the column selection signals and conducting the second input/output tube, the fourth input/output tube, the sixth input/output tube and the eighth input/output tube based on the column selection signals.

In addition, the first data reading module is arranged at one side of the first equalization structure and the third equalization structure far away from the first sense amplifying structure and the third sense amplifying structure; the second data reading module is arranged on one side of the second equalization structure and the fourth equalization structure far away from the second sense amplifying structure and the fourth sense amplifying structure.

In addition, the first sense amplifying structure includes: the sense amplifying module is connected with the first bit line through a read bit line, is connected with the first complementary bit line through a complementary read bit line, and is used for sensing the voltage of the memory cells of the memory array and outputting logic 1 or 0 corresponding to the voltage; the isolation module is connected between the complementary read bit line and the first complementary bit line and between the read bit line and the first bit line, and is used for isolating the first bit line and the first complementary bit line from signal interaction between the read bit line and the complementary read bit line according to the isolation signal; and the offset elimination module is connected between the read bit line and the first complementary bit line and between the complementary read bit line and the first bit line and is used for adjusting the source-drain conduction difference between NMOS (N-channel metal oxide semiconductor) tubes or between PMOS (P-channel metal oxide semiconductor) tubes in the sense amplification module according to the offset elimination signal.

In addition, the sense amplifying module includes: the first sensing amplifying N tube, the grid connects the first bit line, the drain electrode connects the complementary read-out bit line, the source electrode connects the second signal end, when the sensing amplifying module is in amplifying stage, the second signal end connects the voltage that the logic 0 corresponds to electrically; a second sense amplifier N-tube, wherein the grid electrode is connected with the first complementary bit line, the drain electrode is connected with the read bit line, and the source electrode is connected with the second signal end; the first sensing amplifying P tube, the grid connects the read-out bit line, the drain electrode connects the complementary read-out bit line, the source electrode connects the first signal end, when the sensing amplifying module is in amplifying stage, the first signal end connects the voltage corresponding to logic 1 electrically; a second sense amplifier P-tube, the grid electrode of which is connected with the complementary read bit line, the drain electrode is connected with the read bit line, and the source electrode is connected with the first signal end.

In addition, the gate structure of the first sense amplifying N-tube, the gate structure of the second sense amplifying N-tube, the gate structure of the first sense amplifying P-tube and the gate structure of the second sense amplifying P-tube have the same extending direction, the gate structure of the MOS tube in the isolation module and the gate structure of the MOS tube in the offset cancellation module have the same extending direction, and the gate structure of the first sense amplifying N-tube and the gate structure of the MOS tube in the isolation module have the extending directions perpendicular to each other.

In addition, the first sense amp P-tube, the second sense amp P-tube, the isolation module and the offset cancellation module are disposed between the first sense amp N-tube and the second sense amp N-tube.

In addition, the isolation module includes: the first isolation tube, the grid is used for receiving the isolation signal, the source connects the first bit line, the drain electrode connects and reads out the bit line; a second isolation tube, a grid electrode for receiving the isolation signal, the source is connected to the first complementary bit line and the drain is connected to the complementary sense bit line.

In addition, the offset cancellation module includes: a first offset cancellation tube having a gate for receiving an offset cancellation signal, a source connected to the first bit line, and a drain connected to the complementary sense bit line; a second offset canceling tube having a gate for receiving the offset canceling signal, the source is connected to the first complementary bit line and the drain is connected to the sense bit line.

In addition, the source electrode of the first isolation tube is communicated with the source electrode of the first offset elimination tube and is connected with the first bit line; the source of the second isolation tube is connected with the source of the second offset cancellation tube and is connected with the first complementary bit line.

Drawings

Fig. 1 and fig. 2 are circuit diagrams of a readout circuit structure according to an embodiment of the present application;

fig. 3 and fig. 4 are layouts of a readout circuit structure according to an embodiment of the present application.

Detailed Description

From the background, the performance of the DRAM of the prior art is still to be improved.

The applicant finds that the existing sense amplifier with the offset compensation function comprises a switching-on process of a switching transistor in the precharge process of a bit line and a complementary bit line, so that the charging speed of the bit line and the complementary bit line is not fast enough, and the saturated current of the switching transistor is reduced along with the further miniaturization of the transistor size, so that the situation is more serious, and the read-write performance of a memory is not beneficial to improvement.

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be understood by those of ordinary skill in the art that in various embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. The claimed application may be practiced without these specific details and with various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not be construed as limiting the specific implementation of the present application, and the embodiments can be combined with each other and cited with each other without contradiction.

Fig. 1 and 2 are circuit diagrams of a readout circuit structure provided in this embodiment, fig. 3 and 4 are layouts of the readout circuit structure provided in this embodiment, and the readout circuit structure provided in this embodiment is further described in detail below with reference to the accompanying drawings:

It should be noted that, because the circuit diagram and the layout of the readout circuit structure are larger, in order to clearly embody the readout circuit structure to be protected in this embodiment, the circuit diagram and the layout are split during drawing, that is, fig. 1 and fig. 2 are combined to form the circuit diagram of the readout circuit structure provided in this embodiment, and the combination mode is that the bottom of fig. 1 and the top of fig. 2 are combined; fig. 3 and fig. 4 are combined to provide a layout of the readout circuit structure according to the present embodiment, in such a manner that the bottom of fig. 3 and the top of fig. 4 are combined.

Referring to fig. 1 to 4, a read-out circuit structure, provided in a gap of adjacent memory arrays, includes:

The memory array 101 has n rows and m columns of memory cells, each for storing 1bit (bit) of data, i.e., a memory array 101 may store n×mbit of data, and during data readout, the specific memory cells are gated, so that the data stored in the memory cells are read, or the data is written into the memory cells.

The structure layer, the first interconnection layer and the second interconnection layer which are stacked on top of the structure layer, specifically, referring to fig. 3 and 4, the structure layer is the layout on the right side in the figure, the first interconnection layer is the layout on the middle part in the figure, and the second interconnection layer is the layout on the left side in the figure.

The structure layer is used for forming a specific device structure in the read-out circuit structure, and in the embodiment, a first sense amplifying structure, a second sense amplifying structure, a first equalizing structure and a second equalizing structure are arranged in the structure layer; the first interconnection layer is used for arranging bit lines or complementary bit lines which are electrically connected inside the sense amplifying structure and are closer to each other between the adjacent memory arrays; the second interconnect layer is used for the sense amplifying structure to connect the bit line or the complementary bit line of the farther one between the adjacent memory arrays.

Referring to fig. 1 and 2 in combination with fig. 3 and 4, in the bit line extending direction, a first sense amplifying structure and a second sense amplifying structure are disposed adjacent to each other for sensing a voltage of a memory cell and outputting a logic 1 or 0 corresponding to the voltage; the first sense amplifying structure is connected with one memory array of the adjacent memory array through a first bit line BL1, the first sense amplifying structure is connected with the other memory array of the adjacent memory array through a first complementary bit line BLB1, the second sense amplifying structure is connected with one memory array of the adjacent memory array through a second bit line BL2, and the second sense amplifying structure is connected with the other memory array of the adjacent memory array through a second complementary bit line BLB 2.

For the first bit line BL1, the second bit line BL2, the first complementary bit line BLB1, and the second complementary bit line BLB2, one of the first bit line BL1 or the first complementary bit line BLB1 is disposed in the first interconnect layer, and at least part of the other is disposed in the second interconnect layer; one of the second bit line BL2 or the second complementary bit line BLB2 is disposed in the first interconnect layer, and at least part of the other is disposed in the second interconnect layer.

Specifically, in the present embodiment, the first bit line BL1 is disposed in the first interconnect layer, at least part of the first complementary bit line BLB1 is disposed in the second interconnect layer, the first complementary bit line BLB1 is coupled to the first sense amplifying structure after passing through the region where the second sense amplifying structure is located in the second interconnect layer, the second bit line BL2 is at least partially disposed in the second interconnect layer, the second bit line BL2 is coupled to the second sense amplifying structure after passing through the region where the first sense amplifying structure is located in the second interconnect layer, and the second complementary bit line BLB2 is disposed in the first interconnect layer.

The first complementary bit line BLB1 passes through the area where the second sense amplifying structure is located and is coupled with the first sense amplifying structure, namely, the first complementary bit line BLB1 does not need to occupy an extra layout area to finish wiring, so that the layout area of the read-out circuit structure is reduced, and the second bit line BL2 passes through the area where the first sense amplifying structure is located and is coupled with the second sense amplifying structure, namely, the second bit line BL2 does not need to occupy an extra layout area to finish wiring, so that the layout area of the read-out circuit structure is reduced.

The first equalizing structure is directly connected to the first bit line BL1 or the first complementary bit line BLB1 for precharging the first bit line BL1, the first complementary bit line BLB1 and the first sense amplifying structure.

In this embodiment, the first equalizing structure is disposed on a side of the first sense amplifying structure away from the second sense amplifying structure.

The first equalization structure includes a first equalization tube < N1>, a gate of the first equalization tube < N1> is used for receiving a first equalization signal EQ1, one of a source or a drain is connected to the first bit line BL1 or the first complementary bit line BLB1, and the other is used for receiving a first precharge voltage V ₁, and is used for precharging the first bit line BL1, the first complementary bit line BLB1 and the first sense amplifying structure to the first precharge voltage V ₁ based on the first equalization signal EQ 1.

In this embodiment, the first equalization structure is directly connected to the first bit line BL1, i.e. the source of the first equalization tube < N1> is connected to the first bit line BL1, the drain is used for receiving the first precharge voltage V ₁ for precharging the first bit line BL1, the first complementary bit line BLB1 and the first sense amplifying structure to the first precharge voltage V ₁ based on the first equalization signal EQ 1.

The second equalizing structure is directly connected to the second bit line BL2 or the second complementary bit line BLB2 for precharging the second bit line BL2, the second complementary bit line BLB2, and the second sense amplifying structure.

In this embodiment, the second equalizing structure is disposed on a side of the second sense amplifying structure away from the first sense amplifying structure.

The second equalization structure includes a second equalization tube < N2>, wherein a gate of the second equalization tube < N2> is used for receiving a second equalization signal EQ2, one of a source or a drain is connected to the second bit line BL2 or the second complementary bit line BLB2, and the other is used for receiving a second precharge voltage V ₂ for precharging the second bit line BL2, the second complementary bit line BLB2 and the second sense amplifying structure to the second precharge voltage V ₂ based on the second equalization signal EQ 2.

In this embodiment, the second equalizing structure is directly connected to the second complementary bit line BLB2, that is, the source of the second equalizing tube < N2> is connected to the second complementary bit line BLB2, the drain is used for receiving the second precharge voltage V ₂, and the second bit line BL2, the second complementary bit line BLB2 and the second sense amplifying structure are precharged to the second precharge voltage V ₂ based on the second equalizing signal EQ 2.

In the above description, the connection manner of the "source" and the "drain" is not limited to the embodiment, and in other embodiments, the connection manner of the "drain" instead of the "source" may be adopted, and the connection manner of the "source" instead of the "drain" may be adopted.

The equalization tube is directly connected with the bit line/complementary bit line to directly charge the bit line and the complementary bit line, so that the situation that the bit line/complementary bit line is precharged only by switching on of the switching transistor in the precharge process is avoided, and the charging speed of the bit line and the complementary bit line is accelerated.

It should be noted that the above-mentioned "first precharge voltage V ₁" and "second precharge voltage V ₂", that is, the voltages required for precharging the memory bit line and the complementary bit line in the precharge phase, are set according to the precharge voltages required for the normal operation of the memory, and the present embodiment does not constitute limitation of the values of the "first precharge voltage V ₁" and the "second precharge voltage V ₂".

In one example, the first equalization signal EQ1 and the second equalization signal EQ2 are the same equalization signal, i.e., the same control signal is used to precharge the bit line and the complementary bit line. The first precharge voltage V ₁ and the second precharge voltage V ₂ are the same precharge voltage V _BLP; in the present embodiment, the precharge voltage V _BLP＝1/2V_DD, where V _DD is the chip internal power supply voltage; in other embodiments, the precharge voltage V _BLP may be set according to a specific application scenario.

In this embodiment, in order to clearly distinguish the above-described one memory array from the other memory array, in the following description, the memory array in which the first sense amplifying structure is connected through the first bit line BL1 is referred to as a "first memory array"; the memory array in which the second sense amplifying structure is connected through the second complementary bit line BLB2 is referred to as a "second memory array".

In addition, in the extending direction of the word line, there is not only one group of sense amplifying structures between adjacent memory arrays, and the embodiment is described in detail by taking a layout structure of 2x2 as an example, which is specifically as follows:

In this embodiment, a third sense amplifying structure, a fourth sense amplifying structure, a third equalizing structure, and a fourth equalizing structure are further disposed in the structural layer.

The third sense amplifying structure and the fourth sense amplifying structure are adjacently disposed in the bit line extending direction, for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage; in the word line extending direction, the third sense amplifying structure and the first sense amplifying structure are disposed adjacent to each other, and the fourth sense amplifying structure and the second sense amplifying structure are disposed adjacent to each other.

The third sense amplifying structure is connected to the "first memory array" through a third bit line BL3, connected to the "second memory array" through a third complementary bit line BLB3, and connected to the "first memory array" through a fourth bit line BL4, and connected to the "second memory array" through a fourth complementary bit line BLB 4.

For the third bit line BL3, the fourth bit line BL4, the third complementary bit line BLB3, and the fourth complementary bit line BLB4, one of the third bit line BL3 or the third complementary bit line BLB3 is disposed in the first interconnect layer, and at least part of the other is disposed in the second interconnect layer; one of the fourth bit line BL4 or the fourth complementary bit line BLB4 is disposed in the first interconnect layer, and at least part of the other is disposed in the second interconnect layer.

It should be noted that, the first bit line BL1, the second bit line BL2, the third bit line BL3, and the fourth bit line BL4 are four adjacent bit lines in the same memory array; the first, second, third and fourth complementary bit lines BLB1, BLB2, BLB3 and BLB4 are four adjacent bit lines in the same memory array.

Specifically, in the present embodiment, the third bit line BL3 is disposed in the first interconnect layer, at least part of the third complementary bit line BLB3 is disposed in the second interconnect layer, the third complementary bit line BLB3 is coupled to the third sense amplifying structure after passing through the region where the fourth sense amplifying structure is located in the second interconnect layer, the fourth bit line BL4 is at least partially disposed in the second interconnect layer, the fourth bit line BL4 is coupled to the fourth sense amplifying structure after passing through the region where the third sense amplifying structure is located in the second interconnect layer, and the fourth complementary bit line BLB4 is disposed in the first interconnect layer.

The third complementary bit line BLB3 passes through the area where the second sense amplifying structure is located and is coupled with the first sense amplifying structure, namely, the third complementary bit line BLB3 does not need to occupy an extra layout area to finish wiring, so that the layout area of the read-out circuit structure is reduced, and the fourth bit line BL4 passes through the area where the first sense amplifying structure is located and is coupled with the second sense amplifying structure, namely, the fourth bit line BL4 does not need to occupy an extra layout area to finish wiring, so that the layout area of the read-out circuit structure is reduced.

The third equalizing structure is directly connected to the third bit line BL3 or the third complementary bit line BLB3 for precharging the third bit line BL3, the third complementary bit line BLB3, and the third sense amplifying structure.

In this embodiment, the third equalizing structure is disposed on a side of the third sense amplifying structure away from the fourth sense amplifying structure.

The third equalization structure includes a third equalization tube < N3>, wherein a gate of the third equalization tube < N3> is used for receiving a first equalization signal EQ1, one of a source and a drain is connected to the third bit line BL3 or the third complementary bit line BLB3, and the other is used for receiving a first precharge voltage V ₁ for precharging the third bit line BL3, the third complementary bit line BLB3 and the third sense amplifying structure to the first precharge voltage V ₁ based on the first equalization signal EQ 1.

In the present embodiment, the third equalization structure is directly connected to the third bit line BL3, that is, the source of the third equalization tube < N3> is connected to the third bit line BL3, the drain is used for receiving the first precharge voltage V ₁, and for precharging the third bit line BL3, the third complementary bit line BLB3, and the third sense amplifying structure to the first precharge voltage V ₁ based on the first equalization signal EQ 1.

The fourth equalizing structure is directly connected to the fourth bit line BL4 or the fourth complementary bit line BLB4 for precharging the fourth bit line BL4, the fourth complementary bit line BLB4, and the fourth sense amplifying structure.

In this embodiment, the fourth equalizing structure is disposed on a side of the fourth sense amplifying structure away from the third sense amplifying structure.

The fourth equalization structure includes a fourth equalization tube < N4>, a gate of the fourth equalization tube < N4> is used for receiving a second equalization signal EQ2, one of a source or a drain is connected to the fourth bit line BL4 or the fourth complementary bit line BLB4, the other is used for receiving a second precharge voltage V ₂, and the fourth bit line BL4, the fourth complementary bit line BLB4 and the fourth sense amplifying structure are precharged to the second precharge voltage V ₂ based on the second equalization signal EQ 2.

In this embodiment, the fourth equalization structure is directly connected to the fourth complementary bit line BLB4, that is, the source of the fourth equalization tube < N4> is connected to the fourth complementary bit line BLB4, the drain is used for receiving the second precharge voltage V ₂, and the fourth bit line BL4, the fourth complementary bit line BLB4, and the fourth sense amplifying structure are precharged to the second precharge voltage V ₂ based on the second equalization signal EQ 2.

With continued reference to fig. 1 and 2, the sensing circuit structure further includes a first data sensing module comprising: the first input/output tube, the third input/output tube, the fifth input/output tube, and the seventh input/output tube.

One of the source electrode or the drain electrode of the first input/output tube is directly connected with the first input/output line, the other is connected with the first bit line, the grid electrode of the first input/output tube is used for receiving a column selection signal, and the first input/output tube is conducted based on the column selection signal so that the first input/output line is electrically connected with the first bit line, and therefore an electric signal carried in the first bit line is output through the first input/output line; in this embodiment, the first input/output pipe has a source connected to the first input/output line and a drain connected to the first bit line.

One of the source electrode or the drain electrode of the third input/output tube is directly connected with the third input/output line, the other is connected with the second bit line, the grid electrode of the third input/output tube is used for receiving a column selection signal, and the third input/output tube is conducted based on the column selection signal, so that the third input/output line is electrically connected with the second bit line, and the electric signal carried in the second bit line is output through the third input/output line; in this embodiment, the third input/output pipe has a source connected to the third input/output line and a drain connected to the second bit line.

One of the source electrode or the drain electrode of the fifth input/output tube is directly connected with the fifth input/output line, the other is connected with the third bit line, the grid electrode of the fifth input/output tube is used for receiving a column selection signal, and the fifth input/output tube is conducted based on the column selection signal so that the fifth input/output line is electrically connected with the third bit line, and therefore an electric signal carried in the third bit line is output through the fifth input/output line; in this embodiment, the fifth input/output line has a source connected to the fifth input/output line and a drain connected to the third bit line.

One of the source electrode or the drain electrode of the seventh input/output tube is directly connected with the seventh input/output line, the other is connected with the fourth bit line, the grid electrode of the seventh input/output tube is used for receiving a column selection signal, and the seventh input/output tube is conducted based on the column selection signal, so that the seventh input/output line is electrically connected with the fourth bit line, and the electric signal carried in the fourth bit line is output through the seventh input/output line; in this embodiment, the seventh input/output line has a source connected to the seventh input/output line and a drain connected to the fourth bit line.

It should be noted that, in the above description, the connection manner of the "source" and the "drain" is not limited to the embodiment, and in other embodiments, the connection manner of the "drain" instead of the "source" may be adopted, and the connection manner of the "source" instead of the "drain" may also be adopted.

A second data readout module, the second data readout module comprising: a second input/output tube, a fourth input/output tube, a sixth input/output tube, and an eighth input/output tube.

One of the source electrode or the drain electrode of the second input/output tube is directly connected with the second input/output line, the other is connected with the first complementary bit line, the grid electrode of the second input/output tube is used for receiving a column selection signal, and the second input/output tube is conducted on the basis of the column selection signal so that the second input/output line is electrically connected with the first complementary bit line, and therefore an electric signal carried in the first complementary bit line is output through the second input/output line; in this embodiment, the second input/output pipe has a source connected to the second input/output line and a drain connected to the first complementary bit line.

One of the source electrode or the drain electrode of the fourth input/output tube is directly connected with the fourth input/output line, the other is connected with the second complementary bit line, the grid electrode of the fourth input/output tube is used for receiving a column selection signal, and the fourth input/output tube is conducted based on the column selection signal so that the fourth input/output line is electrically connected with the second complementary bit line, and therefore the electric signal carried in the second complementary bit line is output through the fourth input/output line; in this embodiment, the fourth input/output line has a source connected to the fourth input/output line and a drain connected to the second complementary bit line.

One of the source electrode or the drain electrode of the sixth input/output tube is directly connected with the sixth input/output line, the other is connected with the third complementary bit line, the grid electrode of the sixth input/output tube is used for receiving a column selection signal, and the sixth input/output tube is conducted based on the column selection signal so that the sixth input/output line is electrically connected with the third complementary bit line, and therefore the electric signal carried in the third complementary bit line is output through the sixth input/output line; in this embodiment, the sixth input/output line has a source connected to the sixth input/output line and a drain connected to the third complementary bit line.

One of the source electrode or the drain electrode of the eighth input/output tube is directly connected with the eighth input/output line, the other is connected with the fourth complementary bit line, the grid electrode of the eighth input/output tube is used for receiving a column selection signal, and the eighth input/output tube is conducted based on the column selection signal so that the eighth input/output line is electrically connected with the fourth complementary bit line, and therefore the electric signal carried in the fourth complementary bit line is output through the eighth input/output line; in this embodiment, the eighth input/output line has a source connected to the eighth input/output line and a drain connected to the fourth complementary bit line.

Referring to fig. 1, for the first sense amplifying structure and the third sense amplifying structure, a detailed description will be given below taking the first sense amplifying structure as an example, where the first sense amplifying structure includes:

The sense amplifying module is connected to the first bit line BL1 through the sense bit line SABL, connected to the first complementary bit line BLB1 through the complementary sense bit line SABLB, and used for sensing the voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage.

Specifically, the sense amplification module includes: a first sense amplifying N-pipe < N1400>, a gate connected to the first bit line BL1, a drain connected to the complementary sense bit line SABLB, a source connected to the second signal terminal NCS, the second signal terminal NCS electrically connected to a voltage corresponding to logic 0 when the sense amplifying module is in an amplifying stage; a second sense amplifier N-tube < N1405>, wherein the gate is connected with the first complementary bit line BLB1, the drain is connected with the read bit line SABL, and the source is connected with the second signal end NCS; a first sense amplifying P-tube < P1401>, a gate connected to the sense bit line SABL, a drain connected to the complementary sense bit line SABLB, and a source connected to the first signal terminal PCS, the first signal terminal PCS being electrically connected to a voltage corresponding to logic 1 when the sense amplifying module is in an amplifying stage; the second sense amplifier P-tube < P1400>, the gate is connected with the complementary read bit line SABLB, the drain is connected with the read bit line SABL, and the source is connected with the first signal end PCS.

And an isolation module connected between the complementary sense bit line SABLB and the first complementary bit line BLB1 and between the sense bit line SABL and the first bit line BL1 for isolating signal interactions between the first bit line BL1, the first complementary bit line BLB1, and the sense bit line SABL and the complementary sense bit line SABLB according to an isolation signal ISO.

Specifically, the isolation module includes: the first isolation tube < N1402>, the grid is used for receiving the isolation signal ISO, the source is connected with the first bit line BL1, the drain is connected with the read bit line SABL, the second isolation tube < N1403>, the grid is used for receiving the isolation signal ISO, the source is connected with the first complementary bit line BLB1, and the drain is connected with the complementary read bit line SABLB.

The offset cancellation module is connected between the sense bit line SABL and the first complementary bit line BLB1 and between the complementary sense bit line SABLB and the first bit line BL1, and is used for adjusting the source-drain conduction difference between the NMOS or PMOS transistors in the sense amplification module according to the offset cancellation signal OC.

It should be noted that, the above-mentioned "source-drain conduction difference" refers to: the first and second sense amplifying N-tubes < N1400> and < N1405> and the first and second sense amplifying P-tubes < P1401> may have different threshold voltages from each other due to variations in manufacturing process, temperature, etc. In this case, the sense amplification module may cause offset noise due to a difference between threshold voltages of the first and second sense amplification P-tubes < P1401> and P1400> and the first and second sense amplification N-tubes < N1400> and N1405 >.

Specifically, the offset cancellation module includes: a first offset cancellation pipe < N1401>, having a gate for receiving an offset cancellation signal OC, a source connected to the first bit line BL1, and a drain connected to the complementary sense bit line SABLB; and a second offset canceling line < N1404>, having a gate for receiving the offset canceling signal OC, a source connected to the first complementary bit line BLB1, and a drain connected to the sense bit line SABL.

Those skilled in the art will recognize that the third sense amplifying structure has the same structure as the first sense amplifying structure, and the same structure is applicable to the above description after the feature replacement of the corresponding structure. Specifically, the corresponding structure includes: the first bit line BL1 corresponds to BL3, the first complementary bit line BLB1 corresponds to BLB3, the first equalization tube < N1> corresponds to < N5>, the third equalization tube < N3> corresponds to < N7>, the first sense amp N tube < N1400> corresponds to < N1410>, the second sense amp N tube < N1405> corresponds to < N1415>, the first sense amp P tube < P1401> corresponds to < P1411>, the second sense amp P tube < P1400> corresponds to < P1410>, the first isolation tube < N1402> corresponds to < N1412>, the second isolation tube < N1403> corresponds to < N1413>, the first offset cancellation tube < N1401> corresponds to < N1411>, and the second offset cancellation tube < N1404> corresponds to < N1414>.

For the first data readout module, the first input/output pipe source is connected to the first input/output line I/O1, the drain is directly connected to the first bit line BL1, the gate is for receiving the column selection signal CY, the third input/output pipe source is connected to the third input/output line I/O3, the drain is directly connected to the second bit line BL2, the gate is for receiving the column selection signal CY, the fifth input/output pipe source is connected to the fifth input/output line I/O5, the drain is directly connected to the third bit line BL3, the gate is for receiving the column selection signal CY, the seventh input/output pipe source is connected to the seventh input/output line I/O7, the drain is directly connected to the fourth bit line BL4, and the gate is for receiving the column selection signal CY.

The first input/output pipe, the third input/output pipe, the fifth input/output pipe, and the seventh input/output pipe are turned on by the same column selection signal CY, so that the level signal transmitted in the first bit line BL1 is derived through the first input/output line I/O1, the level signal transmitted in the second bit line BL2 is derived through the third input/output line I/O3, the level signal transmitted in the third bit line BL3 is derived through the fifth input/output line I/O5, and the level signal transmitted in the fourth bit line BL4 is derived through the seventh input/output line I/O7.

Referring to fig. 2, for the second sense amplifying structure and the fourth sense amplifying structure, a second sense amplifying structure will be described in detail below, and the second sense amplifying structure includes:

The sense amplifying module is connected to the second bit line BL2 through the sense bit line SABL, is connected to the second complementary bit line BLB2 through the complementary sense bit line SABLB, and is used for sensing the voltage of the memory cell and outputting logic 1 or 0 corresponding to the voltage.

Specifically, the sense amplification module includes: a third sense amplifying N-pipe < N1425>, wherein the gate is connected to the second bit line BL2, the drain is connected to the complementary read bit line SABLB, the source is connected to the second signal terminal NCS, and when the sense amplifying module is in the amplifying stage, the second signal terminal NCS is electrically connected to the voltage corresponding to logic 0; a fourth sense amplifier N-tube < N1420>, the grid electrode is connected with the second complementary bit line BLB2, the drain electrode is connected with the read bit line SABL, and the source electrode is connected with the second signal end NCS; a third sense amplifying P-pipe < P1421>, wherein the gate is connected with the sense bit line SABL, the drain is connected with the complementary sense bit line SABLB, the source is connected with the first signal end PCS, and when the sense amplifying module is in an amplifying stage, the first signal end PCS is electrically connected with a voltage corresponding to logic 1; the fourth sense amplifier P-tube < P1420> has a gate connected to the complementary sense bit line SABLB, a drain connected to the sense bit line SABL, and a source connected to the first signal terminal PCS.

And an isolation module connected between the complementary sense bit line SABLB and the second complementary bit line BLB2 and between the sense bit line SABL and the second bit line BL2 for isolating signal interactions between the second bit line BL2, the second complementary bit line BLB2 and the sense bit line SABL and the complementary sense bit line SABLB according to an isolation signal ISO.

Specifically, the isolation module includes: the first isolation tube < N1423>, the grid is used for receiving the isolation signal ISO, the source is connected with the second bit line BL2, the drain is connected with the read bit line SABL, the second isolation tube < N1422>, the grid is used for receiving the isolation signal ISO, the source is connected with the second complementary bit line BLB2, and the drain is connected with the complementary read bit line SABLB.

The offset cancellation module is connected between the sense bit line SABL and the second complementary bit line BLB2 and between the complementary sense bit line SABLB and the second bit line BL2, and is used for adjusting the source-drain conduction difference between the NMOS or PMOS transistors in the sense amplification module according to the offset cancellation signal OC.

It should be noted that, the above-mentioned "source-drain conduction difference" refers to: the third and fourth sense amplifying N-tubes < N1425> and N1420> and the third and fourth sense amplifying P-tubes < P1421> and P1420 may have different threshold voltages from each other due to variations in manufacturing processes, temperatures, etc. In this case, the sense amplification module may cause offset noise due to a difference between threshold voltages of the third and fourth sense amplification P-tubes < P1421> and P-tubes < P1420> and the third and fourth sense amplification N-tubes < N1445> and N-tube < N1420 >.

Specifically, the offset cancellation module includes: a third offset cancellation pipe < N1424>, having a gate for receiving the offset cancellation signal OC, a source connected to the second bit line BL2, and a drain connected to the complementary sense bit line SABLB; and a fourth offset canceling line < N1421>, having a gate for receiving the offset canceling signal OC, a source connected to the second complementary bit line BLB2, and a drain connected to the sense bit line SABL.

Those skilled in the art will recognize that the structure of the fourth sense amplifying structure is the same as that of the second sense amplifying structure, and the same applies to the above description after the feature replacement of the corresponding structure. Specifically, the corresponding structure includes: the second bit line BL2 corresponds to BL4, the second complementary bit line BLB2 corresponds to BLB4, the second equalization tube < N2> corresponds to < N6>, the fourth equalization tube < N4> corresponds to < N8>, the third sense amp N tube < N1425> corresponds to < N1435>, the fourth sense amp N tube < N1420> corresponds to < N1430>, the third sense amp P tube < P1421> corresponds to < P1431>, the fourth sense amp P tube < P1420> corresponds to < P1430>, the third isolation tube < N1423> corresponds to < N1433>, the fourth isolation tube < N1422> corresponds to < N1432>, the third offset cancel tube < N1424> corresponds to < N1434>, the fourth offset cancel tube < N1421> corresponds to < N1431>.

For the second data read-out module, the second input/output pipe source is connected to the second input/output line I/O2, the drain is directly connected to the first complementary bit line BLB1, the gate is used for receiving the column selection signal CY, the fourth input/output pipe source is connected to the fourth input/output line I/O4, the drain is directly connected to the second complementary bit line BLB2, the gate is used for receiving the column selection signal CY, the sixth input/output pipe source is connected to the sixth input/output line I/O6, the drain is directly connected to the third complementary bit line BLB3, the gate is used for receiving the column selection signal CY, the eighth input/output pipe source is connected to the eighth input/output line I/O8, the drain is directly connected to the fourth complementary bit line BLB4, and the gate is used for receiving the column selection signal CY.

The second input/output pipe, the fourth input/output pipe, the sixth input/output pipe, and the eighth input/output pipe are turned on by the same column selection signal CY, so that the level signal transmitted in the first complementary bit line BLB1 is derived through the second input/output line I/O2, the level signal transmitted in the second complementary bit line BLB2 is derived through the fourth input/output line I/O4, the level signal transmitted in the third complementary bit line BLB3 is derived through the sixth input/output line I/O6, and the level signal transmitted in the fourth complementary bit line BLB4 is derived through the eighth input/output line I/O8.

Referring to fig. 3, the left side is the layout of the second interconnect layer, the middle is the layout of the first interconnect layer, the right side is the layout of the structural layer, the regions of the same number represent the layout of the different layers that need to be electrically connected, wherein the inclined frame region is the layout of the active layer, the white frame region is the layout of the gate layer, and the shadow region is the layout of the contact layer.

The first sense amplifying structure is taken as an example for the following description, and the third sense amplifying structure can be analogized according to the drawings, which is not repeated in this embodiment. For a layout of a layer of a structure, the method sequentially comprises the following steps from top to bottom: the first data read-out module, the first equalization structure < N1>, the first sense amplifying N-pipe < N1425>, the first isolation and offset cancellation integrated module, the second sense amplifying P-pipe < P1400>, the first sense amplifying P-pipe < P1401>, the second isolation and offset cancellation integrated module and the second sense amplifying N-pipe < N1405>.

For the first data read-out module, the gate of the first input/output tube < N1001>, the gate of the third input/output tube < N1003>, the gate of the fifth input/output tube < N1005> and the gate of the seventh input/output tube < N1007> are connected together for receiving the same column selection signal CY, in particular to the first interconnect layer through the contact region 109, and in the first interconnect layer to the second interconnect layer through the contact 201 for receiving the column selection signal CY. Namely, the readout circuit structure of the embodiment can read out the data stored in the continuous 4 storage units through the continuous 4 bit lines arranged in parallel according to the same column selection signal; it should be noted that, in a specific application, the number of input/output pipes controlled by the same column selection signal may be set according to the actual requirement, that is, the number of data to be read by the same column selection signal.

In addition, as can be seen from the figure, the first input/output tube < N1001>, the third input/output tube < N1003>, the fifth input/output tube < N1005> and the seventh input/output tube < N1007> are arranged in a staggered manner, wherein the contact areas 105, 106, 107 and 108 between the "H" type gates are used to connect the first bit line BL1, the second bit line BL2, the third bit line BL3 and the fourth bit line BL4, respectively. Contact regions 101, 102, 103 and 104 outside the "H" type gate are used to connect to I/O1, I/O3, I/O5 and I/O7, respectively, at the first interconnect layer.

Further, in the direction in which the word lines extend, the pitches between the first bit line BL1, the second bit line BL2, the third bit line BL3, and the fourth bit line BL4 to which the first data sense module 114 is connected are equal.

For the first equalizing structure < N1>, the source is connected to the first interconnect layer through the contact region 110, to the second interconnect layer through the contact region 202 in the first interconnect layer, and to the precharge voltage V _BLP in the second interconnect layer; the drain is connected to the first interconnect layer through the contact region 111, where it is connected to the first bit line BL1, i.e. the first equalizing structure < N1> is used to precharge the first bit line BL 1.

For the first sense amplifying N-pipe < N1400>, the gate is connected to the first interconnect layer through contact regions 110 and 120, the first bit line BL1 is connected to the first interconnect layer, the source is connected to the first interconnect layer through contact region 117, the first complementary sense bit line SABLB1 is connected to the first interconnect layer, the drain is connected to the first interconnect layer through contact region 116, the first interconnect layer is connected to the second interconnect layer through contact region 206, the second interconnect layer is used to contact the second control signal NCS, and the second control signal NCS is used to provide a low level signal during the sense phase.

For the first isolation and offset cancellation integrated module, including first offset cancellation tube < N1401> and first isolation tube < N1402>, first offset cancellation tube < N1401> and first isolation tube < N1402> share a source, the source is connected to a first interconnect layer through contact region 124, first bit line BL1 is connected at the first interconnect layer, first offset cancellation tube < N1401> drain is connected to the first interconnect layer through contact region 122, first complementary sense bit line SABLB1 is connected at the first interconnect layer, first isolation tube < N1402> drain is connected to the first interconnect layer through contact region 126, first sense bit line SABL1 is connected at the first interconnect layer.

For the second sense amplifying P-pipe < P1400>, the gate is connected to the first interconnect layer through the contact regions 128 and 133, the first complementary sense bit line SABLB is connected to the first interconnect layer, the source is connected to the first interconnect layer through the contact region 130, the first sense bit line SABL1 is connected to the first interconnect layer, the drain is connected to the first interconnect layer through the contact region 131, the first interconnect layer is connected to the second interconnect layer through the contact region 208, the first control signal PCS is received at the second interconnect layer, and the first control signal PCS is used to provide a high level signal during the sense phase.

For the first sense amplifying P-pipe < P1401>, the gate is connected to the first interconnect layer through the contact regions 134 and 139, the first sense bit line SABL1 is connected to the first interconnect layer, the source is connected to the first interconnect layer through the contact region 136, the first complementary sense bit line SABLB1 is connected to the first interconnect layer, the drain is connected to the first interconnect layer through the contact region 135, the first interconnect layer is connected to the second interconnect layer through the contact region 209, and the first control signal PCS is received at the second interconnect layer.

For the second isolation and offset cancellation integrated module, including the second isolation tube < N1403> and the second offset cancellation tube < N1404>, the second isolation tube < N1403> and the second offset cancellation tube < N1404> share a source, the source is connected to the first interconnect layer through the contact region 143, the first complementary bit line BLB1 is connected to the first interconnect layer through the contact region 141, the second isolation tube < N1403> drain is connected to the first complementary sense bit line SABLB through the contact region 141, the second offset cancellation tube < N1404> drain is connected to the first interconnect layer through the contact region 145, and the first sense bit line SABL1 is connected to the first interconnect layer.

For the second sense amplifying N-tube < N1405>, the gate is connected to the first interconnect layer through contact regions 147 and 152, the first complementary bit line BLB1 is connected to the first interconnect layer through contact region 149, the first sense bit line SABL1 is connected to the first interconnect layer, the drain is connected to the first interconnect layer through contact region 150, the first interconnect layer is connected to the second interconnect layer through contact region 211, the second interconnect layer is used to contact the second control signal NCS, and the second control signal NCS is used to provide a low level signal during the read phase.

For the first complementary bit line BLB1, referring to fig. 4, the first complementary bit line BLB1 located in the first interconnect layer is connected to the second interconnect layer through the contact regions 404 and 412, and is routed in the second interconnect layer, thereby reducing the layout area of the sense circuit structure.

Referring to fig. 4, the left side is the layout of the second interconnect layer, the middle is the layout of the first interconnect layer, the right side is the layout of the structural layer, the regions of the same number represent the layout of the different layers that need to be electrically connected, wherein the inclined frame region is the layout of the active layer, the white frame region is the layout of the gate layer, and the shadow region is the layout of the contact layer.

The second sense amplifying structure is taken as an example for the following description, and the fourth sense amplifying structure can be analogized according to the drawings, which is not repeated in this embodiment. For a layout of a layer of a structure, the method sequentially comprises the following steps from top to bottom: the fourth sense amp N-tube < N1425>, the fourth integrated module for isolation and offset cancellation, the third sense amp P-tube < P1421>, the fourth sense amp P-tube < P1420>, the third integrated module for isolation and offset cancellation, the third sense amp N-tube < N1420>, the second equalization structure < N2>, and the second data readout module.

For the fourth sense amp N-tube < N1425>, the gate is connected to the first interconnect layer through contact regions 348 and 350, the second bit line BL2 is connected to the first interconnect layer through contact region 349, the second complementary sense bit line SABLB is connected to the first interconnect layer through contact region 348, the drain is connected to the first interconnect layer through contact region 348, the second interconnect layer through contact region 410, the second control signal NCS is provided for contacting the second control signal NCS at the second interconnect layer, and the second control signal NCS is provided for providing a low level signal during the sense phase.

For the fourth isolation and offset cancelled integrated module, for the second isolation and offset cancelled integrated module, comprising a fourth isolation tube < N1423> and a fourth offset cancelled tube < N1424>, the fourth isolation tube < N1423> and the fourth offset cancelled tube < N1424> share a source, the source is connected to the first interconnect layer through contact region 342, the second bit line BL2 is connected to the first interconnect layer, the fourth isolation tube < N1423> drain is connected to the first interconnect layer through contact region 340, the second sense bit line SABL2 is connected to the first interconnect layer, the fourth offset cancelled tube < N1424> drain is connected to the first interconnect layer through contact region 344, and the second complementary sense bit line SABLB is connected to the first interconnect layer.

For the third sense amplifying P-pipe < P1421>, the gate is connected to the first interconnect layer through the contact region 338, the second complementary sense bit line SABLB is connected to the first interconnect layer through the contact region 335, the second sense bit line SABL2 is connected to the first interconnect layer through the contact region 335, the drain is connected to the first interconnect layer through the contact region 336, the second interconnect layer through the contact region 409, and the first control signal PCS is received at the second interconnect layer.

For the fourth sense amplifying P-pipe < P1420>, the gate is connected to the first interconnect layer through the contact region 327, the second sense bit line SABL2 is connected to the first interconnect layer through the contact region 330, the source is connected to the first interconnect layer, the second complementary sense bit line SABLB is connected to the first interconnect layer through the contact region 329, the drain is connected to the second interconnect layer through the contact region 407, the first control signal PCS is received at the second interconnect layer, and the first control signal PCS is used to provide a high level signal during the sense phase.

For the third isolation and offset cancellation integrated module, including the third offset cancellation tube < N1421> and the third isolation tube < N1422>, the third offset cancellation tube < N1421> and the third isolation tube < N1422> share a source, the source is connected to the first interconnect layer through contact region 323, the second complementary bit line BLB2 is connected to the first interconnect layer through contact region 321, the third offset cancellation tube < N1421> drain is connected to the first interconnect layer through contact region 321, the second sense bit line SABL2 is connected to the first interconnect layer, the third isolation tube < N1422> drain is connected to the first interconnect layer through contact region 325, and the second complementary sense bit line SABLB is connected to the first interconnect layer.

For the third sense amplifying N-pipe < N1420>, the gate is connected to the first interconnect layer through contact regions 314 and 319, the second complementary bit line BLB2 is connected to the first interconnect layer, the source is connected to the first interconnect layer through contact region 316, the second sense bit line SABL2 is connected to the first interconnect layer, the drain is connected to the first interconnect layer through contact region 317, the first interconnect layer is connected to the second interconnect layer through contact region 406, the second interconnect layer is used to contact the second control signal NCS, which is used to provide a low level signal during the sense phase.

For the second equalizing structure < N2>, the source is connected to the first interconnect layer through the contact region 310, to the second interconnect layer through the contact region 402 in the first interconnect layer, and to the precharge voltage V _BLP in the second interconnect layer; the drain is connected to the first interconnect layer through contact region 312 where it is connected to the second complementary bit line BLB2, i.e. the second equalization structure < N2> is used to precharge the second complementary bit line BLB 2.

For the second data read-out module, the gate of the second input/output tube < N1002>, the gate of the fourth input/output tube < N1004>, the gate of the sixth input/output tube < N1006> and the gate of the eighth input/output tube < N1008> are connected together for receiving the same column selection signal CY, in particular to the first interconnect layer via the contact area 309, and in the first interconnect layer to the second interconnect layer via the contact 201 for receiving the column selection signal CY. Namely, the readout circuit structure of the embodiment can read out the data stored in the continuous 4 storage units through the continuous 4 complementary bit lines arranged in parallel according to the same column selection signal; it should be noted that, in a specific application, the number of input/output pipes controlled by the same column selection signal may be set according to the actual requirement, that is, the number of data to be read by the same column selection signal.

In addition, it can be seen that the second input/output tube < N1002>, the fourth input/output tube < N1004>, the sixth input/output tube < N1006> and the eighth input/output tube < N1008> are arranged in a staggered manner, wherein the contact areas between the "H" -type gates are used for connecting the first complementary bit line BLB1, the second complementary bit line BLB2, the third complementary bit line BLB3 and the fourth complementary bit line BLB4, respectively. Contact regions 301, 302, 303, and 304 outside the "H" shaped gate are used to connect to I/O2, I/O4, I/O6, and I/O8, respectively, at the first interconnect layer.

Further, in the direction in which the word lines extend, the pitches between the first, second, third, and fourth complementary bit lines BLB1, BLB2, BLB3, and BLB4 to which the second data sense module 124 is connected are equal.

For the second bit line BL2, referring to fig. 3, the second bit line BL2 located in the first interconnect layer is connected to the second interconnect layer through the contact regions 204 and 212, and is routed in the second interconnect layer, thereby reducing the layout area of the sense circuit structure.

Compared with the related art, the first equalization structure is directly connected with the first bit line or the first complementary bit line and is used for precharging the first bit line and the first complementary bit line, the second equalization structure is directly connected with the second bit line or the second complementary bit line and is used for precharging the second bit line and the second complementary bit line, the third equalization structure is directly connected with the third bit line or the third complementary bit line and is used for precharging the third bit line and the third complementary bit line, the fourth equalization structure is directly connected with the fourth bit line or the fourth complementary bit line and is used for precharging the fourth bit line and the fourth complementary bit line, and the bit line is directly precharged through the equalization structure, so that the switching transistor is prevented from being conducted in the precharging process to precharge the bit line, and the charging speed of the bit line is accelerated; further, at least part of one of the first bit line or the first complementary bit line is provided in the second interconnect layer, the other is provided in the first interconnect layer, at least part of one of the second bit line or the second complementary bit line is provided in the second interconnect layer, the other is provided in the first interconnect layer, at least part of one of the third bit line or the third complementary bit line is provided in the second interconnect layer, the other is provided in the first interconnect layer, at least part of one of the fourth bit line or the fourth complementary bit line is provided in the second interconnect layer, and the other is provided in the first interconnect layer.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of carrying out the application and that various changes in form and details may be made therein without departing from the spirit and scope of the application.

Claims

1. A readout circuit structure disposed in a gap between adjacent memory arrays, comprising:

the structure layer, the first interconnection layer and the second interconnection layer which are stacked on top of the structure layer;

The structure layer is provided with a first sensing amplifying structure, a second sensing amplifying structure, a first balancing structure and a second balancing structure;

The first sense amplifying structure is connected with one of the adjacent memory arrays through a first bit line, the first sense amplifying structure is connected with the other of the adjacent memory arrays through a first complementary bit line, the second sense amplifying structure is connected with one of the adjacent memory arrays through a second bit line, and the second sense amplifying structure is connected with the other of the adjacent memory arrays through a second complementary bit line;

Wherein one of the first bit line or the first complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; one of the second bit line or the second complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer;

Wherein the first sense amplifying structure includes:

a first sense amplifying module connected to the first bit line through a first sense bit line, connected to the first complementary bit line through a first complementary sense bit line, for sensing a voltage of a memory cell of the memory array and outputting a logic 1 or 0 corresponding to the voltage;

A first isolation module connected between the first complementary sense bit line and the first complementary bit line and between the first sense bit line and the first bit line for isolating signal interactions between the first complementary sense bit line and the first complementary bit line and between the first sense bit line and the first bit line, respectively, according to an isolation signal;

The first offset cancellation module is connected between the first read bit line and the first complementary bit line and between the first complementary read bit line and the first bit line, and is used for adjusting the source-drain conduction difference between NMOS (N-channel metal oxide semiconductor) tubes or between PMOS (P-channel metal oxide semiconductor) tubes in the first sense amplification module according to an offset cancellation signal;

the second sense amplifying structure includes:

a second sense amplifying module connected to the second bit line through a second sense bit line, connected to the second complementary bit line through a second complementary sense bit line, for sensing a voltage of a memory cell of the memory array and outputting a logic 1 or 0 corresponding to the voltage;

a second isolation module connected between the second complementary sense bit line and the second complementary bit line and between the second sense bit line and the second bit line for isolating signal interactions between the second complementary sense bit line and the second complementary bit line and between the second sense bit line and the second bit line, respectively, according to an isolation signal;

The second offset cancellation module is connected between the second read bit line and the second complementary bit line and between the second complementary read bit line and the second bit line, and is used for adjusting the source-drain conduction difference between NMOS (N-channel metal oxide semiconductor) tubes or between PMOS (P-channel metal oxide semiconductor) tubes in the second sense amplification module according to an offset cancellation signal;

The first equalization structure is directly connected with the first bit line or the first complementary bit line and is used for precharging the first bit line, the first complementary bit line and the first sense amplifying structure;

the second equalization structure is directly connected to the second bit line or the second complementary bit line for precharging the second bit line, the second complementary bit line and the second sense amplifying structure.

2. The sensing circuit structure of claim 1, wherein the first bit line is disposed in the first interconnect layer, at least a portion of the first complementary bit line is disposed in the second interconnect layer, the first complementary bit line is coupled to the first sense amplifying structure after passing through a region of the second sense amplifying structure in the second interconnect layer, at least a portion of the second bit line is disposed in the second interconnect layer, the second bit line is coupled to the second sense amplifying structure after passing through a region of the first sense amplifying structure in the second interconnect layer, and the second complementary bit line is disposed in the first interconnect layer.

3. The readout circuit structure according to claim 2, characterized by comprising:

the first equalization structure is arranged on one side of the first sense amplifying structure far away from the second sense amplifying structure, and the first equalization structure is directly connected with the first bit line;

The second equalization structure is arranged on one side, far away from the first sense amplification structure, of the second sense amplification structure, and the second equalization structure is directly connected with the second complementary bit line.

4. The readout circuit structure according to claim 1, characterized by comprising:

The first equalization structure comprises a first equalization tube, wherein a grid electrode of the first equalization tube is used for receiving a first equalization signal, one of a source electrode or a drain electrode is connected with the first bit line or the first complementary bit line, the other one is used for receiving a first precharge voltage, and the first bit line, the first complementary bit line and the first sense amplification structure are precharged to the first precharge voltage based on the first equalization signal;

the second equalization structure includes a second equalization tube having a gate for receiving a second equalization signal, one of a source or a drain connected to the second bit line or the second complementary bit line, the other for receiving a second precharge voltage for precharging the second bit line, the second complementary bit line, and the second sense amplifying structure to the second precharge voltage based on the second equalization signal.

5. The sensing circuit structure of claim 4, wherein the first and second equalization signals are the same equalization signal and the first and second precharge voltages are the same precharge voltage.

6. The readout circuit structure according to claim 1, characterized by comprising:

the structure layer is also provided with a third sensing amplifying structure, a fourth sensing amplifying structure, a third equalizing structure and a fourth equalizing structure;

The third sense amplifying structure is connected with one of the adjacent memory arrays through a third bit line, the third sense amplifying structure is connected with the other of the adjacent memory arrays through a third complementary bit line, the fourth sense amplifying structure is connected with one of the adjacent memory arrays through a fourth bit line, and the fourth sense amplifying structure is connected with the other of the adjacent memory arrays through a fourth complementary bit line;

wherein one of the third bit line or the third complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; one of the fourth bit line or the fourth complementary bit line is disposed in the second interconnect layer, and at least a portion of the other is disposed in the second interconnect layer;

The third equalization structure is directly connected to the third bit line or the third complementary bit line and is used for precharging the third bit line, the third complementary bit line and the third sense amplifying structure;

The fourth equalization structure is directly connected to the fourth bit line or the fourth complementary bit line for precharging the fourth bit line, the fourth complementary bit line and the fourth sense amplifying structure.

7. The readout circuit structure according to claim 6, wherein a first data readout module and a second data readout module are further provided in the structural layer;

a first data readout module comprising: a first input/output pipe, a third input/output pipe, a fifth input/output pipe, and a seventh input/output pipe;

the source electrode of the first input/output pipe is connected with the first input/output line, the drain electrode of the first input/output pipe is connected with the first bit line, the source electrode of the third input/output pipe is connected with the third input/output line, the drain electrode of the third input/output pipe is connected with the second bit line, the source electrode of the fifth input/output pipe is connected with the fifth input/output line, the drain electrode of the seventh input/output pipe is connected with the third bit line, and the drain electrode of the seventh input/output pipe is connected with the seventh input/output line;

The first bit line, the second bit line, the third bit line and the fourth bit line are four adjacent bit lines in the same memory array;

the grid electrode of the first input/output tube, the grid electrode of the third input/output tube, the grid electrode of the fifth input/output tube and the grid electrode of the seventh input/output tube are connected together and are used for receiving a column selection signal and conducting the first input/output tube, the third input/output tube, the fifth input/output tube and the seventh input/output tube based on the column selection signal;

the second data reading module comprises a second input/output pipe, a fourth input/output pipe, a sixth input/output pipe and an eighth input/output pipe;

The source electrode of the second input/output tube is connected with the second input/output line, the drain electrode of the second input/output tube is connected with the first complementary bit line, the source electrode of the fourth input/output tube is connected with the fourth input/output line, the drain electrode of the fourth input/output tube is connected with the second complementary bit line, the source electrode of the sixth input/output tube is connected with the sixth input/output line, the drain electrode of the eighth input/output tube is connected with the third complementary bit line, the source electrode of the eighth input/output tube is connected with the eighth input/output line, and the drain electrode of the eighth input/output tube is connected with the fourth complementary bit line;

the first complementary bit line, the second complementary bit line, the third complementary bit line and the fourth complementary bit line are four adjacent bit lines in the same memory array;

The grid electrode of the second input/output tube, the grid electrode of the fourth input/output tube, the grid electrode of the sixth input/output tube and the grid electrode of the eighth input/output tube are connected together and used for receiving the column selection signals and conducting the second input/output tube, the fourth input/output tube, the sixth input/output tube and the eighth input/output tube based on the column selection signals.

8. The sensing circuit structure of claim 7, comprising:

The first data reading module is arranged on one side of the first equalization structure and the third equalization structure far away from the first sense amplifying structure and the third sense amplifying structure;

the second data reading module is arranged on one side of the second equalization structure and one side of the fourth equalization structure, which are far away from the second sense amplifying structure and the fourth sense amplifying structure.

9. The sensing circuit structure of claim 1, wherein the first sense amplification module comprises:

The first sense amplifying N-tube has a grid electrode connected with the first bit line, a drain electrode connected with the complementary read bit line, and a source electrode connected with a second signal end, wherein when the first sense amplifying module is in an amplifying stage, the second signal end is electrically connected with a voltage corresponding to logic 0;

A second sense amplifier N-tube, wherein the grid electrode is connected with the first complementary bit line, the drain electrode is connected with the read bit line, and the source electrode is connected with the second signal end;

The first sense amplifying P tube has a grid electrode connected with the read bit line, a drain electrode connected with the complementary read bit line, a source electrode connected with a first signal end, and when the first sense amplifying module is in an amplifying stage, the first signal end is electrically connected with a voltage corresponding to logic 1;

and the grid electrode of the second sensing amplification P pipe is connected with the complementary read bit line, the drain electrode of the second sensing amplification P pipe is connected with the read bit line, and the source electrode of the second sensing amplification P pipe is connected with the first signal end.

10. The readout circuit structure of claim 9, wherein the gate structure of the first sense amplifying N-tube, the gate structure of the second sense amplifying N-tube, the gate structure of the first sense amplifying P-tube, and the gate structure of the second sense amplifying P-tube extend in the same direction, the gate structure of the MOS tube in the first isolation module and the gate structure of the MOS tube in the first offset cancellation module extend in the same direction, and the gate structure of the first sense amplifying N-tube and the gate structure of the MOS tube in the first isolation module extend in directions perpendicular to each other.

11. The sensing circuit structure of claim 9, wherein the first sense amp P-tube, the second sense amp P-tube, the first isolation module, and the first offset cancellation module are disposed between the first sense amp N-tube and the second sense amp N-tube.

12. The sensing circuit structure of claim 1, wherein the first isolation module comprises:

The first isolation tube is used for receiving the isolation signal, the source electrode is connected with the first bit line, and the drain electrode is connected with the readout bit line;

And the grid electrode of the second isolation tube is used for receiving the isolation signal, the source electrode of the second isolation tube is connected with the first complementary bit line, and the drain electrode of the second isolation tube is connected with the complementary read-out bit line.

13. The sensing circuit structure of claim 12, wherein the first offset cancellation module comprises:

A first offset cancellation pipe having a gate for receiving the offset cancellation signal, a source connected to the first bit line, and a drain connected to the complementary sense bit line;

And the grid electrode of the second offset elimination tube is used for receiving the offset elimination signal, the source electrode of the second offset elimination tube is connected with the first complementary bit line, and the drain electrode of the second offset elimination tube is connected with the read bit line.

14. The sense circuit structure of claim 13 wherein the source of the first isolation tube communicates with the source of the first offset cancellation tube and is connected to the first bit line; the source of the second isolation tube is connected with the source of the second offset cancellation tube and is connected with the first complementary bit line.