CN115561942A

CN115561942A - Display panel, display device and manufacturing method

Info

Publication number: CN115561942A
Application number: CN202211389548.0A
Authority: CN
Inventors: 任丹丹; 李志勇; 储周硕; 祁小敬
Original assignee: BOE Technology Group Co Ltd; Chengdu CEC Panda Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu CEC Panda Display Technology Co Ltd
Priority date: 2022-11-08
Filing date: 2022-11-08
Publication date: 2023-01-03

Abstract

The invention discloses a display panel, a display device and a manufacturing method, wherein the display panel of one embodiment comprises the following components: the first substrate comprises a first area, a second area positioned on one side of the first area and a second substrate which is arranged opposite to the first substrate in a box; the first region includes a display area, and the second region includes: a cutting region, a plurality of test terminals, a plurality of ground potentials, and a charge-draining structure, the second region further comprising: the charge drainage structure comprises a starting drainage part which at least partially overlaps with the orthographic projection of the first substrate and the orthographic projection of the cutting area on the first substrate; and a termination drain connected to either of the ground potential or the ground line.

Description

Display panel, display device and manufacturing method

Technical Field

The invention relates to the technical field of display. And more particularly, to a display panel, a display device and a method of manufacturing.

Background

The display panel usually has some terminals for inspection, called PAD, or inspection TEG, disposed on the Thin Film Transistor (TFT) array substrate at the periphery of the display area, so as to perform a lighting Test to confirm a failure, called CT Test (Cell Test PAD) in advance before the module is produced. After the CT test is completed, the glass including the PADs needs to be cut off to cut off the connection between the PADs and the inside of the panel, and when the color film substrate is cut by using a cutting knife, a display panel generates a large amount of electrostatic charges, so that a film layer on the array substrate is damaged, and defects such as poor wiring and abnormal display occur.

Disclosure of Invention

The present invention is directed to a display panel, a display device and a method for manufacturing the same, which solve at least one of the problems of the prior art.

In order to achieve the purpose, the invention adopts the following technical scheme:

a first aspect of the present invention provides a display panel comprising:

a first substrate including a first region and a second region positioned at one side of the first region,

the second substrate is arranged in a box-to-box mode with the first substrate, wherein the orthographic projection of the second substrate on the first substrate is located in the first area;

the first region includes a display area and a second region,

the second region includes: a cutting region, a plurality of test terminals, a plurality of ground potentials, and a charge-draining structure, the second region further comprising: a ground line for connecting the plurality of ground potentials, and a connection line for connecting each of the test terminals and the driving line in the display region, wherein,

the orthographic projection of the cutting area on the first substrate is in the orthographic projection of the connecting line on the first substrate,

the charge draining structure includes:

the orthographic projection of the initial drainage part on the first substrate is at least partially overlapped with the orthographic projection of the cutting area on the first substrate; and

and a terminal drain connected to any one of the ground potential and the ground line.

Further, the first region includes a first boundary on a side away from the second region, and

a second boundary at which the first region and the second region coincide, the second boundary being parallel to the first boundary,

the ground potential comprises:

a first electrode located adjacent to one side of the first boundary and along a first direction parallel to the first boundary; and

a second electrode located on a side close to the second boundary and arranged along the first direction,

the first electrode and the second electrode are connected to the same potential through the grounding wire.

Further, the test terminal is located at a side close to the first boundary,

the charge draining structure further includes:

a first drainage wire proximate the originating drainage portion; and

a second drainage wire adjacent to the terminating drainage portion,

the first drainage thread is connected with the second drainage thread,

the orthographic projection of the first drainage wire on the first substrate is overlapped with the orthographic projection of the cutting area on the boundary of one side far away from the testing terminal area, and the orthographic projection of the second drainage wire on the first substrate is not overlapped with the orthographic projection of the cutting area on the first substrate.

Further, a distance between the initial drainage portion and a side boundary of the test terminal close to the color film substrate is designed to be a first distance, a distance between a side boundary of the cutting area close to the color film substrate and a side boundary of the test terminal close to the color film substrate is designed to be a second distance, and the second distance is greater than the first distance.

Furthermore, the end of the first drainage wire is the initial drainage part, the first drainage wires are multiple, and in a second direction perpendicular to the first direction, the orthographic projection of each first drainage wire on the orthographic projection of the first substrate covers a part of the orthographic projection of the connecting wire.

Furthermore, the end of the first drainage wire is the initial drainage part, and the orthographic projection of the first drainage wire on the first substrate is a patterned graph and extends along the first direction to cover a plurality of connecting wires arranged along the first direction.

Further, with the extension line extending in the first direction where the connecting position of the first drainage thread and the second drainage thread is located as a boundary line,

when the cutting area and the second drainage wire are positioned on the same side, the orthographic projection of the cutting area on the first substrate is a patterned graph, and the cutting length of the cutting area is smaller than the extension length of the wiring area;

when the cutting area and the second drainage wire are positioned on different sides, the cutting length of the cutting area is less than or equal to the extending length of the wire routing area.

Further, the test terminal includes:

a first test metal layer on the substrate;

at least one first insulating layer located on one side of the first test metal layer away from the substrate; and

a second test metal layer on the first insulating layer on a side away from the first test metal layer,

the first insulating layer is provided with a first through hole, and the first test metal layer and the second test metal layer are electrically connected through the first through hole.

Further, the connecting line includes:

a first connection line metal layer on the substrate; and

a second connection line metal layer insulated from the first connection line metal layer;

the first insulating layer includes:

the first sub-insulating layer is positioned on one side, far away from the substrate, of the first connecting wire metal layer; and

the second sub-insulating layer is positioned on one side, away from the substrate, of the second connecting line metal layer, and the first sub-insulating layer is provided with a second through hole;

the connection line at least comprises one of the first connection line metal layer or the second connection line metal layer, or the first connection line metal layer and the second connection line metal layer are electrically connected through the second via hole,

the first connection line metal layer is connected with the first test metal layer or the second test metal layer, and/or the second connection line metal layer is connected with the first test metal layer or the second test metal layer.

Further, the ground potential includes:

a first ground metal layer on the substrate;

a second ground metal layer on a side of the second sub-insulating layer away from the substrate,

the first sub-insulating layer and the second sub-insulating layer are provided with third via holes,

the first grounding metal layer and the second grounding metal layer are electrically connected through the third via hole and are accessed to a grounding signal;

the metal layer of the connection line is insulated from the metal layer of the ground potential at an overlapping position of the ground potential and the orthographic projection of the connection line on the first substrate.

Furthermore, the charge drainage structure comprises a drainage conductive layer which is positioned on one side of the metal layer of the connecting line far away from the substrate, the drainage conductive layer and the metal layer of the connecting line are arranged in an insulating way,

a first distance exists between the drainage conducting layer corresponding to the starting drainage part and the metal layer of the test terminal on the plane;

and the drainage conducting layer corresponding to the termination drainage part is connected with the first grounding metal layer or the second grounding metal layer.

Further, the first test metal layer, the first connection line metal layer and the first ground metal layer are arranged in the same layer;

the second test metal layer, the second grounding metal layer and the current-guiding conducting layer are arranged on the same layer.

A second aspect of the present invention provides a method for manufacturing a display panel according to any one of the first aspect of the present invention, including:

forming the first substrate on the substrate, wherein the first substrate comprises a first area and a second area positioned on one side of the first area, and the first area comprises a display area;

performing cell pairing on the first substrate and the second substrate, wherein the orthographic projection of the second substrate on the first substrate is positioned in the first area;

forming the first substrate on the substrate includes:

forming a plurality of test terminals, a plurality of ground potentials, and charge drains in the second region;

forming a ground line connecting the plurality of ground potentials in the second region, and a connection line connecting each test terminal and a drive line in a display region, wherein an orthographic projection of the cut region on the first substrate falls within an orthographic projection of the connection line on the first substrate,

forming the charge-draining structure in the second region, the charge-draining structure comprising: the orthographic projection of the initial drainage part on the first substrate is at least partially overlapped with the orthographic projection of the cutting area on the first substrate; and a termination drain connected to either the ground potential or the ground line.

A third aspect of the present invention provides a display device including the display panel of any one of the first to third aspects of the present invention.

A fourth aspect of the present invention provides a method of manufacturing the display device of the first aspect of the present invention, the method comprising:

inputting a test signal to the display panel through a test terminal for electrical detection;

and cutting the display panel which mostly accords with the detection result by taking the cutting area as a cutting position, wherein in the cutting process, the charge drainage structure forms a passage.

The invention has the following beneficial effects:

the display panel of the embodiment of the invention designs the second area outside the array substrate, the charge drainage structure connected with the grounding potential or the grounding wire is arranged on the second area, and the charge drainage structure is arranged to form an overlapping relation with the cutting area, so that a drainage channel is formed when the cutting area is used as a cutting position for cutting, current generated by a test terminal due to a cutting process is introduced into the grounding potential through the charge drainage structure, the electrostatic discharge capacity of the second area of the display panel is improved, and line damage and poor display caused by external high-voltage bombardment or charge accumulation at the test terminal are avoided.

Drawings

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram showing a laser cutting of a connecting line between a detection PAD and a display area;

FIG. 2 is a schematic diagram illustrating a film structure of a test terminal electrostatically damaged during a dicing process;

FIG. 3 is a schematic diagram illustrating a film structure of a thin film transistor of an array substrate electrostatically damaged during a cutting process;

FIGS. 4a to 4e are schematic plan views illustrating different charge draining structures of a display panel according to an embodiment of the present invention;

FIG. 5 showsbase:Sub>A schematic structural view of the test terminal at the A-A' position of the cross-section in FIG. 4 b;

FIG. 6a shows a schematic view of the connecting lines at the location of section D-D' in FIG. 4 b;

FIG. 6b shows another schematic view of the connecting line at the location of section D-D' in FIG. 4 b;

FIG. 7 shows the arrangement of the layer structure of the ground potential at the location of section C-C 'and the ground line at the location of section E-E' in FIG. 4 b;

fig. 8a and 8b show different structural schematics of the ground potential and the connection line at the position of overlap of the connection line at the position of the section F-F' in fig. 4 b;

FIGS. 9a, 9B and 9c show different structural schematics of the connection lines and the charge draining structures at the position of section B-B' of FIG. 4B, when they overlap;

fig. 10 is a schematic structural diagram of a thin film driving transistor in a display region according to an embodiment of the present invention.

Detailed Description

In order to more clearly illustrate the present invention, the present invention is further described below with reference to the following examples and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.

The array substrate includes a driving circuit and a thin film transistor, and in order to detect whether the display panel has defects before the module is produced, so as to perform repair, repair or discard in advance, a plurality of exposed test terminals 121, such as a plurality of test terminals (PAD) a, B, C, D,. N shown in fig. 1, are generally disposed at the periphery of one side of the array substrate. The test terminal 121 is connected to the in-plane line of the display area AA via a connection line 131, and can perform a lighting test on the in-plane line of the display area AA of the array substrate by inputting a PAD test signal. After the detection is finished, the test terminals 121 can be completely cut off along with the glass trimming, or laser is performed on the inner sides of the test terminals 121 to cut off the connecting lines 131 between the test terminals 121 and the in-plane lines of the display area AA, so that the defect that the in-plane lines are damaged due to subsequent bonding connection or PAD corrosion caused by external conditions is avoided.

Fig. 1 shows a schematic view of laser cutting the connecting line 131 between the test terminal 121 and the display area AA at the position of the cutting area 14 by means of laser. In the laser process, whenbase:Sub>A large amount of charges are accumulated on the PAD inbase:Sub>A short time, the film structure below the PAD may be damaged as shown in fig. 2, for example, the second sub-insulating layer 1232, the first sub-insulating layer 1232 and the connecting line 131 (base:Sub>A-base:Sub>A "section in fig. 1) are damaged by downward transmission impact; damage may also be caused to the connection line 131 connected to the PAD, for example, the connection line at the position B-B "in fig. 1, and the film layer and the circuit in the AA surface of the display area may be damaged by being hit over the cutting area 14, which may cause damage to the metal circuit on the TFT array substrate 10;

on the other hand, as shown in fig. 3, a liquid crystal layer 30 is disposed between the color filter substrate 20 and the array substrate 10, and static electricity is transferred to one side of the color filter substrate 20, so that a voltage difference between the common electrode 21 on the color filter substrate 20 and the pixel electrode 176 on the TFT array substrate 10 corresponding to the common electrode is increased, and the voltage returns to the active layer 173 through the drain electrode 176D connected to the pixel electrode 176, thereby causing damage to the thin film driving transistor 17 (i.e., S-D Leak); on the other hand, when the PAD in-plane leads are connected to a COF (Chip on Film) bonding line (not shown), static electricity may also damage the bonding element, the COF, or a PCB member connected to the COF along the leads, eventually causing various display defects.

Based on the above description, in order to solve the problem of poor breakdown of the film layer and the device of the display panel caused by electrostatic discharge when the connection line between the test terminal and the display area is cut off, the invention provides a display panel, a display device and a manufacturing method to solve the problem.

A first embodiment of the present invention proposes a display panel, as shown in fig. 4a, comprising:

a first substrate 10, the first substrate 10 including a first region 10A and a second region 10B on one side of the first region 10A,

a second substrate 20 arranged in a box-to-box relationship with the first substrate 10, wherein an orthographic projection of the second substrate 20 on the first substrate 21 is located in the first region 10A;

the first area 10A comprises a display area AA,

the second region 10B includes: a cutting region 14, a plurality of test terminals 121, a plurality of ground potentials 151, and a charge draining structure 16,

the second region 10B further includes: a ground line 152 connecting the plurality of ground potentials 151, and a connection line 131 connecting each test terminal 141 and a driving line in the display area AA, wherein,

the orthographic projection of the cutting area 14 on the first substrate 10 is overlapped with the orthographic projection of the connecting line 131 positioned in the second area on the first substrate 10.

In a specific example, the first substrate is an array substrate 10, and the second substrate is a color filter substrate 20. The first region 10A is an overlapping region formed by the array substrate 10 and the color filter substrate 20, and the first region 10A includes not only the display region AA but also a routing region extending from the second region 10B to the first region 10A. The second region 10B is an outer region of an overlapping region formed by the array substrate 10 and the color filter substrate 20.

As shown in fig. 4a, the first region 10A includes:

a first boundary 10B1 far away from the second region 10B, where the first boundary 10B1 is an end boundary of the array substrate 10 far away from the color filter substrate 20, and

a second boundary 10B2 at the overlapping position of the first region 10A and the second region 10B, where the second boundary 10B2 is an overlapping boundary of the array substrate 10 and the color filter substrate 20,

the second boundary 10B2 is parallel to the first boundary 10B1, and the second boundary 10B2 and the first boundary 10B1 both extend in the illustrated first direction D1, and perpendicular to the first direction D1 is the illustrated second direction D2.

As shown in fig. 4a, the position relationship of each structure of the second region 10B is: a plurality of test terminals 121 are located in the test terminal area 12, the test terminal area 12 is located on the side of the second area 10B near the first boundary 10B1,

the connecting lines 131 are located in the connecting line area 13, wherein the connecting line area 13 extends from the second area 10B2 to the first area 10B1, and each connecting line 131 connects the test terminal 121 and the driving line of the display area AA, and inputs the test signal to the display area AA by inputting the test signal to the test terminal 121 and using the connecting line 131 to perform the line detection of the display area AA.

In the orthographic projection of the array substrate 10 on the cutting area 14 and the orthographic projection of the connecting line 131 of the second area 10B on the array substrate 10, cutting off the connecting line 131 at the position of the cutting area 14 in the cutting process;

the ground potential regions 15 are formed by a plurality of ground potentials 151 and a ground line 152 connected to the ground potentials 151, and a ground signal is applied to any one of the ground potentials 151 and the connection line 131.

As shown in fig. 4a, the charge draining structure 16 includes:

an initial drainage part 161, wherein an orthographic projection of the initial drainage part 161 on the array substrate 10 at least partially overlaps with an orthographic projection of the cutting area 14 on the array substrate 10; and

a termination drain 162, wherein the termination drain 162 is connected to either the ground potential 151 or the ground line 152.

The display panel of the embodiment of the invention designs the second area 10B outside the array substrate 10, the charge drainage structure 16 connected with the grounding potential or the grounding wire is arranged on the second area 10B, and the charge drainage structure 16 is arranged to form an overlapping relation with the cutting area 14, so that a drainage path is formed when the cutting area 14 is used as a cutting position for cutting, current generated by the test terminal 121 due to a cutting process is led into the grounding potential through the charge drainage structure 16, the electrostatic discharge capability of the second area 10B of the display panel is improved, and line damage and poor display caused by external high-voltage bombardment or charge accumulation at the test terminal are avoided.

As shown in fig. 4a, an orthographic area of the array substrate 10 is larger than an orthographic area of the color filter substrate 20, an overlapping region is formed after the array substrate 10 and the color filter substrate 20 are paired, that is, a first region 10A, a second region 10B according to an embodiment of the present invention includes both an overlapping boundary (a second boundary 10B 2) formed by the array substrate 10 and the color filter substrate 20, and a non-overlapping region of the array substrate 10 located outside an orthographic projection of the color filter substrate 20, and the second region 10B is arranged to extend along a first direction D1.

In an alternative embodiment, the orthographic projections of the adjacent test terminals 121 in the first direction D1 on the array substrate 10 do not overlap, that is, each test terminal 121 is provided with insulation, and a line connection path with the display area AA is ensured. In one specific example, as shown in fig. 4b, the boundary distance between adjacent test terminals 121 is a fifth distance d5, which is exemplarily determined according to the deposition accuracy of the deposition process.

In an alternative embodiment, as shown in fig. 4b, the ground potential 151 comprises a first electrode 1511 and a second electrode 1512.

The first electrode 1511 (VM 1, VM 2) is provided at a position close to the first boundary 10B1, and the first electrode 1511 (VM 1) and the first electrode 1511 (VM 2) are connected by the ground line 152 to form a Vcom potential, i.e., a ground potential.

In an alternative embodiment, the first electrode 1511 is close to the first boundary 10B1, and the fourth distance d4 is provided between the ground line 152 connecting the adjacent first electrodes 1511 and the first boundary 10B1, by which the first electrode 1511 and the ground line 152 are prevented from being damaged by an accuracy error generated when the array substrate 10 is cut with the first boundary 10B1 as a cutting position.

In another alternative embodiment, the minimum distance d3 between the first electrode 1511 and the test terminal 121 is greater than or equal to twice the fifth distance, i.e., d3 ≧ 2 × d5, to ensure the insulating arrangement between the first electrode 1511 and the test terminal 121 to avoid signal crosstalk. In addition, orthographic projections of the test terminal 121, the first electrode 1511 and the second electrode 1512 in the second region do not overlap, so that the insulating arrangement between the test terminal 121, the first electrode 1511 and the second electrode 1512 is ensured, and signal crosstalk is avoided.

As shown in fig. 4B, the second electrodes 1512 (VM 3, VM4, VM 5) are located on one side close to the second boundary 10B1 and arranged along the extending direction parallel to the first boundary 10B1, adjacent second electrodes 1512 are connected by the grounding line 152, and the first electrode 1511 and the second electrode 1512 are also connected by the grounding line 152, so that the first electrode 1511 and the second electrode 1512 are connected to the same potential through the grounding line 152.

The embodiment of the present invention does not limit the specific arrangement positions, the specific number, and the distance between adjacent first electrodes 1511 of the plurality of first electrodes 1511 near the first boundary 10B1, and also does not limit the specific arrangement positions, the specific number, and the distance between adjacent second electrodes 1512 of the plurality of second electrodes 1512 near the second boundary 10B2, and those skilled in the art perform the setting according to practical applications, and are not described herein again.

In an alternative embodiment, as shown in fig. 4b, the orthographic projection of the test terminal 121 on the array substrate 10 is larger than the orthographic projection area of the ground potential 151 on the array substrate 10, and in consideration of the poor accuracy of the external signal pointing, by this arrangement, the area of the detection PAD is set to be larger, so as to improve the signal access accuracy.

In an embodiment of the present invention, as shown in fig. 4c and 4d, the termination tap 162 is connected to at least one of the first electrode 1511, the second electrode 1512, and the ground line 152.

In a specific example, as shown in fig. 4b, the termination drains 162 corresponding to the test terminals A1 and A2 are connected to the first electrode 1511 (VM 1) at the upper left corner, and the termination drains 162 corresponding to the test terminals An are connected to the ground line 152 at the right side.

In a specific example, as shown in fig. 4c, the termination drains 162 corresponding to the test terminals B1 and B2 … Bn are connected to the second electrodes 1512 (VM 4 and VM 5) on the second boundary 10B2 side, and the ground of the termination drains 162 is implemented.

In a specific example, as shown in fig. 4d, the termination drains 162 corresponding to the test terminals A1 and A2 … An are connected to the first electrode 1511 (VM 1) on the first boundary 10B1 side, and the termination drains 162 are grounded.

Based on the above examples, the embodiment of the present invention does not limit which ground potential 151 is specifically connected to the termination drain 162, or which ground line 152 is specifically connected to, and any design of the second region 10B based on the embodiment of the present invention can achieve the grounding of the charge draining structure 16 is within the protection scope of the embodiment of the present invention.

In an alternative embodiment, as shown in fig. 4b, 4c and 4d, the charge draining structure 16 further comprises:

a first drainage thread 163 adjacent to the initial drainage portion 161; and

a second drainage wire 164, adjacent to the terminating drain 162,

the first and

second drain wires

163 and 164 are connected,

the orthographic projection of the first drainage wire 163 in the second zone 10B overlaps with the orthographic projection of the boundary of the cut zone 14 on the side away from the test terminal 121 (e.g., the boundary corresponding to the dashed line of the cut zone 14 in fig. 4B), and the orthographic projection of the second drainage wire 164 in the second zone 10B does not overlap with the orthographic projection of the cut zone 14 in the second zone 10B.

In this embodiment, the start drain 161 is an end of the first lead 163 on the side close to the test terminal 121, and the end drain 162 is an end of the second lead 164 connected to the ground potential (the first electrode 1511, the second electrode 1512, or the ground line 152).

In the embodiment of the present invention, the positions or connection relationships between the charge draining structure 16 and the ground potential connected thereto, and between the charge draining structure and the test terminal 121 are as follows:

the start tap 161 is disposed at a position close to the test terminal 121 but at a distance from the test terminal 121, that is, the start tap 161 is disposed insulated from the test terminal 121,

one end of the first drainage wire 163 is connected to the start drainage 161, the other end of the first drainage wire 163 is connected to the second drainage wire 164, and the other end of the second drainage wire 164 is connected to the ground potential 151, such as the first electrode 1511, the second electrode 1512, or the ground 152;

in the embodiment of the present invention, the specific lengths and the specific interface positions of the first drainage wire 163 and the second drainage wire 164 are not limited, but it is set as a basis that whether the orthographic projection of the first drainage wire 163 overlaps the cutting region 14 for transferring the electric charges near the cutting region 14 through the initial drainage portion 161, and whether the second drainage wire 164 overlaps the cutting region 14 for preventing the line connecting the electric charge drainage structure 16 to the ground potential from being cut off during the cutting process, so that the electric charge drainage structure 16 cannot be formed.

In a specific example, as shown in fig. 4b, the start drains 161 of the test terminals A1 and A2 are connected to the first electrode 1511 through the same termination drain 162, and the drain circuits of the start drains 161 of the test terminals A1 and A2 are the same circuit on the side close to the termination drain 162, and in fig. 4b, the same circuit is defined as the second drain 164, and the second drain 164 has an "l" shape. At this time, the crossing points of the first and

second drains

163 and 164 of the test terminal A1 are positioned at X1 and X2 points, the first drain 163 has a '+' shape structure, and similarly, the first drain 163 adjacent to the test terminal A2 also has a '+' shape structure.

In another specific example, as shown in fig. 4d, the test terminal A1, the test terminal A2, and the start drain 161 corresponding to An are all connected to the first electrode 1511 through the same end drain 162, and the drain circuits of the start drains 161 corresponding to the test terminal A1 and the test terminal A2 are the same circuit on the side close to the end drain, but this embodiment does not define this "l" shaped drain circuit as the second drain.

As shown in fig. 4d, in the present example, in the orthographic projection formed by the second zone 10B, the boundary between the end of the drainage wire covering the connecting wire 131 and the end of the drainage wire on the side of the connection termination drainage portion 162 is defined as a boundary point, the first drainage wire 163 is located on the side close to the start drainage portion 161, and the second drainage wire 164 is located on the side close to the termination drainage portion 162, that is, points X3, X4, and X5 shown in fig. 4d are defined as boundary points of the first drainage wire 163 and the second drainage wire 164 corresponding to different test terminals. Under this structure, the second conduction leads 164 are all "L" shaped structures, and the first conduction leads 163 of the start conduction portions 161 corresponding to different test terminals are "L" shaped structures.

In another specific example, as shown in fig. 4c, the first flow-guide line 163 has a block-shaped structure, and the second flow-guide line 164 has a plurality of bar-shaped connecting lines, and in this example, the boundary line formed by the first flow-guide line 163 and the second flow-guide line 164 is defined as a boundary point, such as a connecting line YY extending along the first direction D1 and formed by two Y points as shown in fig. 4 c.

Therefore, the embodiment of the present invention does not limit the specific intersection positions of the first and

second drainage wires

163 and 164, and the design criteria are that the first drainage wire 163 overlaps the cutting region 14, the second drainage wire 164 does not overlap the cutting region 14, and the integrity of the charge drainage path is ensured, which is not described herein again.

It should be noted that although the charge draining structure 16 is divided into different parts according to the embodiment of the present invention, the initial draining part 161, the first draining line 163, the second draining line 164 and the final draining part 162 are not shown to be independent structures, and the embodiment of the present invention is defined only for the purpose of clearly explaining the structure of the charge draining structure 16 in a planar state.

There are different designs of the first drainage wire 163 according to the embodiment of the present invention, as shown in fig. 4a and 4d, the first drainage wire 163 has a plurality of bar-shaped structures, and as shown in fig. 4c, the first drainage wire 163 has a block-shaped structure.

Further, the charge draining structure 16 of the embodiment of the present invention may be a combined structure as shown in fig. 4c and fig. 4D, and as shown in fig. 4e, the test terminal area 12 includes a plurality of test terminals 121 arranged along the first direction D1. The plurality of test terminals 121 form a test terminal group, a charge drainage structure 16 is arranged corresponding to one test terminal, a plurality of charge drainage structures arranged in the first direction D1 are formed, the test terminal groups located at different positions are used for carrying out partition detection on the display area AA, and the corresponding charge drainage structures 16 are used for protecting the film layers at corresponding positions to avoid electrostatic discharge.

For example, as shown in fig. 4d, A1 and A2 … An are a test terminal set capable of detecting the lines on the left side of the display area AA, and the charge draining structure 16 corresponding to the test terminal set is the structure shown in fig. 4 d; b1 and B2 … Bn are another testing terminal group capable of detecting the line on the right side of the display area AA, and the charge draining structure 16 corresponding to the testing terminal group is the structure shown in fig. 4c, so that the partitioned detection is realized, and the detection precision is improved. For example, for a large-size high-resolution product, the number of signals accessing the display area AA is large, and the partition detection can be realized through the above setting.

In an alternative embodiment, as shown in fig. 4a and 4D, the number of first flow-guide lines 163 is the same as the number of connecting lines 131, i.e., the orthographic projection of the first flow-guide lines 163 on the second region 10B covers part of the orthographic projection of the connecting lines 131 in a direction perpendicular to the first boundary 10B1 (i.e., the second direction D2). In this structure, there are a plurality of first drains 163, that is, there are a plurality of start drains 161 or each start drain 161 corresponds to each test terminal 121.

Under this structure, as shown in fig. 4a, the orthographic projection of the first conduction threads 163 on the second area 10B is displayed as a plurality of strip-shaped structures, the extending direction of each strip-shaped first conduction thread 163 is the direction from the second area 10B to the display area AA, i.e., the second direction D2, each first conduction thread 163 covers a part of the connection line 131 in the direction, i.e., each first conduction thread 163 is disposed at the position of the corresponding connection line 131, and the connection line 131 at the covered position is protected by the first conduction thread 163, so as to avoid the problem that a large amount of static electricity generated during the cutting process forms a breakdown damage to the routing inside the display area AA through the connection line 131.

In another alternative embodiment, rather than the first flow-guide lines 163 shown in FIG. 4B being in a stripe configuration, as shown in FIG. 4c, the orthographic projection of the first flow-guide lines 163 in this embodiment onto the second regions 10B is in a patterned pattern, i.e., a block configuration covering a plurality of connecting lines 131. At this time, the initial drain 161 extends in the first direction D1, and the first drain 163 covers a combined orthographic projection of the connecting lines 131 arranged in the extending direction of the second zone 10B in the second zone 10B. With this structure, the number of the first conduction leads 163 is less than the number of the connection wires 131.

In this configuration, as shown in fig. 4c, the first drain wires 163 are arranged over the entire surface in the extending direction of the second region 10B, the second drain wires 164 are connected to different ground potentials 151, and one first drain wire 163 corresponds to each of the second drain wires 164. In this embodiment, the patterned structure of fig. 4c under this structure is not limited to the rectangle shown in fig. 4c, and the first drainage lines 163 extend along the extending direction of the first boundary 10B1, and a plurality of connection lines covering this direction are taken as a design criterion, and the connection lines 131 at the covered positions are protected by the patterned first drainage lines 163, so as to avoid the problem that a large amount of static electricity generated during the cutting process forms a breakdown damage to the internal wirings of the display area AA through the connection lines 131.

Further, the present embodiment is designed with respect to the relative positions of the second conduction strands 164 and the cutting zone 14, considering that if the position of the second conduction strands 164 is improperly set when cutting is performed at the position of the cutting zone 14, there may be a problem in that the second conduction strands 164 are cut by the cutting zone 14, resulting in a failure to form a conduction path.

In an alternative embodiment, the boundary is an extension line in the first direction D1 where the first and

second drainage threads

163 and 164 are connected,

when the cutting zone 14 and the second drainage wire 164 are located on the same side, the orthographic projection of the cutting zone 14 on the first substrate 10 is a patterned figure, and the cutting length of the cutting zone 14 is less than the extension of the second zone 10B in the first direction D1;

when the cutting region 14 and the second drainage wire 164 are located on opposite sides, the cutting length of the cutting region 14 is less than or equal to the extension of the second region 10B in the first direction D1.

Specifically, as illustrated in FIG. 4c and FIG. 4d,

in one specific example, as shown in fig. 4d, one second drainage thread 164 and a plurality of first drainage threads 163 form a plurality of boundary positions X3, X4 and X5, and thus, the positional relationship between the cutting region 14 and the second drainage threads 163 is determined with the extension thread corresponding to the boundary position X3 closest to the cutting region 14 as a boundary line.

As shown in FIG. 4d, the cut region 14 and the second drain wire 164 are on the same side of the dividing line, i.e., both the second drain wire 164 and the cut region 14 are above the dividing line.

With this structure, in order to avoid the damage to the second drainage wire 164 during the cutting process, which results in the damage to the charge drainage structure 16, in this embodiment, the orthogonal projection of the cutting region 14 in the second region 10B is designed as a patterned pattern, and the cutting length of the cutting region 14 is less than the extension length of the second region 10B, i.e. the cutting region 14 does not cut the second drainage wire 164 on the same side as the cutting region. With this arrangement, in the embodiment of the present invention, only the connecting wire 131 near the test terminal 121 is subjected to laser processing, and the line connection from the test terminal 121 to the in-plane display area AA is cut off, and the glass of the second area 10B is not cut off, so that the cutting cost can be reduced.

In another example, as shown in fig. 4c, the first conduction lines 163 are one, or one, sheet-shaped region, one first conduction line 163 corresponds to a plurality of second conduction lines 164, and the junction Y between the second conduction lines 164 and the first conduction lines 163 is a strip-shaped boundary line extending in the first direction D1, with the strip-shaped boundary line being the boundary line.

As shown in fig. 4c, the cut region 14 and the second drainage line 164 are located on opposite sides of the dividing line, i.e., the cut region 14 is above the dividing line and the second drainage line is below the dividing line YY, using the dividing line at the point of intersection Y as the dividing line. In this structure, the cutting length of the cutting region 14 is equal to or less than the extension length of the second region 10B.

With this structure, the cutting area 14 according to the embodiment of the present invention adopts a partial cutting manner as the structure shown in fig. 4d, that is, only the connection line 131 near the test terminal 121 is subjected to laser processing to cut off the line connection from the test terminal 121 to the in-plane display area AA, and the glass of the second area 10B is not cut off, so that the cutting cost can be reduced; it is also possible to cut the second area 10B over the entire cut area 14 for the purpose of reducing the size of the frame.

In an alternative embodiment, as shown in fig. 4B to 4d, a distance between the start drain 161 and the test terminal 121 near the first boundary 10B1 is designed as a first distance d1, and in a specific example, the first distance d1 is a fifth distance d5 between two adjacent test terminals 121 which is greater than or equal to two times, that is, d1 is greater than or equal to 2 × d5, so as to ensure that insulation between the start drain 161 and the test terminal 121 can be achieved even if there is a metal layer deposition error, and normal conduction of the test line and the charge drain line is ensured. In one specific example, the first distance minimum is 500um.

The distance between the side of the cut region 14 close to the second boundary 10B2 (the lower edge of the cut region 14) and the side of the test terminal 121 close to the second boundary 10B2 (the lower edge of the test terminal) is designed to be a second distance d2, and the second distance d2 is greater than the first distance d1. With this arrangement, in a planar state, the cutting region 14 overlaps the first conduction wire 163, and when a large amount of electric charge is formed at the cutting position in the cutting process, a path can be formed with the conduction wire at the overlapping position, and charge transfer can be achieved.

In the embodiment of the present invention, it is not designed whether the upper edge of the cutting region 14, i.e. the boundary close to the side of the test terminal 121 overlaps the start draining part 161 in the orthographic projection, but it is emphasized that the lower edge of the cutting region 14 is designed, and the lower edge of the cutting region 14 and the start draining part 161 just overlap under the limit distance, which also can ensure the conduction of the charge draining circuit, but considering the processing technology, the second distance d2 from the lower edge to the test terminal 121 is set to be greater than the first distance d1 from the start draining part 161 to the test terminal 121, so as to ensure that the charge draining structure 16 and the cutting region 14 can form a path during the cutting technology.

Those skilled in the art can select different designs of the cutting region 14 according to practical applications, and will not be described herein.

In an alternative embodiment, fig. 5 showsbase:Sub>A schematic view ofbase:Sub>A test terminal structure atbase:Sub>A position ofbase:Sub>A cross sectionbase:Sub>A-base:Sub>A', and the test terminal 121 includes:

a first test metal layer 122 on the substrate 11;

at least one first insulating layer 123 on a side of the first test metal layer 122 remote from the substrate 11; and

a second test metal layer 124 on a side of the first insulating layer 123 remote from the first test metal layer 122,

the first insulating layer 123 is provided with a first via hole 123A, and the first test metal layer 122 and the second test metal layer 124 are electrically connected through the first via hole 123A.

In the embodiment of the present invention, the test terminal 121 is a two-metal-layer structure, the second test metal layer 124 is located at the top, i.e., away from the substrate 11, the test signal can be directly loaded to the second test metal layer 124, and the second test metal layer 124 transmits the signal to the first test metal layer 122 below the second test metal layer 124 through the first via 123A, so as to implement access of the test signal.

In the embodiment of the present invention, the connecting lines 131 of the connecting line region 13 extend from the second region 10B to the display region AA, and overlap with the cutting region 14 and the ground potential region 15, so in the trace design, the metal layers of the connecting lines 131 at different positions need to be designed or avoided to ensure circuit arrangement.

In an alternative embodiment, as shown in fig. 6a and 6b, the connection line 131 comprises:

a first connection line metal layer 132 on the substrate 11; and

a second connection line metal layer 133 provided to be insulated from the first connection line metal layer 132;

the first insulating layer 123 includes:

a first sub-insulating layer 1231 located on a side of the first connection line metal layer 132 away from the substrate 11, where the first sub-insulating layer 1231 is provided with a second via hole 1231A; and

a second sub-insulating layer 1232 on a side of the second link metal layer 133 away from the substrate 11;

at the non-overlapping position of the connection line 131 and the cutting region 14, and the connection line 131 on the array substrate 10, the connection line 131 at least includes one of the first connection line metal layer 132 or the second connection line metal layer 133, or the first connection line metal layer 132 and the second connection line metal layer 133 form an electrical connection through the second via 1231A,

the first connection line metal layer 132 is connected to the first test metal layer 122 or the second test metal layer 124, and/or the second connection line metal layer 133 is connected to the second connection line metal layer 133;

at the position where the ground potential 15 and the connecting line 131 overlap in the orthographic projection of the array substrate 10, the metal layer of the connecting line 131 is insulated from the metal layer of the ground potential 151 and from the ground line 152.

As shown in fig. 5, the first via hole 123A penetrates the first and second

sub-insulating layers

1231 and 1232, and the second via hole 1231A penetrates only the first sub-insulating layer 1231.

In a specific example, as shown in fig. 6a, on the orthographic projection of the second region 10B, at the non-projection overlapping position of the connecting line 131 and the cutting region 14, i.e., as shown in the layer structure of the cross section D-D' in fig. 4B, one metal layer may be used as the connecting line 131 for the connecting line 131 at the test terminal A1 and one metal layer may be used as the connecting line 131 for the connecting line 131 at the test terminal A2, for example, the connecting line 131 connecting the test terminal A1 on the left side shown in fig. 6a is the first connecting line metal layer 132, and the connecting line 131 connecting the test terminal A2 on the right side shown in fig. 6B is the second connecting line metal layer 133. In another specific example, as shown in fig. 6b, the connection line 131 at the non-overlapping position may also be formed by the first connection line metal layer 132 and the second connection line metal layer 133, that is, the line change connection is realized through the second via 1231A opened in the first sub-insulating layer 1231.

In an alternative embodiment, fig. 7 shows a layer structure arrangement of the ground potential 151 at the location of section C-C 'and the ground line 152 at the location of section E-E' in fig. 4b, by way of example, the ground potential 151 comprises:

a first ground metal layer 153 on the substrate 11;

a second ground metal layer 154 on a side of the second sub-insulating layer 1232 away from the substrate 11,

the first sub-insulating layer 1231 and the second sub-insulating layer 1232 are opened with a third via hole 1232A,

the first ground metal layer 153 and the second ground metal layer 154 are electrically connected through the third via 1232A, and a ground signal is accessed.

Based on the above structure, the first electrode 1511 and the second electrode 1512 are both formed by the first ground metal layer 153 and the second ground metal layer 154, and are a two-metal layer structure, the second ground metal layer 154 is located at the top, i.e. the side far away from the substrate 11, the ground signal can be directly loaded to the second ground metal layer 154, the second ground metal layer 154 transmits the signal to the first ground metal layer 153 below the second ground metal layer 154 through the third via 1232A, so as to implement access of the ground signal, and through the provision of the two-metal layer, the corrosion resistance of the ground potential 151 can be improved.

As shown in fig. 4b to 4d, the adjacent first electrodes 1511 and the second electrodes 1512, and the adjacent second electrodes 1512 are further connected by the ground line 152, the metal layer forming the ground line 152 may be the first ground metal layer 153, may also be the second ground metal layer 154, and may also be the first ground metal layer 153 and the second ground metal layer 154 to implement line-changing grounding through the third via 1232A, and the specific structure of the ground line 152 may be set by those skilled in the art according to practical applications.

Further, in an alternative embodiment, as shown in fig. 4B and 4d, at the position of the cross section F-F', there is an overlapping position where the ground potential 151 and the orthogonal projection of the connection line 131 in the second region 10B exist, and at the overlapping position, the metal layer of the connection line 131 and the metal layer of the ground potential 151 need to be insulated to ensure the line arrangement. Illustratively, the layer structure at this location is shown in fig. 8a and 8 b.

In a specific example, as shown in fig. 8a, the layer structure at the orthographic overlap position F-F' of the ground potential 151 and the connection line 131 in the second region 10B is designed to: the substrate 11, the first connection line metal layer 132 on the substrate 11, the first sub-insulating layer 1231 on the first connection line metal layer 132, the second sub-insulating layer 1232 on the first sub-insulating layer 1231, and the second ground metal layer 154 on the second sub-insulating layer 1232, thereby implementing a structural design in which the metal layer of the connection line 131 is located below and the metal layer of the ground line 152 is located above. That is, the structure shown in fig. 8a is formed at a position overlapping the second ground metal layer 154 in addition to the layer structure of the connection line 131 shown on the left side of fig. 6 a.

Accordingly, based on the structural design of the connecting wire metal layers of the different embodiments in fig. 6a to 6b, it can be understood that the structural design of the connecting wire 131 and the grounding wire 152 at the overlapping position can be formed based on the structure of fig. 6a to 6b, for example, the structural scheme of forming the second grounding metal layer 154 on the second sub-insulation layer 1232.

In another specific example, unlike the scheme of fig. 8a in which the second ground metal layer 154 is located at the top, as shown in fig. 8b, the design at the overlapping position may be performed by using the first ground metal layer 153 located on the substrate 11, and the connection line 131 is designed by using the second connection metal layer for implementing the insulation arrangement, so as to implement the overlapping structure design of the first ground metal layer 153 located on the substrate 11, the first sub-insulation layer 1231 located on the first ground metal layer 153, the second connection line metal layer 133 located on the first sub-insulation layer 1231, and the second sub-insulation layer 1232 located on the second connection line metal layer 123133, as shown in fig. 8b, thereby implementing the structure design of the connection line metal above and the ground metal layer below.

Those skilled in the art can select different routing arrangements according to practical applications, so as to implement the structural design at the overlapping position of the embodiment of the present invention, so as to ensure the wiring design of the ground line 152 and the connecting line 131.

On the basis of the layer structure design of the connection line 131, and the structure design of the overlapping position of the ground potential 151 and the connection line 131 in the foregoing embodiments, the layer structure of the charge-draining structure 16 in the embodiments of the present invention is further designed,

in an alternative embodiment, as shown in fig. 9a to 9c, the charge draining structure 16 includes a draining conductive layer 165 located on a side of the metal layer of the connection line 131 away from the substrate 11, the draining conductive layer 165 is insulated from the metal layer of the connection line 131, and the first ground metal layer 153 or the second ground metal layer 154 corresponding to the terminating draining part 162 is connected to the draining conductive layer 165.

At the B-B 'position shown in fig. 4B and 4d, as shown in fig. 9a, the connection line 131 and the charge draining structure 16 form an overlap, and thus the film layer at the B-B' position includes the metal layer draining the conductive layer 165 and the connection line 131. Based on the foregoing discussion, as shown in fig. 6a and 6b, there are different designs of the metal layers of the connection line 131, and therefore, there are also different layer structure schemes of the layer structure at the overlapping position of the connection line 131 and the charge draining structure 16, as shown in fig. 9a and 9 b.

In a specific example, fig. 9a is a structural design of the drain conductive layer 165 formed based on the connecting line metal layer shown in fig. 6a, the connecting line 131 on the left side of fig. 9a is composed of the first connecting line metal layer 132 and is insulated from the drain conductive layer 165 by the first sub-insulating layer 1231 and the second sub-insulating layer 1232, and the connecting line 131 on the right side of fig. 9b is composed of the second connecting line metal layer 133 and is insulated from the drain conductive layer 165 by the second sub-insulating layer 1232.

In a specific example, fig. 9b is a structural design of the drain conductive layer 165 formed based on the connecting line metal layer shown in fig. 6b, and as shown in fig. 9b, the connecting line metal layer is electrically connected by the first connecting line metal layer 132 and the second connecting line metal layer 133 through the second via 1231A, and is insulated from the drain conductive layer 165 by the second sub-insulating layer 1232.

In another specific example, fig. 9c is a schematic diagram of the layer structure of the patterned drainage conductive layer 165 on the right side shown in fig. 4c at the G-G 'cross-sectional position of fig. 4c, and as shown at the G-G' position on the right side of fig. 4c, the first drainage line 163 is a patterned sheet-like structure, and at this time, the drainage conductive layer 165 corresponding to the first drainage line 163 is a continuous structure formed on the second sub-insulating layer 1232, that is, as shown in fig. 9c, the layer structure of the embodiment of the present invention is: the liquid crystal display device includes a substrate 11, a first connection line metal layer 132 on the substrate 11, a first sub-insulating layer 1231 on the first connection line metal layer 132, a second sub-insulating layer 1232 on the first sub-insulating layer 1231, and a draining conductive layer 165 on the second sub-insulating layer 1232, wherein an orthographic projection of the draining conductive layer 165 on the substrate 11 covers an orthographic projection of at least one first connection line metal layer 132 on the substrate 11.

Therefore, those skilled in the art can implement the structural arrangement of the charge draining structure 16 and the connecting line region 13 at the overlapping position in different design schemes, which will not be described in detail herein.

In the embodiment of the present invention, at the connection position of the termination drain 162 and the first electrode 1511, the first ground metal layer 153 or the second ground metal layer 154 is connected to the drain conductive layer 165, so as to implement the grounding of the termination drain 162, for example, the termination drain 162 in fig. 4d is connected to the metal layer of the first electrode 1511 (VM 1) to form a grounding, and for example, the termination drain 162 on the right side in fig. 4c is connected to the metal layer of the second electrode 1512 (VM 4) to form a grounding.

In an alternative embodiment, the first test metal layer 122, the first connection line metal layer 132 and the first ground metal layer 153 are disposed in the same layer, and the second test metal layer 124, the second ground metal layer 154 and the current guiding conductive layer 165 are disposed in the same layer, so as to improve the manufacturing efficiency on the basis of ensuring the line layout.

Furthermore, in the embodiment of the present invention, each metal layer in the second region 10B may be fabricated by the same process as the thin film driving transistor 17 in the display region AA, so as to further improve the fabrication efficiency.

In a specific example, the thin film transistor 17 includes a gate metal layer 171 formed on the substrate 11, a gate insulating layer 172 on the gate metal layer 171, an active layer 173 on the gate insulating layer 172, a source drain electrode layer 174 on the gate insulating layer 172, a source electrode 176S and a drain electrode 176D of the source drain electrode layer 174 respectively on both sides of the active layer 173, and a second insulating layer 175 covering the active layer 173 and the source drain electrode layer 174, wherein the second insulating layer 175 is provided with a fourth via 175A and exposes a portion of the source electrode 176S or the drain electrode 176D, and a pixel electrode 176 formed on the fourth via 175A and connected to the exposed portion of the source electrode 176S or the drain electrode 176D.

Based on the structural design of the thin film driving transistor 17, the first test metal layer 122, the first connection line metal layer 132, and the first ground metal layer 153 may be disposed in the same layer as the gate metal layer 171, the first sub-insulating layer 1231 is disposed in the same layer as the gate insulating layer 172, the source/drain electrode layer 174 is disposed in the same layer as the second connection line metal layer 133, the second sub-insulating layer 1232 is disposed in the same layer as the second insulating layer 175, and the second test metal layer 124, the second ground metal layer 154, the drainage conductive layer 165, and the pixel electrode 176 are disposed in the same layer, so that the second region 10B and the display region AA are formed in the same fabrication process, thereby improving the fabrication efficiency.

The structures of the second region 10B, the ground potential 151, the connection line 131, the charge-draining structure 16, and the display region AA will now be described with specific examples:

first, a metal material is deposited on the array substrate 11 and then patterned by exposure and etching processes, so as to form the gate metal layer 171 located in the display area AA, the first test metal layer 122, the first connection line metal layer 132, and the first ground metal layer 153 located in the second area 10B. In one specific example, the first connection wire metal layer 132 can function as the ground wire 152 connecting the two first electrodes 1511, the two second electrodes 1512, the first electrode 1511, and the second electrode 1512. It should be noted that other traces of the second area 10B may also be formed in this step, but are not related to the solution of the embodiment of the present invention, and are not described herein again.

Next, a first sub-insulating layer 1231 (gate insulating layer 172) is deposited on the metal layer, a semiconductor active layer 173 is formed on the gate insulating layer 172 in the display area AA, and the active layer 173 is exposed and etched accordingly to form a TFT channel in the periphery of the pixel area and/or the array display panel. The first sub-insulating layer 1231 is opened, for example, as shown in fig. 6b, a second via 1321A is formed.

Then, a metal material is deposited and patterning is completed, thereby forming the source and drain electrode layers 174 of the display area AA and the second connection line metal layer 133 of the second area 10B. It should be noted that, other traces in the second area 10B and the display area AA can be formed in this step, but are not related to the solution of the embodiment of the present invention and are not described herein again.

After the above steps are completed, the second sub-insulating layer 1232 of the second area 10B (the second insulating layer 175 of the display area AA) is deposited, and then the corresponding exposure and etching are performed to form the through holes/vias required for the pixel area and the second area 10B. Such as the first via 123A shown in fig. 5, the third via 1232A shown in fig. 7, and the fourth via 175A shown in fig. 10. In a specific example, the depth of the first via 123A is greater than that of the fourth via 175A, the depth of the third via 1232A is greater than that of the fourth via 175A, and an external signal may be connected to a metal layer on a side close to the substrate 11 or a metal layer on a side away from the substrate 11 by a via design so as to provide a panel driving signal.

Illustratively, as shown in fig. 5, the transmission of the test signal is realized through the first via 123A, exemplarily, as shown in fig. 6b, the transmission of the test signal to the in-plane routing is realized through the second via 1231A, exemplarily, as shown in fig. 7, the transmission of the ground signal is realized through the third via 1232A, and exemplarily, as shown in fig. 10, the source driving signal is output to the pixel electrode 176 through the fourth via 175A. In an alternative embodiment, the number of the test terminals 121 corresponds to the number of the first vias 123A, ensuring a double-layered structure, and ensuring independent transmission of the test signals.

It is worth noting that the number of the test terminals 121 coincides with the number of the first vias 123A. The number and positions of the other vias such as the second via 1231A or the third via 1232A may be designed according to practical applications, for example, according to the routing design, the wire-changing design of the connecting wire 131, and the wire-changing design of the grounding wire 152. The distance between the adjacent through holes has no special requirement, and the adjacent through holes are preferably uniformly arranged.

After the second sub-insulating layer 1232 is formed, the metal material is deposited and patterned to form the second test metal layer 124, the second ground metal layer 154 and the current guiding conductive layer 165 in the non-display area AA. A first distance d1, illustratively 500um, exists between the drainage conductive layer 165 corresponding to the initial drainage portion 161 and the metal layer of the test terminal 121 on the plane, so as to avoid signal interference caused by too close distance between an external signal and the conductive layer after the external signal is connected to the PAD; the drain conductive layer 165 corresponding to the termination drain portion 162 is connected to the first ground metal layer 153 or the second ground metal layer 154 through a third via 1232A, thereby achieving grounding.

It should be noted that the conductive layer pattern design is not particularly required, and may be a stripe structure, such as the structure of a plurality of initial drains 161 shown in fig. 4b and 4D, or the number of initial drains 161 is less than the number of test terminals 121, such as the drain conductive layer 165 shown in fig. 4c is a patterned design, and the initial drains 161 are stripe-shaped along the first direction D1. In any pattern, the start drain 161 is spaced apart from the test terminal 121 by a first distance, the end drain 162 is connected to the ground potential 151, and the charge draining structure 16 is not connected to the pixel electrode 176 or other electrodes having non-Vcom signals.

Through the above steps, the test terminal 121, the first electrode 1511, the second electrode 1512, and the pixel electrode 176 in the display area AA of the dual metal structure are formed, and it should be noted that the test terminal 121 according to the embodiment of the present invention further includes a TFT test terminal for detecting the thin film driving transistor 17, and can be fabricated by the same process as the test terminal 12. Further, the first electrode 1511, the second electrode 1512, and the test terminal 121 are independent shapes, such as a rectangle, a convex shape, a cross shape, and the like, and are not described herein again.

Further, as shown in fig. 3, the color filter substrate 20 includes a second substrate 11, and a common electrode 21 located on a side of the second substrate 11 facing the array substrate 10. Based on the charge draining structure 16 of the above embodiment of the present invention, when static electricity is conducted to the in-plane line of the display area AA through the cutting area 14, the charge draining structure 16, in which the start draining part 161 is located near the test terminal 121 and the stop draining part 162 is connected to the ground potential area 15, of the embodiment of the present invention, can preferentially conduct the static electricity to the ground through the charge draining structure 16, so as to achieve static electricity discharge, and greatly reduce the tendency of the static electricity to be longitudinally transferred on the film layer of the test terminal 121 and the film layer of the connection line 131 connected to the test terminal 121, thereby avoiding the problem of line damage caused by damaging the metal layer of the lead wire, or bad display caused by damage of static electricity reflow to the internal elements of the display area AA, such as the timing controller.

Another embodiment of the present invention provides a method for manufacturing a display panel according to the above embodiment of the present invention, the method including:

forming the first substrate on the substrate includes:

forming the charge-directing structure in the second region, the charge-directing structure comprising: the orthographic projection of the initial drainage part on the first substrate is at least partially overlapped with the orthographic projection of the cutting area on the first substrate; and a termination drain connected to either the ground potential or the ground line.

It should be noted that the process and principle of the manufacturing method can be referred to the foregoing embodiments, and are not repeated herein.

Another embodiment of the present invention provides a display device, including the display panel according to the above embodiment of the present invention. The display device may be any product or component with a touch sensing function, such as electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a vehicle-mounted display device, and the like, which is not limited in this embodiment.

Another embodiment of the present invention provides a method for manufacturing a display device, including:

the test signal is input to the display panel through the test terminal 121 for electrical detection, and the test signal is transmitted to the line of the display area AA through the test terminal 121 and the connection line 131, so that electrical line detection of the display area AA is realized.

The cutting region 14 is used as a cutting position to cut the display panel which meets the detection result, the charge drainage structure 16 forms a passage in the cutting process, and based on the display panel provided with the charge drainage structure 16, electrostatic charges generated in the cutting process can be transferred into the passage through the initial drainage part 161 preferentially, and then the charges are transmitted to a grounding potential part connected with the termination drainage part 162 through the first drainage line 163 and the second drainage line 164, so that electrostatic discharge is realized.

In the description of the present invention, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations and modifications can be made on the basis of the above description, and all embodiments cannot be exhaustive, and all obvious variations and modifications belonging to the technical scheme of the present invention are within the protection scope of the present invention.

Claims

1. A display panel, comprising:

the first region includes a display area and a second region,

the orthographic projection of the cutting area on the first substrate falls in the orthographic projection of the connecting line on the first substrate,

the charge-draining structure includes:

and a terminal drain connected to either the ground potential or the ground line.

2. The display panel according to claim 1,

the first region includes a first boundary on a side away from the second region, an

the ground potential comprises:

a second electrode positioned on a side close to the second boundary and arranged along the first direction,

3. The display panel according to claim 2,

the test terminal is located on a side near the first boundary,

the charge-draining structure further comprises:

a first drainage wire adjacent to the initial drainage portion; and

a second drainage wire adjacent to the termination drainage portion,

the first drainage thread is connected with the second drainage thread,

4. The display panel according to claim 1,

the distance between the starting drainage part and the side boundary, close to the color film substrate, of the test terminal is designed to be a first distance, the distance between the side boundary, close to the color film substrate, of the cutting area and the side boundary, close to the color film substrate, of the test terminal is designed to be a second distance, and the second distance is larger than the first distance.

5. The display panel according to claim 3,

the end part of the first drainage wire is the initial drainage part, the first drainage wires are multiple, and in a second direction perpendicular to the first direction, the orthographic projection of each first drainage wire on the orthographic projection of the first substrate covers part of the orthographic projection of the connecting wire.

6. The display panel according to claim 3,

the end part of the first drainage wire is the initial drainage part, the orthographic projection of the first drainage wire on the first substrate is a patterned graph and extends along the first direction, and a plurality of connecting wires arranged along the first direction are covered.

7. The display panel according to claim 3,

the extension line extending in the first direction where the connecting positions of the first and second drainage threads are located is used as a dividing line,

when the cutting area and the second drainage wire are positioned on different sides, the cutting length of the cutting area is less than or equal to the extending length of the wire walking area.

8. The display panel according to claim 1, wherein the test terminal comprises:

a first test metal layer on the substrate;

a second test metal layer on a side of the first insulating layer remote from the first test metal layer,

9. The display panel according to claim 8, wherein the connection line comprises:

a first connection line metal layer on the substrate; and

the first insulating layer includes:

10. The display panel according to claim 9,

the ground potential comprises:

a first ground metal layer on the substrate;

11. The display panel according to claim 10, wherein the charge draining structure comprises a draining conductive layer on a side of the metal layer of the connection line away from the substrate, the draining conductive layer being disposed insulated from the metal layer of the connection line,

12. The display panel according to claim 11,

the first test metal layer, the first connection line metal layer and the first ground metal layer are arranged on the same layer;

13. A method of manufacturing the display panel according to any one of claims 1 to 12, the method comprising:

forming the first substrate on the substrate includes:

forming a ground line connecting the plurality of ground potentials and a connection line connecting each test terminal and a drive line in a display region in the second region, wherein an orthographic projection of the cutting region on the first substrate falls within an orthographic projection of the connection line on the first substrate,

14. A display device comprising the display panel according to any one of 1 to 12.

15. A method of manufacturing a display device according to claim 14, the method comprising:

and cutting the display panel which accords with the detection result by taking the cutting area as a cutting position, wherein in the cutting process, the charge drainage structure forms a passage.