CN115561940A - Array substrate and display device - Google Patents

Abstract

An array substrate and a display device. The array substrate includes data lines and signal lines, each sub-pixel unit includes a pixel electrode, the distance between the pixel electrode and the data line is a first distance D1, the distance between the pixel electrode and the signal line is a second distance D2, and the pixel electrode The length of the side close to the data line is L1, and the length of the side close to the signal line is L2; each sub-pixel unit also includes a driving transistor, the source of the driving transistor is connected to one of the data line and the signal line, and the drain is connected to the pixel electrode; The distance between the drain and the source of the driving transistor is a third distance D3, the distance between the drain and the other of the data line and the signal line is a fourth distance D4, the dimension of the source in the second direction is L3, and the drain is The size in the second direction is L4, and the ratio range of (E1*L1/D1+E2*L3/D3) to (E1*L2/D2+E2*L4/D4) is 0.9‑1.1, which can effectively avoid gray Poor order crosstalk.

Description

Array substrate and display device

technical field

Embodiments of the present disclosure relate to an array substrate and a display device.

Background technique

With the continuous development of technology, display panels are widely used in various electronic devices, such as smart phones, tablet computers, notebook computers, car navigation and so on. Common display panels can be classified into liquid crystal display panels (Liquid Crystal Display, LCD) and organic light emitting diode display panels (Organic Light Emitting Diode, OLED). Liquid crystal display panels have the advantages of fast response, high resolution, high integration, low power consumption, and low cost, and thus occupy a relatively large market share.

Generally, a liquid crystal display panel usually includes an array substrate, an opposite substrate, a liquid crystal layer, a first polarizer and a second polarizer; the array substrate and the opposite substrate are arranged oppositely, the liquid crystal layer is located between the array substrate and the opposite substrate, The polarizer is located on a side of the array substrate away from the opposite substrate, and the second polarizer is located on a side of the opposite substrate away from the array substrate. Thin film transistors (TFT) and pixel electrodes are arranged on the array substrate. The liquid crystal display panel can provide driving voltage to the pixel electrodes through the thin film transistors to generate an electric field. The electric field can change the molecular arrangement of the liquid crystal molecules in the liquid crystal layer. The first polarizer and the second polarizer on both sides of the panel can form a liquid crystal light valve to realize the display function. In addition, in cooperation with the color filter layer formed on the array substrate or the opposite substrate, the liquid crystal display panel can further realize color display.

Contents of the invention

Embodiments of the present disclosure provide an array substrate and a display device. The array substrate makes the pixel electrode in each sub-pixel unit roughly equal to the parasitic capacitance generated by other conductive structures on the left and right sides, so as to effectively avoid grayscale V-Crosstalk (crosstalk) defects and improve display quality.

At least one embodiment of the present disclosure provides an array substrate, which includes a base substrate; a plurality of sub-pixel units are located on the base substrate and arranged in an array along a first direction and a second direction, so as to be formed in the first direction Extended sub-pixel rows and sub-pixel columns extending in the second direction; gate lines, located on the substrate, extending along the first direction and configured to provide gate signals to the sub-pixel rows; The data line is located on the base substrate and extends along the second direction; and the signal line is located on the base substrate and extends along the second direction; the data line and the signal line are respectively located in the sub-pixel Listed on both sides in the first direction, each of the sub-pixel units includes a pixel electrode, the distance between the pixel electrode and the data line is a first distance D1, and the pixel electrode and the signal line The distance between them is the second distance D2, the side length of the pixel electrode close to the data line is S1, the side length of the pixel electrode close to the signal line is L2, and each of the sub-pixel units also includes a driving transistor , the driving transistor includes a source and a drain, the source is connected to one of the data line and the signal line, the drain is connected to the pixel electrode, and the drain is connected to the source The distance between the poles in the first direction is a third distance D3, the distance between the drain and the other of the data line and the signal line is a fourth distance D4, and the source is in the first direction. The size in the two directions is L3, the size of the drain in the second direction is L4, (E1*L1/D1+E2*L3/D3) and (E1*L2/D2+E2*L4/D4 ) ratio range is 0.9-1.1, E1 is the dielectric constant of the film layer between the pixel electrode and the data line or the signal line, E2 is the signal line and the source or the drain The dielectric constant of the film layer between the electrodes.

For example, in an array substrate provided in an embodiment of the present disclosure, the ratio of (E1*L1/D1+E2*L3/D3) to (E1*L2/D2+E2*L4/D4) ranges from 0.95 to 1.05 .

For example, in an array substrate provided by an embodiment of the present disclosure, (E1*L1/D1+E2*L3/D3)=(E1*L2/D2+E2*L4/D4).

For example, in an array substrate provided in an embodiment of the present disclosure, the data lines and the signal lines are both configured to transmit data signals, and the sources of some of the sub-pixel units in the sub-pixel column The source electrodes of another part of the sub-pixel units in the sub-pixel column are connected to the signal lines.

For example, in an array substrate provided in an embodiment of the present disclosure, the data lines located on one side of the j-th sub-pixel column in the first direction are arranged toward the j-th sub-pixel The column provides data signals, and the signal line located on the other side of the j-th sub-pixel column in the first direction is configured to provide data signals to the j+1-th sub-pixel column, the j is a positive integer greater than or equal to 1.

For example, in an array substrate provided in an embodiment of the present disclosure, the signal line located on one side of the j-th sub-pixel column in the first direction is connected to the signal line located on the j+1-th sub-pixel column. The data lines on one side of the pixel column in the first direction are configured to be connected to the same signal terminal.

For example, in an array substrate provided by an embodiment of the present disclosure, the signal line is configured to transmit a common electrode signal.

For example, in an array substrate provided in an embodiment of the present disclosure, the connection portion between the pixel electrode and the drain electrode is located on an area bisector of the pixel electrode in the first direction.

For example, in an array substrate provided in an embodiment of the present disclosure, the side length L1 of the pixel electrode close to the data line is equal to the side length L2 of the pixel electrode close to the signal line, and the first distance D1 is equal to the second distance D2.

For example, in an array substrate provided in an embodiment of the present disclosure, the dimension L3 of the source electrode in the second direction is equal to the dimension L4 of the drain electrode in the second direction, and the dimension L3 of the drain electrode in the second direction is equal. The third distance D3 is equal to the fourth distance D4.

For example, in an array substrate provided in an embodiment of the present disclosure, each of the sub-pixel units includes a first region and a second region sequentially arranged along the second direction, and the pixel electrode is located in the first region , the driving transistor is located in the second region.

For example, in an array substrate provided in an embodiment of the present disclosure, the source electrode and the data line or the signal line connected to the source electrode are relatively spaced apart, and the array substrate further includes a conductive connection block , the source is connected to the data line or the signal line connected to the source through the conductive connection block, and the source is connected to the data line or the signal line connected to the source The distance between the lines is a fifth distance D5 equal to said fourth distance D4.

For example, in an array substrate provided in an embodiment of the present disclosure, the width of the sub-pixel unit in the first direction is Wpixel, the driving transistor includes an active layer, and the channel of the active layer The length of the region in the first direction is L, the length of the channel region of the active layer in the second direction is W, and the width of the source electrode in the first direction is Wsource, The width of the drain electrode in the first direction is Wdrain, the width of the data line and the signal line in the first direction is Wdata, and the channel region of the active layer is in the first direction. The length L in one direction satisfies the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wsource-Wdrain)/3.

For example, in an array substrate provided in an embodiment of the present disclosure, the length L of the channel region of the active layer in the first direction satisfies the following formula:

Wsource+Wdrain<L<(Wpixel-2Wdata-Wsource-Wdrain)/4.

For example, in an array substrate provided in an embodiment of the present disclosure, the source is a part of the data line or the signal line connected to the source.

For example, in an array substrate provided in an embodiment of the present disclosure, the width of the sub-pixel unit in the first direction is Wpixel, the driving transistor includes an active layer, and the channel of the active layer The length of the region in the first direction is L, the length of the channel region of the active layer in the second direction is W, and the width of the source electrode in the first direction is Wsource, The width of the drain electrode in the first direction is Wdrain, the width of the data line and the signal line in the first direction is Wdata, and the channel region of the active layer is in the first direction. The length L in one direction satisfies the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wdrain)/2.

For example, in an array substrate provided in an embodiment of the present disclosure, the orthographic projection of the pixel electrode on the base substrate is axisymmetric with respect to an area bisector of the pixel electrode in the first direction.

For example, in an array substrate provided in an embodiment of the present disclosure, the pixel electrode includes a first domain, a second domain, a third domain, and a fourth domain, and the first domain and the second domain are related to the The area bisector of the pixel electrode in the first direction is axisymmetric, and the third domain and the fourth domain are axisymmetric with respect to the area bisector of the pixel electrode in the first direction, so The first domain and the third domain are sequentially arranged along the second direction, and the second domain and the fourth domain are sequentially arranged along the second direction.

For example, in an array substrate provided in an embodiment of the present disclosure, the pixel electrode includes a middle portion extending along the second direction and located between the first domain and the second domain, the Between the third domain and the fourth domain, the drain is connected to the middle portion of the pixel electrode.

For example, in an array substrate provided in an embodiment of the present disclosure, the pixel electrode includes: a plurality of first slits arranged at intervals, located in the first domain; a plurality of second slits arranged at intervals, located in The second domain; a plurality of third slits arranged at intervals, located in the third domain; and a plurality of fourth slits arranged at intervals, located in the fourth domain.

For example, in an array substrate provided in an embodiment of the present disclosure, the plurality of sub-pixel units form n sub-pixel rows arranged in the second direction, the array substrate includes n gate lines, Set in one-to-one correspondence with the n sub-pixel rows, the kth gate line and the k+1th gate line form a (k+1)/2th gate line group, and the array substrate further includes a A vertical gate line and a second vertical gate line, respectively located on both sides of the plurality of sub-pixel units in the first direction, in the (k+1)/2th gate line group, the kth The first grid line and the k+1th grid line are connected through the first vertical grid line and the second vertical grid line, k can be an odd number greater than or equal to 1, n is a positive value greater than k integer.

For example, in an array substrate provided in an embodiment of the present disclosure, the first vertical gate lines and the second vertical gate lines are arranged on the same layer as the data lines.

For example, in an array substrate provided in an embodiment of the present disclosure, the first vertical gate line is connected to the k-th gate line through a first via connection structure, and the first vertical gate line is connected to the kth gate line through The second via hole connection structure is connected to the k+1th gate line, the second vertical gate line is connected to the kth gate line through the third via hole connection structure, and the second vertical gate line The line is connected to the k+1th gate line through the fourth via hole connection structure.

For example, in an array substrate provided in an embodiment of the present disclosure, the array substrate further includes at least one intermediate vertical gate line located between two adjacent sub-pixel columns, and the (k+1th )/2 grid line group, the kth grid line and the k+1th grid line are connected through the middle vertical grid line.

For example, in an array substrate provided in an embodiment of the present disclosure, the middle vertical gate line is arranged on the same layer as the gate line.

For example, an array substrate provided by an embodiment of the present disclosure further includes: a first common electrode line extending along the first direction; and a second common electrode line extending along the second direction, and each of the sub-pixels The unit includes a first area and a second area arranged in sequence along the second direction, the pixel electrode is located in the first area, the driving transistor is located in the second area, and the first common electrode line is located in the Between two adjacent sub-pixel units in the second direction, and between the first region and the second region of the same sub-pixel unit, the second common electrode line is located in the adjacent between the two sub-pixel columns.

For example, in an array substrate provided in an embodiment of the present disclosure, the first common electrode line is provided on the same layer as the gate line, and the first common electrode line includes at least one first notch and is located on the second For the first sub-common electrode lines on both sides of the gap, the middle vertical gate line passes through the first gap and is respectively spaced and insulated from the first sub-common electrode lines.

For example, in an array substrate provided in an embodiment of the present disclosure, the second common electrode lines include a gate layer common electrode line and a data line layer common electrode line, and the gate layer common electrode line is the same as the gate line. The common electrode line of the data line layer is arranged on the same layer as the data line, and the common electrode line of the gate layer is connected to the common electrode line of the data line layer through a fifth via connection structure.

For example, in an array substrate provided in an embodiment of the present disclosure, the two first common electrode lines are arranged on the kth gate line and the kth gate line in the (k+1)/2th gate line group. Between +1 grid lines, and respectively including the first gap, the middle vertical grid line passes through the two first gaps of the two first common electrode lines to form the k-th grid line The gate line is connected to the k+1th gate line.

For example, in an array substrate provided in an embodiment of the present disclosure, the width of the part where the second common electrode line is located in the first region is larger than the width of the part where the second common electrode line is located in the second region. width.

For example, in an array substrate provided in an embodiment of the present disclosure, the second common electrode line is located between the 1st sub-pixel column and the 1+1th sub-pixel column, and the second common electrode line The distance between the signal lines corresponding to the lth sub-pixel column is equal to the distance between the second common electrode line and the data line corresponding to the l+1th sub-pixel column, or, The distance between the second common electrode line and the data line corresponding to the lth sub-pixel column and the distance between the second common electrode line and the signal line corresponding to the l+1th sub-pixel column The distances are equal, and l is a positive integer greater than or equal to 1.

For example, in an array substrate provided in an embodiment of the present disclosure, each of the sub-pixel units includes a first region and a second region sequentially arranged along the second direction, and the pixel electrode is located in the first region , the driving transistor is located in the second region, and the distance between the part of the data line in the first region and the part of the signal line in the first region in the first direction is smaller than that of the data line in the first region The distance between the part of the second area and the part of the signal line in the second area in the first direction, the data line includes a first inclined connection part, and the data line is connected in the first direction. A part of the first area is connected to the part of the data line in the second area, and the signal line includes a second inclined connection part, connecting the part of the signal line in the first area to the part of the signal line in the second area. part of the second region.

For example, an array substrate provided by an embodiment of the present disclosure further includes: a plurality of gate lead-out lines, each of the gate lead-out lines is located between two adjacent sub-pixel columns, and each of the gate lead-out lines The lines include: a first gate lead-out line, arranged on the same layer as the data line, and configured to connect to a gate signal; a second gate lead-out line, arranged on the same layer as the gate line, and configured to be connected to a corresponding The gate lines are connected, and the first gate lead-out line and the second gate lead-out line are connected through a fifth via hole structure.

For example, in an array substrate provided in an embodiment of the present disclosure, the gate lead-out line is configured to be electrically connected to the (m+1)/2th gate line group, and the second gate lead-out line is connected to The mth grid lines are directly connected, m is an odd number greater than or equal to 1, the m-1th grid line includes a second gap, and the three first common electrode lines are arranged on the mth grid line. Between the gate line and the m-2th gate line, each of which includes a first gap, the second gate lead-out line passes through the second gap of the m-1th gate line and the three The three first gaps of the first common electrode line extend to the position where the sixth via hole connection structure is located, and the sixth via hole connection structure is located between the m-2th gate line and the Between the first common electrode lines, the first gate lead-out line is connected to the second gate lead-out line through the sixth via connection structure.

For example, an array substrate provided by an embodiment of the present disclosure further includes: a shielding electrode located on the base substrate and disposed on the same layer as the gate line.

For example, in an array substrate provided in an embodiment of the present disclosure, the orthographic projection of the shielding electrode on the base substrate is located between the orthographic projection of the second common electrode line on the base substrate and the Between the orthographic projection of the data line on the base substrate, and between the orthographic projection of the second common electrode line on the base substrate and the orthographic projection of the signal line on the base substrate between.

For example, in an array substrate provided by an embodiment of the present disclosure, the orthographic projection of the shielding electrode on the base substrate is also located between the orthographic projection of the data line on the base substrate and the signal Lines between orthographic projections on the substrate substrate.

At least one embodiment of the present disclosure further provides a display device, which includes the array substrate described in any one of the above.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present disclosure more clearly, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure .

1 is a schematic plan view of an array substrate;

FIG. 2 is a schematic plan view of an array substrate provided by an embodiment of the present disclosure;

FIG. 3 is an enlarged schematic diagram of a driving transistor in an array substrate provided by an embodiment of the present disclosure;

FIG. 4 is a schematic plan view of another array substrate provided by an embodiment of the present disclosure;

FIG. 5 is an enlarged schematic diagram of a driving transistor in another array substrate provided by an embodiment of the present disclosure;

FIG. 6A is a schematic plan view of another array substrate provided by an embodiment of the present disclosure;

FIG. 6B is a schematic plan view of another array substrate provided by an embodiment of the present disclosure;

FIG. 7A is a schematic diagram of another array substrate provided by an embodiment of the present disclosure;

FIG. 7B is a schematic diagram of another array substrate provided by an embodiment of the present disclosure;

FIG. 8A is a schematic cross-sectional view of an array substrate along line AB in FIG. 7A according to an embodiment of the present disclosure;

FIG. 8B is a schematic cross-sectional view of an array substrate along line CD in FIG. 7A according to an embodiment of the present disclosure;

FIG. 9 is a schematic plan view of another array substrate provided by an embodiment of the present disclosure;

FIG. 10 is a schematic plan view of another array substrate provided by an embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a display device provided by an embodiment of the present disclosure; and

FIG. 12 is a schematic cross-sectional view of a display device provided by an embodiment of the present disclosure.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those skilled in the art to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Comprising" or "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other elements or items.

FIG. 1 is a schematic plan view of an array substrate. As shown in FIG. 1, the array substrate 10 includes a base substrate 11, a plurality of gate lines 12 and a plurality of data lines 13; a plurality of gate lines 12 and a plurality of data lines 13 are arranged to cross each other to define a plurality of pixel units 20; each pixel unit 20 includes a pixel electrode 14, a common electrode 15 and a drive transistor 16; the gate line 12 is connected to the gate of the drive transistor 16, the data line 13 is connected to the source of the drive transistor 16, and the pixel electrode 14 is connected to the drive transistor 16 connected to the drain. In order to continuously emit light, a storage capacitor needs to be formed between the pixel electrode 14 and the common electrode 15 in the pixel unit 20 . However, in an actual array substrate, in addition to the storage capacitor used for normal display, the pixel electrode 14 will also form parasitic capacitors with other conductive structures. For example, a parasitic capacitance Cpd1 is formed between the pixel electrode 14 and the data line 13 , and a parasitic capacitance Cpd2 is formed between the pixel electrode 14 and the source of the driving transistor 16 .

As shown in FIG. 1 , since the driving transistor 16 is usually arranged close to the data line 13 , it is easy to cause a parasitic capacitance difference between the pixel electrode 14 and other conductive structures on the left and right sides. On the left side, the pixel electrode 14 forms a parasitic capacitance Cpd1 with the data line 13 on the left side, and forms a parasitic capacitance Cpd2 with the source of the drive transistor 16; on the right side, the pixel electrode 14 forms a parasitic capacitance with the data line 13 on the right side Cpd3. At this time, the parasitic capacitance C1=Cpd1+Cpd2 generated between the pixel electrode 14 and the conductive structure on the left, and the parasitic capacitance C2=Cpd3 generated between the pixel electrode 14 and the conductive structure on the right. Usually, Cpd1 and Cpd3 are roughly equal. At this time, the parasitic capacitance C1 generated between the pixel electrode 14 and the conductive structure on the left is greater than the parasitic capacitance C2 generated between the pixel electrode 14 and the conductive structure on the right.

The pixel electrode 14 and other conductive structures on the left and right sides produce different parasitic capacitances, which will lead to poor grayscale V-Crosstalk (crosstalk); and, for high-resolution products, such as 8K products, due to the small size of the pixel unit, its own The storage capacitance of the pixel is small, so it is more likely to be pulled by the parasitic capacitance, and the V-Crosstalk failure caused by the difference between the parasitic capacitance of the pixel electrode and other conductive structures on the left and right sides will be more obvious.

In this regard, embodiments of the present disclosure provide an array substrate and a display device. The array substrate includes a base substrate, a plurality of sub-pixel units, gate lines, data lines and signal lines; a plurality of sub-pixel units are located on the base substrate, and the plurality of sub-pixel units are arrayed along the first direction and the second direction to form A sub-pixel row extending in one direction and a sub-pixel column extending in a second direction; the gate line is located on the substrate, extending along the first direction and configured to provide a gate signal to the sub-pixel row; the data line is located in the substrate The base substrate extends along the second direction; the signal line is located on the base substrate and extends in the second direction; the data line and the signal line are respectively located on both sides of the sub-pixel column in the first direction, and each sub-pixel unit includes a pixel electrode , the distance between the pixel electrode and the data line is the first distance D1, the distance between the pixel electrode and the signal line is the second distance D2, the side length of the pixel electrode close to the data line is L1, and the side length of the pixel electrode close to the signal line L2; each sub-pixel unit also includes a driving transistor, the driving transistor includes a source and a drain, the source is connected to one of the data line and the signal line, and the drain is connected to the pixel electrode; the drain and the source are connected on the first side The upward distance is the third distance D3, the distance between the drain and the other of the data line and the signal line is the fourth distance D4, the dimension of the source in the second direction is L3, and the dimension of the drain in the second direction For L4, the ratio range of (E1*L1/D1+E2*L3/D3) and (E1*L2/D2+E2*L4/D4) is 0.9-1.1, and E1 is between the pixel electrode and the data line or signal line The dielectric constant of the film layer, E2 is the dielectric constant of the film layer between the drain electrode and the source electrode or the signal line. Thus, since the ratio range of (E1*L1/D1+E2*L3/D3) to (E1*L2/D2+E2*L4/D4) is 0.9-1.1, the pixel electrodes in each sub-pixel unit are connected to the left and right two The parasitic capacitance generated by other conductive structures on the side is roughly equal, so that the gray scale V-Crosstalk (crosstalk) can be effectively avoided and the display quality can be improved.

Hereinafter, the array substrate and the display device provided by the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

An embodiment of the present disclosure provides an array substrate. FIG. 2 is a schematic plan view of an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 2, the array substrate 100 includes a base substrate 110, a plurality of sub-pixel units 120, gate lines 130, data lines 141 and signal lines 142; a plurality of sub-pixel units 120 are located on the base substrate 110, and a plurality of sub-pixel units 120 are arrayed along the first direction X and the second direction Y to form sub-pixel rows 210 extending in the first direction X and sub-pixel columns 220 extending in the second direction Y; the gate lines 130 are located on the base substrate 110 , extending along the first direction and configured to provide gate signals to the sub-pixel row 210; the data line 141 is located on the base substrate 110 and extends along the second direction; the signal line 142 is located on the base substrate 110 and extends along the second direction Extension; the data line 141 and the signal line 142 are respectively located on both sides of the sub-pixel column 220 in the first direction, and each sub-pixel unit 120 includes a pixel electrode 122 .

As shown in Figure 2, the distance between the pixel electrode 122 and the data line 141 is the first distance D1, the distance between the pixel electrode 122 and the signal line 142 is the second distance D2, and the side length of the pixel electrode 122 close to the data line 141 L1, the side length of the pixel electrode 122 close to the signal line 142 is L2; each sub-pixel unit 120 also includes a driving transistor T1, and the driving transistor T1 includes a source Source1 and a drain Drain1, and the source Source1 is connected to the data line 141 and the signal line 142 The drain Drain1 is connected to the pixel electrode 122; the distance between the drain Drain1 and the source Source1 in the first direction X is the third distance D3, and the drain Drain1 is connected to the other of the data line 141 and the signal line 142 The distance is the fourth distance D4, the size of the source Source1 in the second direction is L3, the size of the drain Drain1 in the second direction is L4, (E1*L1/D1+E2*L3/D3) and (E1 *L2/D2+E2*L4/D4) The ratio range is 0.9-1.1, E1 is the dielectric constant of the film layer between the pixel electrode 122 and the data line 141 or the signal line 142, E2 is the signal line 142 and the source electrode The dielectric constant of the film layer between Source1 or drain Drain1.

In the array substrate provided in the embodiment of the present disclosure, the pixel electrode 122 is provided with the data line 141 on the first side in the first direction X (for example, the left side in FIG. 2 ), and the second side in the first direction X ( For example, the right side in FIG. 2 ) is provided with a signal line 142 . On the first side of the pixel electrode 122, the parasitic capacitance Cpd1=E1*L1/D1 between the pixel electrode 122 and the data line 141, and the parasitic capacitance Cpd2=E2 between the drain Drain1 connected to the pixel electrode 122 and the source Source1 *L3/D3; at this time, the parasitic capacitance C1 between the pixel electrode 122 and the conductive structure on the first side of the pixel electrode 122=E1*L1/D1+E2*L3/D3. On the second side of the pixel electrode 122, the parasitic capacitance Cpd3=E1*L2/D2 between the pixel electrode 122 and the signal line 142, the parasitic capacitance between the drain Drain1 connected to the pixel electrode 122 and the data line 141 or signal line 142 Capacitance Cpd4=E2*L4/D4; at this time, the parasitic capacitance C2 between the pixel electrode 122 and the conductive structure on the second side of the pixel electrode 122=E1*L2/D2+E2*L4/D4. Since the ratio range of (E1*L1/D1+E2*L3/D3) to (E1*L2/D2+E2*L4/D4) is 0.9-1.1, the pixel electrode in each sub-pixel unit and the pixel electrode at the Parasitic capacitances of other conductive structures on the first side and the second side (for example, the left and right sides in FIG. 2 ) in one direction are approximately equal, thereby effectively avoiding grayscale V-Crosstalk (crosstalk) defects and improving display quality. It should be noted that, the above-mentioned first side and second side of the pixel electrode are divided by an area bisector of the pixel electrode in the first direction.

In some examples, the ratio of (E1*L1/D1+E2*L3/D3) to (E1*L2/D2+E2*L4/D4) is in the range of 0.95-1.05, so that the gray scale V- Crosstalk (crosstalk) is bad and improves display quality.

In some examples, the ratio of (E1*L1/D1+E2*L3/D3) to (E1*L2/D2+E2*L4/D4) is in the range of 0.99-1.01, so that the gray scale V- Crosstalk (crosstalk) is bad and improves display quality.

In some examples, the ratio of (E1*L1/D1+E2*L3/D3) to (E1*L2/D2+E2*L4/D4) is in the range of 0.995-1.005, so that the gray scale V- Crosstalk (crosstalk) is bad and improves display quality.

In some examples, the ratio of (E1*L1/D1+E2*L3/D3) to (E1*L2/D2+E2*L4/D4) is equal to 1, which can better avoid grayscale V-Crosstalk (crosstalk ) bad, and improve the display quality.

In some examples, as shown in FIG. 2 , the data line 141 located on one side of the jth subpixel column 220 in the first direction is configured to provide a data signal to the jth subpixel column 220 . The signal line 142 on the other side in the first direction is configured to provide a data signal to the j+1th sub-pixel column 220 , where j is a positive integer greater than or equal to 1. That is, both the data line 141 and the signal line 142 are configured to transmit data signals.

In some examples, as shown in FIG. 2 , the signal line 142 located on one side of the j-th sub-pixel column 220 in the first direction is connected to the data line 142 located on one side of the j+1-th sub-pixel column 220 in the first direction. Line 141 is configured to be connected to the same signal terminal. At this time, the signal line 142 located on one side of the j-th sub-pixel column 220 in the first direction is configured to transmit the same data signal.

In some examples, the signal line can also be used to transmit other signals, for example, the signal line is configured to transmit a common electrode signal. For example, as shown in Figure 2, the gate line 130 is mutually insulated from the data line 141 and the signal line 142; An insulating layer may be provided between the layers.

For example, the film layer between the pixel electrode 122 and the data line 141 or the signal line 142 can be an optical adhesive layer; the material of the optical adhesive layer includes polyethylene, and its dielectric constant can be in the range of 2.2-2.5.

For example, the film layer between the signal line 142 and the source electrode Source1 or the drain electrode Drain1 can be a passivation layer; the material of the passivation layer includes silicon nitride, silicon oxide or silicon oxynitride, and the range of its dielectric constant can be 1.56 -3.9.

For example, the base substrate 110 may be a glass substrate, a plastic substrate, a quartz substrate, or a polyimide substrate. Of course, the embodiments of the present disclosure include but are not limited thereto, and other substrates may also be used as the base substrate.

For example, the gate lines 130, the data lines 141 and the signal lines 142 can be made of the same conductive material, or can be made of different conductive materials. For example, the materials of the gate lines 130 , the data lines 141 and the signal lines 142 include one or more selected from aluminum, aluminum alloy, copper, copper alloy, molybdenum, and molybdenum-aluminum alloy.

For example, the value range of the first distance D1 between the pixel electrode 122 and the data line 141 can be 10-12 microns, for example, 10.9 microns; the second distance D2 between the pixel electrode 122 and the signal line 142 can also be 10. -12 microns, such as 10.9 microns; the value range of the third distance D3 between the drain Drain1 and the source Source1 in the first direction X can be 5.1-6.4 microns, such as 5.79 microns; the distance between the drain Drain1 and the signal line 142 The value range of the four-distance D4 may be 5.1-6.4 microns, for example, 5.79 microns.

For example, the value range of the side length L1 of the pixel electrode 122 close to the data line 141 can be 110-120 microns, for example, 114 microns; the side length L2 of the pixel electrode 122 close to the signal line 142 can also be 110-120 microns, such as 114 microns. microns; the value range of the dimension L3 of the source Source1 in the second direction may be 20-24 microns, such as 22 microns; the value range of the dimension L4 of the drain Drain in the second direction may be 20-24 microns, For example 22 microns.

In some examples, E1=2.3, E2=1.6, D1=11 μm, L1=114 μm, D2=10.1 μm, L2=119 μm, D3=5.2 μm, L3=22.1 μm, D4=5.1 μm, L4=22.1 μm, Therefore, (E1*L1/D1+E2*L3/D3)/(E1*L2/D2+E2*L4/D4)=0.900.

In some examples, E1=2.3, E2=1.6, D1=11 μm, L1=114 μm, D2=10.6 μm, L2=114 μm, D3=5.2 μm, L3=22.1 μm, D4=5.1 μm, L4=23.9 μm, Therefore, (E1*L1/D1+E2*L3/D3)/(E1*L2/D2+E2*L4/D4)=0.950.

In some examples, E1=2.3, E2=1.6, D1=11 μm, L1=114 μm, D2=11 μm, L2=114 μm, D3=5.2 μm, L3=22.1 μm, D4=5.2 μm, L4=22.1 μm, so , (E1*L1/D1+E2*L3/D3)/(E1*L2/D2+E2*L4/D4)=1.

In some examples, E1=2.3, E2=1.6, D1=11 μm, L1=114 μm, D2=11.1 μm, L2=114 μm, D3=5.2 μm, L3=22.1 μm, D4=6.4 μm, L4=22.1 μm, Therefore, (E1*L1/D1+E2*L3/D3)/(E1*L2/D2+E2*L4/D4)=1.051.

In some examples, E1=2.3, E2=1.6, D1=11 μm, L1=114 μm, D2=11.8 μm, L2=114 μm, D3=5.2 μm, L3=22.1 μm, D4=6.4 μm, L4=22.6 μm, Therefore, (E1*L1/D1+E2*L3/D3)/(E1*L2/D2+E2*L4/D4)=1.099.

In some examples, as shown in FIG. 2 , the connection portion 1220 between the pixel electrode 122 and the drain Drain1 is located on the bisector of the area of the pixel electrode 122 in the first direction. Thus, the parasitic capacitance Cpd2 between the drain Drain1 and the source Source1 and the parasitic capacitance Cpd4 between the drain Drain1 and the signal line 142 are both connected to the middle of the pixel electrode 122 in the first direction, so that for the pixel electrode 122 in The influence of the parasitic capacitances on both sides of the first direction is more balanced, so that the gray scale V-Crosstalk (crosstalk) can be further effectively avoided, and the display quality can be improved. It should be noted that the above-mentioned area bisector may be an area bisector of the orthographic projection of the pixel electrode on the base substrate.

In some examples, as shown in FIG. 2 , the side length L1 of the pixel electrode 122 close to the data line 141 is equal to the side length L2 of the pixel electrode 122 close to the signal line 142 , and the first distance D1 is equal to the second distance D2 . Thus, the parasitic capacitance Cpd1=E1*L1/D1 between the pixel electrode 122 and the data line 141 is equal to the parasitic capacitance Cpd3=E1*L2/D2 between the pixel electrode 122 and the signal line 142, thereby ensuring that the pixel electrode 122 The data line 141 and the signal line 142 on both sides are equal to the parasitic capacitance generated by the pixel electrode 122 .

In some examples, as shown in FIG. 2 , the dimension L3 of the source Source1 in the second direction Y is equal to the dimension L4 of the drain Drain1 in the second direction Y, and the third distance D3 and the fourth distance D4 are equal. Therefore, the parasitic capacitance Cpd2=E2*L3/D3 between the drain Drain1 and the source Source1 and the parasitic capacitance Cpd4=E2*L4/D4 between the drain Drain1 and the signal line 142 are equal, thereby ensuring that the drain Drain1 is about The source Source1 and the signal line 142 on both sides are equal to the parasitic capacitance generated by the drain Drain1.

In the array substrate provided in the above example, the parasitic capacitance Cpd1 between the pixel electrode 122 and the data line 141 = E1 * L1 / D1 and the parasitic capacitance Cpd3 between the pixel electrode 122 and the signal line 142 = E1 * L2 / D2 is set equal, and the parasitic capacitance Cpd2=E2*L3/D3 between the drain Drain1 and the source Source1 and the parasitic capacitance Cpd4=E2*L4/D4 between the drain Drain1 and the signal line 142 are set equal, so that It can better guarantee E1*L1/D1+E2*L3/D3=E1*L2/D2+E2*L4/D4, thereby effectively avoiding grayscale V-Crosstalk (crosstalk) failure and improving display quality.

In some examples, as shown in FIG. 2 , each sub-pixel unit 120 includes a first region 120A and a second region 120B sequentially arranged along the second direction Y, the pixel electrode 122 is located in the first region 120A, and the driving transistor T1 is located in the second region. Area 120B. In this case, the first region 120A may be a light emitting region or a color filter region, and the second region 120B may be a driving region or a TFT region.

In some examples, as shown in FIG. 2 , in the second region 120B, the source electrode Source1 and the data line 141 or the signal line 142 connected to the source electrode Source1 are relatively spaced apart from each other. At this time, the array substrate 100 further includes a conductive connection block 151 through which the source electrode Source1 is connected to the data line 141 or the signal line 142 connected to the source electrode Source1; the source electrode Source1 is connected to the data line connected to the source electrode Source1 141 or the distance between the signal lines 142 is a fifth distance D5, and the fifth distance D5 is equal to the fourth distance D4. That is to say, the third distance D3, the fourth distance D4 and the fifth distance D5 are all equal. Therefore, the driving transistor T1 is located on the bisector of the area of the pixel electrode 122 in the first direction as a whole, thereby improving the symmetry of the driving transistor T1 and further improving the symmetry of the sub-pixel unit 120 .

As shown in Figure 2, Figure 2 shows four sub-pixel units 120, including a first sub-pixel unit 1201, a second sub-pixel unit 1202, a third sub-pixel unit 1203 and a fourth sub-pixel unit 1204; The unit 1201, the second sub-pixel unit 1202, the third sub-pixel unit 1203 and the fourth sub-pixel unit 1204 are arranged in sequence along the first direction X; in the first sub-pixel unit 1201 and the second sub-pixel unit 1202, the source electrode Source1 It is connected to the data line 141 ; in the third sub-pixel unit 1203 and the fourth sub-pixel unit 1204 , the source electrode Source1 is connected to the signal line 142 . Thus, taking the above four sub-pixel units 120 as a whole, the symmetry of the four sub-pixel units 120 in the first direction is improved.

In some examples, as shown in FIG. 2 , the orthographic projection of the pixel electrode 122 on the base substrate 110 is axisymmetric with respect to the area bisector of the pixel electrode 122 in the first direction, so that the symmetry of the pixel electrode 122 can be improved.

In some examples, as shown in FIG. 2 , the pixel electrode 122 includes a first domain 161, a second domain 162, a third domain 163, and a fourth domain 164; The area bisector in a direction X is axisymmetric, the third domain 163 and the fourth domain 164 are axisymmetric with respect to the area bisector of the pixel electrode 122 in the first direction X; the first domain 161 and the third domain 163 are along the The second direction Y is arranged sequentially, and the second domain 162 and the fourth domain 163 are arranged sequentially along the second direction Y. Therefore, by disposing the pixel electrode 122 as the first domain 161 , the second domain 162 , the third domain 163 and the fourth domain 164 , the array substrate can reduce color shift and improve display effect.

In addition, since the first domain 161 and the second domain 162 are axisymmetric with respect to the area bisector of the pixel electrode 122 in the first direction X, the third domain 163 and the fourth domain 164 are symmetrical with respect to the area bisector of the pixel electrode 122 in the first direction X. The bisector of the area is axisymmetric, so the symmetry of the pixel electrode 122 is relatively high.

In some examples, as shown in FIG. 2 , the pixel electrode 122 further includes a middle portion 1225 extending along the second direction Y and located between the first domain 161 and the second domain 162 , the third domain 163 and the second domain 163 . Between the four domains 164 ; the drain Drain1 is connected to the middle part 1225 of the pixel electrode 122 . Thus, the parasitic capacitance Cpd2 between the drain Drain1 and the source Source1 and the parasitic capacitance Cpd4 between the drain Drain1 and the signal line 142 are both connected to the middle of the pixel electrode 122 in the first direction, so that for the pixel electrode 122 in The influence of the parasitic capacitances on both sides of the first direction is more balanced, so that the gray scale V-Crosstalk (crosstalk) can be further effectively avoided, and the display quality can be improved.

In some examples, as shown in FIG. 2 , the pixel electrode 122 includes a plurality of first slits 1224A arranged at intervals, located in the first domain 161; a plurality of second slits 1224B arranged at intervals, located in the second domain 162; The third slits 1224C arranged at intervals are located in the third domain 163 ; and the fourth slits 1224D arranged at intervals are located in the fourth domain 164 .

FIG. 3 is an enlarged schematic diagram of a driving transistor in an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 3 , the width of the sub-pixel unit 120 in the first direction X is Wpixel, the driving transistor T1 includes an active layer A1, the length of the channel region of the active layer A1 in the first direction X is L, and The length of the channel region of the source layer A in the second direction Y is W; the width of the source electrode Source1 in the first direction X is Wsource, the width of the drain Drain1 in the first direction X is Wdrain, and the data line 141 or The width of the signal line 142 in the first direction X is Wdata. At this time, the length L of the channel region of the active layer A1 in the first direction X satisfies the following formula:

Wsource+Wdrain<L<(Wpixel-2Wdata-Wsource-Wdrain)/3.

In the array substrate provided by the embodiment of the present disclosure, the calculation formula of the turn-on current I _on of the driving transistor T1 is as follows:

Wherein, W and L are respectively the width and length of the channel region of the active layer A1 of the drive transistor T1, μ _n is the equivalent electron mobility, C _SiNx is the capacitance of the drive transistor T1, and V _TH is the threshold value of the drive transistor T1 Voltages, V _G and V _D are the voltages of the gate G1 and the drain Drain1 of the driving transistor T1 relative to the source Source1.

It can be seen from the above formula that factors affecting the turn- _on current Ion of the driving transistor T1 mainly include the ratio W/L of the width to the length of the channel region, electron mobility and the like. In order to obtain a larger turn-on current I _on , the ratio W/L of the width to the length of the channel region needs to be set larger. Therefore, by making the length L of the channel region of the active layer A1 in the first direction X satisfy the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wsource-Wdrain)/3, the size of the active layer can be reduced The length of the channel region of A1 in the first direction X is L, so that the ratio W/L of the width to the length of the channel of the driving transistor T1 can be increased, thereby increasing the turn-on current.

In some examples, the length L of the channel region of the active layer A1 in the first direction X satisfies the following formula: Wsource+Wdrain<L<(Wpixel−2Wdata−Wsource−Wdrain)/4. Therefore, by making the length L of the channel region of the active layer A1 in the first direction X satisfy the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wsource-Wdrain)/4, the effective The length of the channel region of the source layer A1 in the first direction X is L, so that the ratio W/L of the width to the length of the channel of the driving transistor T1 can be increased, thereby increasing the turn-on current.

FIG. 4 is a schematic plan view of another array substrate provided by an embodiment of the present disclosure. As shown in FIG. 4 , the source electrode Source1 is a part of the data line 141 or the signal line 142 connected to the source electrode Source1 . Therefore, the array substrate 100 does not need to be provided with the above-mentioned conductive connection block, and the data line 141 or the signal line 142 connected to the source electrode Source1 directly overlaps the active layer A1 of the driving transistor T1 .

As shown in Figure 4, the distance between the pixel electrode 122 and the data line 141 is the first distance D1, the distance between the pixel electrode 122 and the signal line 142 is the second distance D2, and the side length of the pixel electrode 122 close to the data line 141 L1, the side length of the pixel electrode 122 close to the signal line 142 is L2; the distance between the drain Drain1 and the source Source1 in the first direction is the third distance D3, and the distance between the drain Drain1 and the signal line 142 is the fourth distance D4 , the size of the drain Drain1 in the second direction is L3, and the size of the source Source1 in the second direction is L4. The above-mentioned L1, L2, L3, L4, D1, D2, D3, and D4 also satisfy the following formula:

E1*L1/D1+E2*L3/D3=E1*L2/D2+E2*L4/D4,

Wherein, E1 is the dielectric constant of the film layer between the pixel electrode 122 and the data line 141 or the signal line 142 , and E2 is the dielectric constant of the film layer between the signal line 142 and the source electrode Source1 or the drain electrode Drain1 .

In the array substrate, the pixel electrode 122 is provided with a data line 141 on the first side in the first direction X (for example, the left side in FIG. Right side) is provided with a signal line 142 . On the first side of the pixel electrode 122, the parasitic capacitance Cpd1=E1*L1/D1 between the pixel electrode 122 and the data line 141, and the parasitic capacitance Cpd2=E2 between the drain Drain1 connected to the pixel electrode 122 and the source Source1 *L3/D3; at this time, the parasitic capacitance C1 between the pixel electrode 122 and the conductive structure on the first side of the pixel electrode 122=E1*L1/D1+E2*L3/D3. On the second side of the pixel electrode 122, the parasitic capacitance Cpd3=E1*L2/D2 between the pixel electrode 122 and the signal line 142, and the parasitic capacitance Cpd4=E2 between the drain Drain1 connected to the pixel electrode 122 and the signal line 142 *L4/D4; at this time, the parasitic capacitance C2 between the pixel electrode 122 and the conductive structure on the second side of the pixel electrode 122=E1*L2/D2+E2*L4/D4. Since the ratio range of (E1*L1/D1+E2*L3/D3) to (E1*L2/D2+E2*L4/D4) is 0.9-1.1, the pixel electrode and the pixel electrode in each sub-pixel unit are in the first The other conductive structures on the first side and the second side in the direction (for example, the left and right sides in FIG. 4 ) generate approximately equal parasitic capacitances, thereby effectively avoiding grayscale V-Crosstalk (crosstalk) defects and improving display quality. It should be noted that, the above-mentioned first side and second side of the pixel electrode are divided by an area bisector of the pixel electrode in the first direction.

FIG. 5 is an enlarged schematic diagram of a driving transistor in another array substrate provided by an embodiment of the present disclosure. As shown in FIG. 5 , the width of the sub-pixel unit 120 in the first direction X is Wpixel, the driving transistor T1 includes an active layer A1, the length of the channel region of the active layer A1 in the first direction X is L, and The length of the channel region of the source layer A1 in the second direction Y is W, the width of the source electrode Source1 in the first direction is Wsource, the width of the drain electrode Drain1 in the first direction is Wdrain, the data line 141 and the signal line The width of 142 in the first direction is Wdata, and the length of the channel region of the active layer in the first direction is L, satisfying the following formula:

Wsource+Wdrain<L<(Wpixel-2Wdata-Wdrain)/2.

In the array substrate, by making the length L of the channel region of the active layer A1 in the first direction X satisfy the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wdrain)/2, the effective The length of the channel region of the source layer A1 in the first direction X is L, so that the ratio W/L of the width to the length of the channel of the driving transistor T1 can be increased, thereby increasing the turn-on current.

For example, the width Wpixel of the sub-pixel unit 120 in the first direction X ranges from 60-64 microns, such as 62 microns; the length L of the channel region of the active layer A1 in the first direction X ranges from 5-7 microns. microns, such as 5.79 microns, the range of the length W of the channel region of the active layer A1 in the second direction Y can be 9-12.5 microns, such as 11.24 microns, and the range of the width Wsource of the source electrode Source1 in the first direction can be 2-4 microns, such as 2.57 microns, the drain Drain1 width Wdrain in the first direction can range from 2-4 microns, such as 2.57 microns, the width Wdata of the data line 141 and the signal line 142 in the first direction The range may be 4-6 microns, such as 5.4 microns. At this point, the formula for calculating the turn-on current I _on is:

可以简化为

can be simplified to

Wherein, the value range of k may be 1.05-1.20, for example, k=1.11.

FIG. 6A is a schematic plan view of another array substrate provided by an embodiment of the present disclosure; FIG. 6B is a schematic plan view of another array substrate provided by an embodiment of the present disclosure. As shown in FIG. 6A, a plurality of sub-pixel units 120 form n sub-pixel rows 210 arranged in the second direction Y, and the array substrate 100 includes n gate lines 130, which are set in one-to-one correspondence with the n sub-pixel rows 210; the kth The gate lines 130 and the k+1th gate line 130 form a (k+1)/2th gate line group 1300 . At this time, the array substrate 100 further includes a first vertical gate line 131 and a second vertical gate line 132, which are respectively located on both sides of the plurality of sub-pixel units 120 in the first direction, and the (k+1)/2th gate line In the line group 1300, the kth gate line 130 and the k+1th gate line 130 are connected through the first vertical gate line 131 and the second vertical gate line 132, k can be an odd number greater than or equal to 1, and n can be greater than or equal to A positive integer of k. Thus, a gate line group 1300 can have a ring structure, thereby reducing the signal delay on the gate lines and improving the display quality of the array substrate.

In some examples, as shown in FIG. 6A and FIG. 6B , the first vertical gate line 131 and the second vertical gate line 132 are arranged on the same layer as the data line 141 .

In some examples, as shown in FIG. 6A and FIG. 6B, the first vertical gate line 131 is connected to the kth gate line 130 through the first via connection structure H1, and the first vertical gate line 131 passes through the second via hole. The connection structure H2 is connected to the k+1th gate line 130, the second vertical gate line 132 is connected to the kth gate line 130 through the third via connection structure H3, and the second vertical gate line 132 is connected to the kth gate line 130 through the fourth via hole. The hole connection structure H4 is connected to the k+1th gate line 130 . It should be noted that the above-mentioned via connection structure generally includes a via hole in the insulating layer between the two conductive film layers and a conductive structure located in the via hole, so that the two conductive film layers can be electrically connected.

In some examples, as shown in FIG. 6B, the array substrate 100 further includes at least one intermediate vertical gate line 135, located between two adjacent sub-pixel columns 220; the (k+1)/2th gate line group In 1300 , the k-th gate line 130 and the k+1-th gate line 130 are connected through an intermediate vertical gate line 135 . Thus, the middle vertical grid line can be used to connect two grid lines in the same grid line group, so that when the first vertical grid line or the second vertical grid line is short-circuited, the two grid lines of the same grid line group The electrical connection of the gate lines can reduce the signal delay of the sub-pixel units located in the middle of the array substrate.

In some examples, as shown in FIG. 6B , the middle vertical gate line 135 is provided on the same layer as the gate line 130 , so that no additional via connection structure is required, and can be formed by using the same metal film layer and the same patterning process.

In some examples, as shown in FIG. 6A and FIG. 6B , both the data line 141 and the signal line 142 are configured to transmit data signals, and the sources Source1 of some sub-pixel units 120 in the sub-pixel column 220 are connected to the data line 141, Sources Source1 of another part of the sub-pixel units 120 in the sub-pixel row 220 are connected to the signal line 142 .

FIG. 7A is a schematic diagram of another array substrate provided by an embodiment of the present disclosure; FIG. 7B is a schematic diagram of another array substrate provided by an embodiment of the present disclosure. As shown in FIG. 7A, the array substrate 100 further includes first common electrode lines 171 and second common electrode lines 172; the first common electrode lines 171 extend along the first direction X, and the second common electrode lines 172 extend along the second direction Y. Extension; each sub-pixel unit 120 includes a first region 120A and a second region 120B arranged in sequence along the second direction Y, the pixel electrode 122 is located in the first region 120A, and the driving transistor T1 is located in the second region 120B; the first common electrode line 171 Located between two adjacent sub-pixels 120 in the second direction Y, and between the first region 120A and the second region 120B of the same sub-pixel 120; the second common electrode line 172 is located in two adjacent sub-pixel columns 220 Between, so that the mutual influence between the data signals of adjacent sub-pixel units 120 can be shielded.

In some examples, as shown in FIG. 7A , each sub-pixel unit 120 includes a first region 120A and a second region 120B sequentially arranged along the second direction Y, the pixel electrode 122 is located in the first region 120A, and the driving transistor T1 is located in the second region. Region 120B; the width of the part where the second common electrode line 172 is located in the first region 120A is larger than the width of the part where the second common electrode line 172 is located in the second region 120B, that is, the part where the second common electrode line is located in the first region is on the substrate The width of the orthographic projection on the base substrate is greater than the width of the orthographic projection of the portion of the second common electrode line located in the second region on the base substrate. Therefore, when the array substrate adopts a COA (color filter on array) structure, the color filter can be arranged in the first region 120A. At this time, by setting the width of the second common electrode line 172 larger, the array The substrate 100 can use the second common electrode lines 172 as a black matrix to achieve a light-shielding effect.

In some examples, as shown in FIGS. 7A and 7B , the second common electrode lines 172 include gate layer common electrode lines 1721 and data line layer common electrode lines 1722; the gate layer common electrode lines 1721 and the gate line 130 are arranged on the same layer , and connected to the data line layer common electrode line 1722 through a via hole, thereby reducing the resistance of the second common electrode line 172 .

In some examples, as shown in FIG. 7A and FIG. 7B , the first common electrode line 171 is provided on the same layer as the gate line 130 , and the first common electrode line 171 includes at least one first notch 1710 and two sides of the first notch 1710 . The first sub-common electrode line 1712 and the middle vertical gate line 135 pass through the first gap 1710 and are spaced and insulated from the first sub-common electrode line 1712 respectively. Therefore, by providing the first notches 1710 on the first common electrode lines 171 , it is convenient to arrange the above-mentioned intermediate vertical gate lines 135 .

In some examples, as shown in FIG. 7A and FIG. 7B, two first common electrode lines 171 are arranged on the kth gate line 130 and the k+1th gate line group 1300 in the (k+1)/2th gate line group 1300. Between the gate lines 130, and respectively include first gaps 1710, the middle vertical gate line 135 passes through the two first gaps 1710 of the two first common electrode lines 171 to connect the kth gate line 130 and the k+1th gate line 130 The grid lines 130 are connected.

In some examples, as shown in FIG. 7A and FIG. 7B , in the case where the above-mentioned intermediate vertical grid lines 135 are provided, since the intermediate vertical grid lines 135 are arranged on the same layer as the grid lines 130; at this time, the intermediate vertical grid lines The second common electrode line 172 at the location of the gate line 135 may not include the gate layer common electrode line 1721 . In some examples, as shown in FIG. 7A and FIG. 7B, the second common electrode line 172 is located between the lth subpixel column 220 and the l+1th subpixel column 220, and the second common electrode line 172 is connected to the lth subpixel column 220. The distance between the signal lines 142 corresponding to the column 220 is equal to the distance between the second common electrode line 172 and the data line 141 corresponding to the l+1th sub-pixel column 220, or, the second common electrode line 172 is the same as the distance between the l+1th sub-pixel column 220. The distance between the data lines 141 corresponding to the pixel column 220 is equal to the distance between the second common electrode line 172 and the signal line 142 corresponding to the l+1th sub-pixel column 220, where l is a positive integer greater than or equal to 1.

FIG. 8A is a schematic cross-sectional view of an array substrate provided by an embodiment of the present disclosure along line AB in FIG. 7A . As shown in FIG. 8A, the second common electrode line 172 includes a gate layer common electrode line 1721 and a data line layer common electrode line 1722; the gate layer common electrode line 1721 is set on the same layer as the gate line 130, and passes through the fifth via hole The connection structure H5 is connected to the common electrode line 1722 of the data line layer, so as to reduce the resistance of the second common electrode line 172 .

In some examples, as shown in FIG. 8A, the array substrate 100 further includes a first color filter 191 and a second color filter 192, and the first color filter 191 and the second color filter 192 The orthographic projection on the base substrate 110 and the orthographic projection of the second common electrode line 172 on the base substrate 110 both overlap. At this time, by setting the width of the second common electrode lines 172 larger, the array substrate 100 can use the second common electrode lines 172 as a black matrix to achieve a light-shielding effect.

For example, the width of the part of the second common electrode line 172 located in the first region 120A may be 12.3 microns, and the width of the part of the second common electrode line 172 located in the second region 120B may be 5.5 microns.

For example, as shown in FIG. 8A , the array substrate 100 further includes a shielding electrode 195 located on the base substrate 110 and disposed on the same layer as the gate line 130 . The shielding electrode 195 is used to prevent signal crosstalk between the data line 141 or the signal line 142 and the second common electrode line 172 , thereby improving display quality.

For example, as shown in FIG. 8A, the shielding electrode 195 can be arranged between the data line 141 and the signal line 142 of the same sub-pixel unit 120, thereby also preventing the interference between the data line 141 and the signal line 142 of the same sub-pixel unit 120. signal crosstalk.

例如

For example, the shielding electrode 195 can be made of a transparent conductive oxide material, such as ITO (Indium Tin Oxide). The width range of the shielding electrode 195 in the first direction X is 3-5 microns, such as 4 microns; the thickness range of the shielding electrode 195 perpendicular to the base substrate 110 is

For example

In some examples, as shown in FIG. 8A , the orthographic projection of the shielding electrode 195 on the base substrate 110 is located between the orthographic projection of the second common electrode line 172 on the base substrate 110 and the orthographic projection of the data line 141 on the base substrate 110. Between the orthographic projection, and between the orthographic projection of the second common electrode line 172 on the base substrate 110 and the orthographic projection of the signal line 142 on the base substrate 110 .

8B is a schematic cross-sectional view of an array substrate provided by an embodiment of the present disclosure along CD line in FIG. 7A; as shown in FIG. Between the orthographic projection on the substrate 110 and the orthographic projection of the signal line 142 on the base substrate 110 .

FIG. 9 is a schematic plan view of another array substrate provided by an embodiment of the present disclosure. As shown in FIG. 9 , each sub-pixel unit 120 includes a first region 120A and a second region 120B arranged in sequence along the second direction Y, the pixel electrode 122 is located in the first region 120A, the driving transistor T1 is located in the second region 120B; the data line The distance between the part of the data line 141 in the first region 120A and the part of the signal line 142 in the first region 120A in the first direction is smaller than the part of the data line 141 in the second region 120B and the part of the signal line 142 in the second region 120B The distance in the first direction; the data line 141 includes a first inclined connecting portion 1415, which connects the part of the data line 141 in the first area 120A and the part of the data line 141 in the second area 120B, and the signal line 142 includes a second inclined The connection part 1425 connects the part of the signal line 142 in the first area 120A and the part of the signal line 142 in the second area 120B.

In some examples, as shown in FIG. 9 , the orthographic projection of the first oblique connection portion 1415 on the base substrate 110 overlaps the orthographic projection of the first common electrode line 171 on the base substrate 110 , and the second oblique connection portion The orthographic projection of 1425 on the base substrate 110 overlaps with the orthographic projection of the first common electrode line 171 on the base substrate 110 .

In some examples, as shown in FIG. 9 , the orthographic projection of the via hole H7 connecting the pixel electrode 122 to the drain Drain1 of the driving transistor T1 on the base substrate 110 is located at the first oblique connection portion 1415 and the second oblique connection portion 1425 between.

FIG. 10 is a schematic plan view of another array substrate provided by an embodiment of the present disclosure. As shown in FIG. 10 , the array substrate 100 further includes: a plurality of gate lead-out lines 180, and each gate lead-out line 180 is located between two adjacent sub-pixel columns 220; each gate lead-out line 180 includes: a first gate The electrode lead-out line 181 is arranged on the same layer as the data line 141 and is configured to connect to the gate signal; the second gate lead-out line 182 is arranged on the same layer as the gate line 130 and is configured to be connected to the corresponding gate line 130, The first gate lead-out line 181 and the second gate lead-out line 182 are connected through the sixth via connection structure H6.

In some examples, as shown in FIG. 10 , the gate lead-out line 180 is configured to be electrically connected to the (m+1)/2th gate line group 1300 , and the second gate lead-out line 182 is connected to the m-th gate line 130 directly connected, m is an odd number greater than or equal to 1; the m-1th gate line 130 includes a second gap 1302, and three first common electrode lines 171 are arranged between the m-th gate line 130 and the m-2th gate line 130 and each includes a first gap 1710, the second gate lead-out line 182 passes through the second gap 1302 of the m-1th gate line 130 and the three first gaps 1710 of the three first common electrode lines 171, and extends To the position where the sixth via hole connection structure H6 is located; the sixth via hole connection structure H6 is located between the m-2th gate line 130 and the first common electrode line 171, and the first gate lead-out line 181 passes through the sixth via hole The connection structure H6 is connected to the second gate lead-out line 182 .

At least one embodiment of the present disclosure further provides a display device. FIG. 11 is a schematic diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG. 11 , the display device 400 includes any one of the above array substrates 100 . In the array substrate, the pixel electrode in each sub-pixel unit is approximately equal to the parasitic capacitance generated by other conductive structures on both sides of the pixel electrode in the first direction, so that grayscale V-Crosstalk (crosstalk) defects can be effectively avoided, and Improve display quality. Therefore, the display device can also effectively avoid grayscale V-Crosstalk (crosstalk) defects and improve display quality.

FIG. 12 is a schematic cross-sectional view of a display device provided by an embodiment of the present disclosure. As shown in FIG. 12 , the display device 400 further includes an opposing substrate 300 and a liquid crystal layer 350 , the opposing substrate 300 is arranged at a distance from the array substrate 100 , and the liquid crystal layer 350 is arranged between the opposing substrate 300 and the array substrate 100 ; The substrate 300 includes a common electrode 310 ; the common electrode 310 is spaced apart from the pixel electrode 122 on the array substrate 100 and is configured to form an electric field to drive liquid crystal molecules in the liquid crystal layer 350 to deflect. It can be seen that the display device shown in FIG. 12 adopts the VA mode. Of course, embodiments of the present disclosure include but are not limited thereto. The display device can also adopt the ADS mode or the IPS mode, that is, the common electrode 310 is also disposed on the array substrate 100 .

In some examples, the display device may be any product or component with a display function, such as a liquid crystal display, a smart phone, a tablet computer, a television, a monitor, a smart watch, a notebook computer, a digital photo frame, a navigator, and the like.

The following points need to be explained:

(1) Embodiments of the present disclosure In the drawings, only the structures related to the embodiments of the present disclosure are involved, and other structures may refer to general designs.

(2) In the case of no conflict, features in the same embodiment and different embodiments of the present disclosure can be combined with each other.

The above are only exemplary implementations of the present disclosure, and are not intended to limit the protection scope of the present disclosure, which is determined by the appended claims.

Claims (38)

1. An array substrate, comprising: Substrate substrate; A plurality of sub-pixel units are located on the base substrate and arranged in an array along a first direction and a second direction to form sub-pixel rows extending in the first direction and sub-pixel rows extending in the second direction pixel column; a gate line, located on the base substrate, extending along the first direction and configured to provide a gate signal to the row of sub-pixels; a data line, located on the base substrate, extending along the second direction; and a signal line, located on the base substrate, extending along the second direction; Wherein, the data line and the signal line are respectively located on both sides of the sub-pixel column in the first direction, Each of the sub-pixel units includes a pixel electrode, the distance between the pixel electrode and the data line is a first distance D1, the distance between the pixel electrode and the signal line is a second distance D2, and the distance between the pixel electrode and the data line is a second distance D2. The side length of the pixel electrode close to the data line is L1, the side length of the pixel electrode close to the signal line is L2, Each of the sub-pixel units further includes a driving transistor, the driving transistor includes a source and a drain, the source is connected to one of the data line and the signal line, and the drain is connected to the pixel electrode connected, The distance between the drain and the source in the first direction is a third distance D3, the distance between the drain and the other of the data line and the signal line is a fourth distance D4, The dimension of the source in the second direction is L3, the dimension of the drain in the second direction is L4, Wherein, the ratio range of (E1*L1/D1+E2*L3/D3) and (E1*L2/D2+E2*L4/D4) is 0.9-1.1, and E1 is the pixel electrode and the data line or the The dielectric constant of the film layer between the signal lines, E2 is the dielectric constant of the film layer between the signal line and the source or the drain. 2. The array substrate according to claim 1, wherein the ratio of (E1*L1/D1+E2*L3/D3) to (E1*L2/D2+E2*L4/D4) ranges from 0.95 to 1.05. 3. The array substrate according to claim 2, wherein (E1*L1/D1+E2*L3/D3)=(E1*L2/D2+E2*L4/D4). 4. The array substrate according to claim 1, wherein the data lines and the signal lines are both configured to transmit data signals, and the sources of some of the sub-pixel units in the sub-pixel columns are connected to The data lines are connected, and the sources of another part of the sub-pixel units in the sub-pixel columns are connected to the signal lines. 5. The array substrate according to claim 1, wherein the data line located on one side of the j-th sub-pixel column in the first direction is configured to provide the j-th sub-pixel column For a data signal, the signal line located on the other side of the j-th sub-pixel column in the first direction is configured to provide a data signal to the j+1-th sub-pixel column, where j is A positive integer greater than or equal to 1. 6. The array substrate according to claim 5, wherein the signal line located on one side of the j-th sub-pixel column in the first direction is connected to the signal line located on the j+1-th sub-pixel column The data lines on one side in the first direction are configured to be connected to the same signal terminal. 7. The array substrate according to claim 1, wherein the signal line is configured to transmit a common electrode signal. 8. The array substrate according to any one of claims 1-7, wherein the connection portion between the pixel electrode and the drain electrode is located on a bisector of an area of the pixel electrode in the first direction. 9. The array substrate according to any one of claims 1-7, wherein the side length L1 of the pixel electrode close to the data line is equal to the side length L2 of the pixel electrode close to the signal line, so The first distance D1 is equal to the second distance D2. 10. The array substrate according to any one of claims 1-7, wherein the dimension L3 of the source in the second direction is equal to the dimension L4 of the drain in the second direction , the third distance D3 and the fourth distance D4 are equal. 11. The array substrate according to any one of claims 1-7, wherein each of the sub-pixel units includes a first region and a second region sequentially arranged along the second direction, and the pixel electrode is located at the In the first area, the driving transistor is located in the second area. 12. The array substrate according to claim 11, wherein the source electrode and the data line or the signal line connected to the source electrode are relatively spaced apart from each other, The array substrate further includes a conductive connection block, the source is connected to the data line or the signal line connected to the source through the conductive connection block, The distance between the source and the data line or the signal line connected to the source is a fifth distance D5, and the fifth distance D5 is equal to the fourth distance D4. 13. The array substrate according to claim 12, wherein the width of the sub-pixel unit in the first direction is Wpixel, the driving transistor comprises an active layer, and the channel region of the active layer is at The length in the first direction is L, the length of the channel region of the active layer in the second direction is W, the width of the source in the first direction is Wsource, the The width of the drain electrode in the first direction is Wdrain, the width of the data line and the signal line in the first direction is Wdata, The length L of the channel region of the active layer in the first direction satisfies the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wsource-Wdrain)/3. 14. The array substrate according to claim 13, wherein the length L of the channel region of the active layer in the first direction satisfies the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wsource-Wdrain)/4. 15. The array substrate according to claim 11, wherein the source is a part of the data line or the signal line connected to the source. 16. The array substrate according to claim 15, wherein the width of the sub-pixel unit in the first direction is Wpixel, the driving transistor comprises an active layer, and the channel region of the active layer is at The length in the first direction is L, the length of the channel region of the active layer in the second direction is W, the width of the source in the first direction is Wsource, the The width of the drain electrode in the first direction is Wdrain, the width of the data line and the signal line in the first direction is Wdata, The length L of the channel region of the active layer in the first direction satisfies the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wdrain)/2. 17. The array substrate according to any one of claims 1-7, wherein the orthographic projection of the pixel electrode on the base substrate is about the area bisector of the pixel electrode in the first direction Axisymmetric. 18. The array substrate according to claim 17, wherein the pixel electrode comprises a first domain, a second domain, a third domain and a fourth domain, The first domain and the second domain are axisymmetric with respect to an area bisector of the pixel electrode in the first direction, and the third domain and the fourth domain are axially symmetric with respect to the pixel electrode in the first direction. The area bisector in the first direction is axisymmetric, The first domain and the third domain are sequentially arranged along the second direction, and the second domain and the fourth domain are sequentially arranged along the second direction. 19. The array substrate according to claim 18, wherein the pixel electrode comprises a middle portion, extends along the second direction, and is located between the first domain and the second domain, and the third domain and the fourth domain, The drain is connected to the middle portion of the pixel electrode. 20. The array substrate according to claim 19, wherein the pixel electrode comprises: a plurality of first slits arranged at intervals, located in the first domain; a plurality of second slits arranged at intervals, located in the second domain; a plurality of third slits arranged at intervals, located in the third domain; and A plurality of fourth slits arranged at intervals are located in the fourth domain. 21. The array substrate according to any one of claims 1-7, wherein the plurality of sub-pixel units form n sub-pixel rows arranged in the second direction, and the array substrate includes n rows of the sub-pixels The gate line is set in one-to-one correspondence with the n sub-pixel rows, The kth gate line and the k+1th gate line form a (k+1)/2th gate line group, The array substrate further includes a first vertical gate line and a second vertical gate line, respectively located on both sides of the plurality of sub-pixel units in the first direction, at the (k+1)/2th In the grid line group, the k-th grid line and the k+1-th grid line are connected through the first vertical grid line and the second vertical grid line, Wherein, k may be an odd number greater than or equal to 1, and n is a positive integer greater than k. 22. The array substrate according to claim 21, wherein the first vertical gate lines and the second vertical gate lines are arranged on the same layer as the data lines. 23. The array substrate according to claim 22, wherein the first vertical gate line is connected to the k-th gate line through a first via connection structure, and the first vertical gate line is connected to the second gate line through the second The via connection structure is connected to the k+1 gate line, The second vertical gate line is connected to the kth gate line through the third via hole connection structure, and the second vertical gate line is connected to the k+1th gate line through the fourth via hole connection structure connected. 24. The array substrate according to claim 21, wherein the array substrate further comprises at least one intermediate vertical gate line located between two adjacent sub-pixel columns, In the (k+1)/2th gridline group, the kth gridline and the k+1th gridline are connected through the middle vertical gridline. 25. The array substrate according to claim 24, wherein the middle vertical gate line is arranged in the same layer as the gate line. 26. The array substrate according to claim 24, further comprising: a first common electrode line extending along the first direction; and a second common electrode line extending along the second direction, Wherein, each of the sub-pixel units includes a first area and a second area arranged in sequence along the second direction, the pixel electrode is located in the first area, the driving transistor is located in the second area, and the first The common electrode line is located between two adjacent sub-pixel units in the second direction, and between the first region and the second region of the same sub-pixel unit, The second common electrode line is located between two adjacent sub-pixel columns. 27. The array substrate according to claim 26, wherein the first common electrode line is provided on the same layer as the gate line, the first common electrode line includes at least one first notch and is located in the first notch the first sub-common electrode lines on both sides, The middle vertical gate lines pass through the first gaps and are spaced and insulated from the first sub-common electrode lines respectively. 28. The array substrate according to claim 26, wherein the second common electrode lines include gate layer common electrode lines and data line layer common electrode lines, and the gate layer common electrode lines are arranged on the same layer as the gate lines The common electrode line of the data line layer is arranged on the same layer as the data line, and the common electrode line of the gate layer is connected to the common electrode line of the data line layer through a fifth via connection structure. 29. The array substrate according to claim 26, wherein the two first common electrode lines are arranged on the kth gate line and the k+1th gate line in the (k+1)/2th gate line group between the two grid lines, and respectively include the first gap, the middle vertical grid line passes through the two first gaps of the two first common electrode lines so as to connect the k-th grid line The gate line is connected to the k+1th gate line. 30. The array substrate according to claim 26, wherein, The width of the part of the second common electrode line located in the first region is greater than the width of the part of the second common electrode line located in the second region. 31. The array substrate according to claim 26, wherein the second common electrode line is located between the 1st sub-pixel column and the 1+1th sub-pixel column, and the second common electrode line The distance between the line and the signal line corresponding to the lth sub-pixel column is equal to the distance between the second common electrode line and the data line corresponding to the l+1th sub-pixel column , or, the distance between the second common electrode line and the data line corresponding to the lth sub-pixel column is the same as the distance between the second common electrode line and the l+1th sub-pixel column The distances between the signal lines are equal, and l is a positive integer greater than or equal to 1. 32. The array substrate according to any one of claims 1-7, wherein, Each of the sub-pixel units includes a first area and a second area arranged in sequence along the second direction, the pixel electrode is located in the first area, and the driving transistor is located in the second area, The distance between the portion of the data line in the first area and the portion of the signal line in the first area in the first direction is smaller than the portion of the data line in the second area and the portion of the signal line in the first area. the distance in the first direction of the part of the signal line in the second area, The data line includes a first oblique connection portion connecting the part of the data line in the first area with the part of the data line in the second area, the signal line includes a second oblique connection portion, Connecting the part of the signal line in the first area and the part of the signal line in the second area. 33. The array substrate according to claim 21, further comprising: A plurality of gate lead-out lines, each gate lead-out line is located between two adjacent sub-pixel columns, Wherein, each of the gate lead-out lines includes: The first gate lead-out line is arranged on the same layer as the data line, and is configured to connect to a gate signal; The second gate lead-out line is arranged on the same layer as the gate line, and is configured to be connected to the corresponding gate line, Wherein, the first gate lead-out line and the second gate lead-out line are connected through a fifth via structure. 34. The array substrate according to claim 33, wherein the gate lead-out line is configured to be electrically connected to the (m+1)/2th gate line group, and the second gate lead-out line is connected to the The mth gate line is directly connected, m is an odd number greater than or equal to 1, The m-1th gate line includes a second gap, and the three first common electrode lines are arranged between the m-th gate line and the m-2th gate line, and each includes a second gap. A gap, the second gate lead-out line passes through the second gap of the m-1th gate line and the three first gaps of the three first common electrode lines, and extends to the Describe the location of the sixth via connection structure, The sixth via connection structure is located between the m-2th gate line and the first common electrode line, and the first gate lead-out line is connected to the first gate line through the sixth via connection structure. The two grid lead wires are connected. 35. The array substrate according to claim 26, further comprising: The shielding electrode is located on the base substrate and is arranged on the same layer as the gate line. 36. The array substrate according to claim 35, wherein the orthographic projection of the shielding electrode on the base substrate is located between the orthographic projection of the second common electrode line on the base substrate and the data between the orthographic projections of the lines on the base substrate, and between the orthographic projections of the second common electrode lines on the base substrate and the orthographic projections of the signal lines on the base substrate. 37. The array substrate according to claim 36, wherein the orthographic projection of the shielding electrode on the base substrate is also located between the orthographic projection of the data line on the base substrate and the signal line on the base substrate. between the orthographic projections on the substrate substrate. 38. A display device, comprising the array substrate according to any one of claims 1-37.

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