CN115549724B - Chip synchronization and frequency estimation method and system for direct sequence spread spectrum signals - Google Patents
Chip synchronization and frequency estimation method and system for direct sequence spread spectrum signals Download PDFInfo
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- H04B1/707—Spread spectrum techniques using direct sequence modulation
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Abstract
The invention discloses a method and a system for chip synchronization and frequency estimation of a direct sequence spread spectrum signal, wherein the method comprises the following steps: s1: calculating conjugate product results of N B branches of the intermediate frequency data; s2: despreading the conjugate product results of the N B branches by utilizing FFT to obtain integral results of the N B branches; s3: conjugate multiplication is carried out on the integral results of the adjacent branches to obtain (N B -1) integral conjugate product results; s4: accumulating and summing (N B -1) integral conjugate product results to obtain an integral accumulation sum; s5: the peak value of the integral accumulation sum is obtained and compared with a preset threshold value; s6: and successfully acquiring the position corresponding to the peak value as the chip synchronization position of the spread spectrum signal by synchronization, and estimating the frequency of the signal by using the peak value phase. The method and the system can carry out chip synchronization and frequency estimation on the direct sequence spread spectrum signal, and simultaneously have the characteristics of low calculation complexity and high synchronization precision.
Description
Technical Field
The present invention relates to the field of spread spectrum communications, and in particular, to a method and system for chip synchronization and frequency estimation of a direct sequence spread spectrum signal.
Background
The spread spectrum receiver firstly performs chip synchronization on the received spread spectrum signal, and then performs operations such as frequency estimation, chip and frequency fine estimation, data demodulation and the like after the synchronization is successful. With the increasing complexity of the application environment of the receiver, the low power consumption of the receiver requires the low computational complexity of the chip synchronization process of the receiver, the chip synchronization precision is high and the synchronization speed is high; the low cost of the receiver requires low device cost so that the synchronization process must have the capability to process large frequency offset signals.
The code chip synchronization process of the spread spectrum receiver needs two-dimensional synchronization of the signal code phase and the carrier frequency, and the traditional synchronization method has time domain synchronization, namely the code phase and the carrier frequency adopt a serial synchronization method, and the method has small calculated amount but long synchronization time and cannot meet the low power consumption requirement of the receiver; the frequency domain parallel synchronization comprises two methods of code phase parallel, carrier frequency serial, code phase serial and carrier frequency parallel, and when the spread spectrum sequence is longer and the signal frequency offset is larger, the calculated amount of the frequency domain parallel synchronization is too large, and the low power consumption requirement of the receiver cannot be met.
The foregoing background is only for the purpose of facilitating an understanding of the principles and concepts of the application and is not necessarily in the prior art to the present application and is not intended to be used as an admission that such background is not entitled to antedate such novelty and creativity by virtue of prior application or that it is already disclosed at the date of filing of this application.
Disclosure of Invention
The invention aims at providing a method and a system suitable for chip synchronization and frequency estimation of a direct sequence spread spectrum signal, which can perform chip synchronization and frequency estimation on the direct sequence spread spectrum signal and have the characteristics of low calculation complexity and high synchronization precision.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
An embodiment of the invention discloses a method suitable for direct sequence spread spectrum signal chip synchronization and frequency estimation, which is characterized by comprising the following steps:
S1: calculating the product of the received intermediate frequency data and the delayed branch thereof after conjugation to obtain the conjugation product result of N B branches; wherein N B is the number of delay branches;
S2: despreading the conjugate product results of the N B branches by utilizing FFT to obtain integral results of the N B branches;
s3: conjugate multiplication is carried out on the integral results of the adjacent branches to obtain (N B -1) integral conjugate product results;
S4: accumulating and summing the (N B -1) integral conjugate product results to obtain an integral accumulation sum;
S5: acquiring the peak value of the integral accumulation sum, comparing the peak value with a preset threshold value, judging that the synchronization is successful if the peak value is larger than the preset threshold value, and judging that the synchronization is failed if the peak value is smaller than the preset threshold value;
S6: and after the synchronization is successful, acquiring the position corresponding to the peak value as the chip synchronization position of the spread spectrum signal, and estimating the frequency of the signal by using the peak value phase.
Preferably, step S1 specifically includes:
S11: initializing a synchronization control parameter, a spreading sequence length N C and a memory for storing the conjugate product results of N B branches;
S12: receiving intermediate frequency data, and caching data with 2 symbol lengths, wherein the data length of 1 symbol is the length N C of a spread spectrum sequence;
s13: acquiring branch data and branch delay data from the buffer medium frequency data;
S14: conjugation of branch delay data is taken and multiplied with the branch data, the product result is circularly shifted to the right to obtain the calculation result of the conjugate product of the branch, the calculation result of the conjugate product of the branch and the conjugate product result of the branch in a memory are accumulated and summed, and finally the accumulated sum is written into the memory;
S15: repeating the step S13 and the step S14 until all branch calculation is completed, and storing conjugate product results of N B branches in a memory;
S16: updating the cache data, and repeating the steps S13-S15 until updating of all symbol data is completed;
Preferably, the synchronization control parameters in step S11 include a delay chip interval, a delay branch number, a symbol number, a delay branch count, and a symbol count, where the values of the delay chip interval and the delay branch number are chosen to ensure that the product of the delay chip interval and the delay branch number is smaller than the length of the spreading sequence.
Preferably, updating the cache data in step S16 specifically includes: and moving the intermediate frequency data corresponding to the 2 nd symbol in the buffer memory to the 1 st symbol position, receiving new intermediate frequency data and buffering the new intermediate frequency data to the 2 nd symbol position, and completing the receiving of N C intermediate frequency data to complete the data updating of 1 symbol.
Preferably, step S2 specifically includes:
S21: reading the conjugate product result of the branch from the memory, performing FFT conversion on the result, and then taking conjugate;
S22: taking the conjugate of the delay spread spectrum sequence and the spread spectrum sequence to carry out product, and carrying out FFT conversion on the product;
s23: multiplying the conjugation result obtained in the step S21 by the FFT conversion result obtained in the step S22, carrying out FFT conversion on the product result, and taking the conjugation of the FFT conversion result as the integral result of the branch;
S24: and repeatedly executing the steps S21, S22 and S23, writing the integration result obtained in the step S23 into a memory, and storing the integration results of N B branches in the memory until the calculation of all branches is completed.
Preferably, in step S6, the peak phase is specifically an integral accumulation sum corresponding to the peak, and the phase of the integral accumulation sum is calculated, and the frequency of the signal is estimated using the phase information.
Another embodiment of the present invention discloses a system for chip synchronization and frequency estimation of a direct sequence spread spectrum signal, which is characterized by comprising an intermediate frequency data buffer module, a synchronization control module, a memory module, a calculation branch conjugate product module, a spread spectrum sequence processing module, a calculation branch integral module, a calculation integral accumulation sum module and a calculation synchronization result module, wherein:
the intermediate frequency data buffer module receives the intermediate frequency data after down-conversion, and updates the intermediate frequency data of the intermediate frequency data buffer module according to the update buffer data signal given by the synchronous control module, and updates the intermediate frequency data with the length of 1 symbol each time;
The synchronous control module gives out a calculation control signal, a branch count value and an update cache data signal according to the delay chip interval, the delay branch number, the symbol number, the delay branch count and the symbol count;
the memory module finishes reading and writing calculation to obtain a branch conjugate product result or a calculated branch integral result;
The branch conjugate product calculating module obtains branch data and branch delay data from the intermediate frequency data buffer module according to the calculation control signal and the branch count value given by the synchronous control module, and completes conjugate multiplication calculation; acquiring data stored in the branch from the memory module, accumulating and summing the data and the conjugate product result after cyclic shift, and writing the accumulated and summed result into a memory;
The spread spectrum sequence processing module completes new generation of a spread spectrum sequence according to the calculation control signal and the branch count value given by the synchronous control module and sends the new generation of the spread spectrum sequence to the calculation branch integration module;
The calculation branch integral module reads the conjugate product result of the branch from the memory module according to the calculation control signal and the branch count value given by the synchronous control module, completes integral calculation of the branch together with the new spread spectrum sequence given by the spread spectrum sequence processing module, and writes the result of integral calculation into the memory;
The calculation integral accumulation sum module reads branch integral results in a memory from the memory module, completes calculation of integral conjugate product results and calculation of integral accumulation sums, and sends the integral accumulation sums to the calculation synchronous result module;
The module for calculating the synchronization result obtains a peak value according to the integral accumulation sum, judges whether the signals are synchronized by utilizing the peak value, and calculates the chip synchronization position and the frequency of the received signals again if the signals are judged to be synchronized.
Compared with the prior art, the invention has the following advantages:
1. The invention realizes the chip synchronization and the frequency parallel estimation of the spread spectrum signal, greatly reduces the frequency of using FFT conversion, reduces the calculation complexity and can meet the design requirement of the spread spectrum receiver with increasingly complex application environment.
2. The invention can support the synchronization of spread spectrum signals with different intensities and the synchronization of spread spectrum signals with large frequency offset by adjusting the delay chip interval, the delay branch number and the symbol number.
Drawings
Fig. 1 is a flow chart of a method of chip synchronization and frequency estimation suitable for direct sequence spread spectrum signals in accordance with a preferred embodiment of the present invention;
FIG. 2 is a flow chart of a module for calculating a branch conjugate product in accordance with an embodiment of the present invention;
FIG. 3 is a flow chart of a calculation branch integration module according to an embodiment of the present invention;
Fig. 4 is a block diagram of a chip synchronization and frequency estimation system suitable for direct sequence spread spectrum signals in accordance with another preferred embodiment of the present invention.
Detailed Description
The following describes embodiments of the present invention in detail; it should be emphasized that the following description is merely exemplary in nature and is in no way intended to limit the scope of the invention or its applications.
The invention will be further described with reference to the following drawings in conjunction with the preferred embodiments.
As shown in fig. 1, the preferred embodiment of the present invention discloses a method for chip synchronization and frequency estimation of a direct sequence spread spectrum signal, comprising the steps of:
s1: calculating the product of the received intermediate frequency data and the delayed branches thereof after conjugation to obtain conjugate product results of N B branches, wherein N B is the number of the delayed branches;
As shown in fig. 2, step S1 specifically includes:
S11: initializing a synchronization control parameter, a spread spectrum sequence length N C and a memory for storing N B branch conjugate product results; wherein the synchronization control parameters include: delay chip interval τ D, delay branch number N B, symbol number N S, delay branch count N b, and symbol count N s; the values of the delay chip interval τ D and the delay branch number N B should ensure N B*τD＜NC; wherein N b is 1,2, 3.n B,ns is 1,2, 3.n S;
S12: receiving intermediate frequency data, and caching data with 2 symbol lengths, wherein the data length of 1 symbol is the length N C of a spread spectrum sequence;
Particularly, when in first buffering, the S pos is used as a starting position to directly receive intermediate frequency data with the length of 2 symbols; updating the buffer again, taking S pos+NC as a starting position, moving data with the length of N C to the position of the starting position S pos in the buffer, receiving new intermediate frequency data, and buffering the new intermediate frequency data to the position of the starting position S pos+NC, wherein the data updating of 1 symbol is completed after the reception of N C intermediate frequency data is completed;
S13: acquiring data with the length of N C as N b branch data D nb from a cache position S pos+nb*τD, and acquiring delay data D nb_d with the length of N C as N b branch from a cache position S pos;
S14: taking the conjugate D nb_d of the branch delay data D nb_d, multiplying the conjugate D nb_d by the branch data D nb, and circularly shifting the product result D nb_d**Dnb to the right (N b-1)*τD times to obtain the result of the conjugate of the nth branch b;
S15: repeating the step S13 and the step S14 until the step is finished after N b＝NB, and storing conjugate product results of N B branches in a memory;
S16: updating the cache data, initializing the delay branch count N b again, and repeating the steps S13-S15 until the updating of the data of N S symbols is completed.
S2: despreading the conjugate product results of the N B branches by utilizing FFT (Fast Fourier Transform ) to obtain integral results of the N B branches;
as shown in fig. 3, step S2 specifically includes:
S21: reading N C conjugate product results from the position (N b-1)*NC +1) of the memory, wherein the result is a conjugate product result Rst nb (N) of an nth b branch, performing FFT conversion on Rst nb (N), and then taking conjugate, wherein the result is Wherein N has the value of [1,2,3, ], N C;
S22: the spreading sequence c (N) with the length of N C is circularly shifted to the right by N b*τD times to obtain a delay spreading sequence c d (N) with the N b branch, the conjugation c d(n)* of the delay spreading sequence is taken, the conjugation result of the delay spreading sequence is multiplied by the spreading sequence, the multiplication result c (N) c d(n)* is a new spreading sequence with the N b branch, the new spreading sequence is subjected to FFT conversion, and the result is that
S23: multiplying the conjugate result H (k) obtained in the step S21 by the FFT conversion result C (k) obtained in the step S22, carrying out FFT conversion on the product result, and taking the integral result of the conjugate of the FFT conversion result as the n b branch as
S24: repeating the steps S21, S22 and S23, writing the branch integration result obtained in the step S23 into a memory, wherein the writing position is (N b-1)*NC +1), and the memory stores the integration results of N B branches until the execution is completed when N b＝NB is completed.
S3: conjugate multiplication is carried out on the integral results of the adjacent branches to obtain (N B -1) integral conjugate product results Rconj nb(n)＝Rcohnb(n)**Rcohnb+1 (N);
S4: the (N B -1) integral conjugate product results are accumulated and summed to obtain an integral accumulated sum
S5: obtaining peak=max (abs (Rsum (n))) of the integral accumulation sum, comparing with a threshold value, and judging that the synchronization is successful if the peak=max is larger than the threshold value; if the synchronization failure is smaller than the threshold value, judging that the synchronization fails;
S6: after the synchronization is successful, the position corresponding to the peak value peak is obtained as the synchronization position of the spread spectrum chip, and then the frequency of the peak phase estimation signal is used, wherein the integral accumulation sum corresponding to the peak value peak is Its phase is/>Thus estimating the frequency of the signal as/>F c is the spreading code rate.
As shown in fig. 4, a block diagram of a chip synchronization and frequency estimation system suitable for direct sequence spread spectrum signals according to another preferred embodiment of the present invention includes an intermediate frequency data buffer module 10, a synchronization control module 20, a memory module 30, a calculation branch conjugate product module 40, a spread spectrum sequence processing module 50, a calculation branch integration module 60, a calculation integration accumulation sum module 70, and a calculation synchronization result module 80, wherein:
the intermediate frequency data buffer module 10 receives the intermediate frequency data after down-conversion, and updates the intermediate frequency data of the intermediate frequency data buffer module according to the update buffer data signal given by the synchronous control module 20, and updates the intermediate frequency data with the length of 1 symbol each time;
the synchronization control module 20 gives a calculation control signal, a branch count value and an update buffer data signal according to the delay chip interval, the delay branch number, the symbol number, the delay branch count and the symbol count;
the memory module 30 finishes the reading and writing calculation to obtain a branch conjugate product result or a calculated branch integral result;
The branch conjugate product calculating module 40 obtains branch data and branch delay data from the intermediate frequency data buffer module 10 according to the calculation control signal and the branch count value given by the synchronous control module 20, and completes conjugate multiplication calculation; the data stored in the branch is obtained from the memory module 30 and added with the result of the conjugate product after cyclic shift, and the added result is written into the memory;
The spreading sequence processing module 50 completes the generation of a new spreading sequence according to the calculation control signal and the branch count value given by the synchronous control module 20 and sends the new spreading sequence to the calculation branch integration module 60;
The calculation branch integration module 60 reads the conjugate product result of the branch from the memory module 30 according to the calculation control signal and the branch count value given by the synchronous control module 20, completes the integration calculation of the branch together with the new spread spectrum sequence given by the spread spectrum sequence processing module 50, and writes the result calculation of the integration calculation into the memory;
The calculation integral accumulation and sum module 70 reads the branch integral result in the memory from the memory module 30, completes the calculation of the integral conjugate product and the calculation of the integral accumulation and sum, and sends the integral accumulation and sum to the calculation synchronization result module 80;
the module 80 obtains peak value according to the integral accumulation sum, judges whether to synchronize by using the peak value, and recalculates the chip synchronization position and frequency of the received signal if judging to synchronize;
the method can be suitable for the synchronization and frequency estimation of spread spectrum signal chips with different spread spectrum sequence lengths, greatly reduces the invoking times of FFT and reduces the calculated amount of the synchronization process; the synchronization of spread spectrum signals with different signal strengths is realized by adjusting the synchronization control parameters, and the method has the characteristics of high synchronization precision, low calculation complexity and flexible parameter configuration, and has certain universality.
The background section of the present invention may contain background information about the problem or environment of the present invention rather than the prior art described by others. Accordingly, inclusion in the background section is not an admission of prior art by the applicant.
The foregoing is a further detailed description of the invention in connection with specific/preferred embodiments, and it is not intended that the invention be limited to such description. It will be apparent to those skilled in the art that several alternatives or modifications can be made to the described embodiments without departing from the spirit of the invention, and these alternatives or modifications should be considered to be within the scope of the invention. In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "preferred embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction. Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope as defined by the appended claims.
Claims (6)
1. A method for chip synchronization and frequency estimation for a direct sequence spread spectrum signal, comprising the steps of:
S1: calculating the product of the received intermediate frequency data and the branch delay data of the delay branch thereof after conjugation to obtain the conjugation product result of N B branches; wherein N B is the number of delay branches;
S2: despreading the conjugate product results of the N B branches by utilizing FFT to obtain integral results of the N B branches;
s3: conjugate multiplication is carried out on the integral results of the adjacent branches to obtain (N B -1) integral conjugate product results;
S4: accumulating and summing the (N B -1) integral conjugate products to obtain an integral accumulation sum;
S5: acquiring the peak value of the integral accumulation sum, comparing the peak value with a preset threshold value, judging that the synchronization is successful if the peak value is larger than the preset threshold value, and judging that the synchronization is failed if the peak value is smaller than the preset threshold value;
S6: after successful synchronization, acquiring the position corresponding to the peak value as the chip synchronization position of the spread spectrum signal, and estimating the frequency of the signal by using the peak value phase;
The step S2 specifically includes:
s21: reading the conjugate product result of the branch from the memory, performing FFT conversion on the result, and then taking conjugate;
S22: taking the conjugate of the delay spread spectrum sequence and the spread spectrum sequence to carry out product, and carrying out FFT conversion on the product;
s23: multiplying the conjugation result obtained in the step S21 by the FFT conversion result obtained in the step S22, carrying out FFT conversion on the product result, and taking the conjugation of the FFT conversion result as the integral result of the branch;
S24: and repeatedly executing the steps S21, S22 and S23, writing the integration result obtained in the step S23 into a memory, and storing the integration results of N B branches in the memory until the calculation of all branches is completed.
2. The method for chip synchronization and frequency estimation according to claim 1, wherein step S1 specifically comprises:
S11: initializing a synchronization control parameter, a spreading sequence length N C and a memory for storing the conjugate product results of N B branches;
S12: receiving intermediate frequency data, and caching data with 2 symbol lengths, wherein the data length of 1 symbol is the length N C of a spread spectrum sequence;
s13: acquiring branch data and branch delay data from the buffer medium frequency data;
S14: conjugation of branch delay data is taken and multiplied by the branch data, the product result is circularly shifted to the right to obtain the result of the calculation of the conjugate product of the branch, the result of the calculation of the conjugate product of the branch and the result of the conjugate product of the branch in a memory are accumulated and summed, and finally the accumulated sum is written into the memory;
S15: repeating the step S13 and the step S14 until all branch calculation is completed, and storing conjugate product results of N B branches in a memory;
s16: updating the cache data, and repeating the steps S13-S15 until the updating of all symbol data is completed.
3. The method according to claim 2, wherein the synchronization control parameters in step S11 include a delay chip interval, a delay branch number, a symbol number, a delay branch count, and a symbol count, and the values of the delay chip interval and the delay branch number are such that the product of the delay chip interval and the delay branch number is smaller than the spreading sequence length.
4. The method for chip synchronization and frequency estimation according to claim 2, wherein updating the buffered data in step S16 specifically comprises: and moving the intermediate frequency data corresponding to the 2 nd symbol in the buffer memory to the 1 st symbol position, receiving new intermediate frequency data and buffering the new intermediate frequency data to the 2 nd symbol position, and completing the receiving of N C intermediate frequency data to complete the data updating of 1 symbol.
5. The method of claim 1, wherein in step S6, the peak phase is specifically obtained by obtaining an integral sum corresponding to the peak, and calculating the phase of the integral sum, and estimating the frequency of the signal using the phase.
6. The chip synchronization and frequency estimation system suitable for the direct sequence spread spectrum signal is characterized by comprising an intermediate frequency data buffer module, a synchronization control module, a memory module, a calculation branch conjugate product module, a spread spectrum sequence processing module, a calculation branch integral module, a calculation integral accumulation sum module and a calculation synchronization result module, wherein:
the intermediate frequency data buffer module receives the intermediate frequency data after down-conversion, and updates the intermediate frequency data of the intermediate frequency data buffer module according to the update buffer data signal given by the synchronous control module, and updates the intermediate frequency data with the length of 1 symbol each time;
The synchronous control module gives out a calculation control signal, a branch count value and an update cache data signal according to the delay chip interval, the delay branch number, the symbol number, the delay branch count and the symbol count;
the memory module is used for storing the branch conjugate product result calculated by the calculation score conjugate product module and the branch integral result calculated by the calculation branch integral module;
The branch conjugate product calculating module obtains branch data and branch delay data from the intermediate frequency data buffer module according to the calculation control signal and the branch count value given by the synchronous control module, and completes conjugate multiplication calculation; acquiring data stored in the branch from the memory module, accumulating and summing the data and the conjugate product result after cyclic shift, and writing the accumulated and summed result into a memory;
The spread spectrum sequence processing module completes new generation of a spread spectrum sequence according to the calculation control signal and the branch count value given by the synchronous control module and sends the new generation of the spread spectrum sequence to the calculation branch integration module;
The calculation branch integral module reads the conjugate product result of the branch from the memory module according to the calculation control signal and the branch count value given by the synchronous control module, completes integral calculation of the branch together with the new spread spectrum sequence given by the spread spectrum sequence processing module, and writes the result of integral calculation into the memory;
The integral accumulation sum calculating module reads the integral result in the memory from the memory module, completes the calculation of integral conjugate product and the calculation of integral accumulation sum, and sends the integral accumulation sum to the calculation synchronization result module;
The module for calculating the synchronization result obtains a peak value according to the integral accumulation sum, judges whether the signals are synchronized by utilizing the peak value, and calculates the chip synchronization position and the frequency of the received signals again if the signals are judged to be synchronized.
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| CN103645483A (en) * | 2013-12-09 | 2014-03-19 | 西安电子科技大学昆山创新研究院 | Beidou signal capturing method in weak signal environment |
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| US7826493B2 (en) * | 2001-08-27 | 2010-11-02 | Broadcom Corp. | Frequency offset correction circuit for WCDMA |
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| CN103645483A (en) * | 2013-12-09 | 2014-03-19 | 西安电子科技大学昆山创新研究院 | Beidou signal capturing method in weak signal environment |
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