CN115549708B - Receiver with phase noise optimization function and wireless communication system - Google Patents
Receiver with phase noise optimization function and wireless communication system Download PDFInfo
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- CN115549708B CN115549708B CN202211502739.3A CN202211502739A CN115549708B CN 115549708 B CN115549708 B CN 115549708B CN 202211502739 A CN202211502739 A CN 202211502739A CN 115549708 B CN115549708 B CN 115549708B
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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- H04B1/26—Circuits for superheterodyne receivers
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The application relates to a receiver with a phase noise optimization function and a wireless communication system, which relate to the technical field of receivers and comprise a frequency division unit, a digital logic unit, a D trigger, a frequency mixer and a clock signal input unit, wherein the clock signal input end of the frequency division unit is connected to the clock signal input unit, the output end of the frequency division unit is connected to the digital logic unit, the output end of the digital logic unit is connected to the data input end of the D trigger, the clock signal input end of the D trigger is connected to the clock signal input unit, and the output end of the D trigger is connected to the frequency mixer; through the digital logic unit, a signal transmission path is shortened, the delay time of local oscillator signal transmission is reduced, a controllable re-timing function can be still realized under a high-speed signal, the processing capacity of phase noise of the receiver is obviously improved on the premise of keeping power consumption, and the communication quality of the receiver is improved.
Description
Technical Field
The present application relates to the field of receiver technologies, and in particular, to a receiver and a wireless communication system having a function of optimizing phase noise.
Background
In a wireless communication system, a receiver is an essential part, the receiver mainly comprises an antenna, a low noise amplifier, a frequency synthesizer, a mixer and a demodulator, a radio frequency signal directly received from the antenna is difficult to directly process, the frequency synthesizer in the receiver can generate a local oscillation signal and transmit the local oscillation signal to the mixer, so that the frequency reduction processing of the radio frequency signal is realized, for example, the radio frequency signal at 5GHz is converted into the radio frequency signal at 500MHZ, and the radio frequency signal is easy to further process in a low frequency state.
With the progress of wireless communication systems, data transmission rates are higher and higher, and in order to improve the communication quality of receivers, higher requirements are put on the purity of local oscillation signals, which require that the local oscillation signals have lower phase noise. However, in the process of transmitting the local oscillation signal, with the increase of devices on the transmission path, the change of the signal level at the zero crossing point is increased, so that the phase noise is increased, and the communication quality is affected.
Disclosure of Invention
In order to reduce phase noise and improve communication quality, the application provides a receiver with a phase noise optimizing function and a wireless communication system.
In a first aspect, the present application provides a receiver with a phase noise optimization function, which adopts the following technical solutions:
a receiver with phase noise optimization function comprises a frequency division unit, a digital logic unit, a D trigger, a mixer and a clock signal input unit, wherein a clock signal input end of the frequency division unit is connected to the clock signal input unit, an output end of the frequency division unit is connected to the digital logic unit, an output end of the digital logic unit is connected to a data input end of the D trigger, a clock signal input end of the D trigger is connected to the clock signal input unit, and an output end of the D trigger is connected to the mixer;
the clock signal input unit is used for generating a local oscillation signal and inputting the local oscillation signal to the frequency division unit and the D trigger;
the frequency division unit is used for receiving the local oscillation signal and performing frequency division on the local oscillation signal for multiple times to obtain a frequency division signal;
the digital logic unit is used for receiving the frequency division signal and generating a retiming signal according to the frequency division signal;
the D trigger is used for delaying and inputting the retiming signal into the frequency mixer according to the local oscillation signal;
the mixer is configured to perform frequency conversion processing on the received retiming signal and the antenna signal, generate an antenna signal to be processed, and send the antenna signal to be processed to a demodulator.
By adopting the technical scheme, the frequency division unit divides the frequency of the clock signal input by the clock signal input unit for multiple times to obtain a frequency division signal, the frequency division signal is input to the digital logic unit, the digital logic unit generates a retiming signal according to the frequency division signal, and the retiming signal only passes through the one-time frequency division and the digital logic unit of the frequency division unit, so that the delay time is shortened, the processing effect of phase noise is improved, and the communication quality of the receiver is improved.
Optionally, the frequency dividing unit includes a multi-modulus frequency divider, an input end of the multi-modulus frequency divider is connected to the clock signal input unit, and a first signal output end of the multi-modulus frequency divider is connected to the first input end of the digital logic unit.
By adopting the technical scheme, the multi-mode frequency divider can perform programmable frequency division on the frequency of the local oscillation signal to obtain a frequency division signal, and the frequency division signal and the antenna signal are mixed to reduce the frequency of the antenna signal, so that the communication quality is improved.
Optionally, the frequency dividing unit further includes a digital frequency divider, an input end of the digital frequency divider is connected to the second signal output end of the multi-modulus frequency divider, and a first signal output end of the digital frequency divider is connected to the second input end of the digital logic unit;
the multi-modulus frequency divider outputs a first frequency-divided signal, the digital frequency divider outputs a second frequency-divided signal, and the frequency of the first frequency-divided signal is greater than the frequency of the second frequency-divided signal.
By adopting the technical scheme, the first frequency division signal is subjected to frequency division through the digital frequency divider to obtain the second frequency division signal, so that the frequency range of the first frequency division signal is wider, the frequency of the antenna signal is lower, the antenna signal is more conveniently processed, and the communication quality is improved.
Optionally, the multi-modulus frequency divider includes a plurality of 2/3 frequency dividers connected in series in sequence, an input end of the first stage of the 2/3 frequency divider is connected to the clock signal input unit, an output end of the first stage of the 2/3 frequency divider is connected to a first signal output end of the multi-modulus frequency divider, and an output end of the last stage of the 2/3 frequency divider is connected to a second signal output end of the multi-modulus frequency divider.
By adopting the technical scheme, the programmable frequency division can be carried out on the local oscillator signal by connecting the plurality of 2/3 frequency dividers in series to achieve the expected frequency division signal, and meanwhile, the frequency division ratio can be controlled by the 2/3 frequency dividers to obtain the frequency division signal with low phase noise, thereby improving the communication quality.
Optionally, the control terminals of the plurality of 2/3 frequency dividers are all connected to the second signal output terminal of the digital frequency divider;
the digital frequency divider is used for controlling the frequency dividing ratio of a plurality of the 2/3 frequency dividers.
By adopting the technical scheme, the digital frequency divider controls the frequency dividing ratio of the 2/3 frequency divider according to the first frequency dividing signal, so that the frequency dividing ratio of the 2/3 frequency divider is more accurate, and the possibility of errors is reduced.
Optionally, the digital logic unit includes a first nand gate and a second nand gate, a first signal input of the first nand gate is connected to a first signal output of the digital frequency divider, a second signal input of the first nand gate is connected to a signal output of the second nand gate, an output of the first nand gate is connected to a first signal input of the second nand gate, a second signal input of the second nand gate is connected to a first signal output of the multi-modulus frequency divider, and an output of the second nand gate is connected to the data input of the D flip-flop.
By adopting the technical scheme, the digital logic unit can generate the retiming signal through the first frequency division signal and the second frequency division signal, so that the frequencies of the retiming signal and the second frequency division signal are consistent, and meanwhile, the rising edge transmission path of the retiming signal only passes through the first-stage 2/3 frequency divider and one NAND gate, so that the delay time is shortened, the processing effect of phase noise is improved, and the communication quality is improved.
Optionally, the clock signal input unit includes a frequency synthesizer, and an output end of the frequency synthesizer is connected to the clock signal input end of the frequency dividing unit and the clock signal input end of the D flip-flop respectively;
the frequency synthesizer is used for providing local oscillation signals and transmitting the local oscillation signals to the frequency division unit and the D trigger.
By adopting the technical scheme, the frequency synthesizer generates the local oscillation signal and transmits the local oscillation signal to the D trigger and the frequency division unit, so that the frequency division unit and the D trigger adopt the same local oscillation signal, the clocks of the D trigger and the frequency division unit are kept synchronous, and phase noise is more conveniently processed.
In a second aspect, the present application provides a wireless communication system, which adopts the following technical solutions:
a wireless communication system comprising a transmitter and a receiver having a phase noise optimization function as claimed in any one of the first aspect.
By adopting the technical scheme, the frequency division unit divides the frequency of the clock signal input by the clock signal input unit for multiple times to obtain a frequency division signal, the frequency division signal is input to the digital logic unit, the digital logic unit generates a retiming signal according to the frequency division signal, and the retiming signal only passes through the one-time frequency division and the digital logic unit of the frequency division unit, so that the delay time is shortened, the processing effect of phase noise is improved, and the communication quality of the receiver is improved.
In summary, the present application includes at least one of the following beneficial technical effects:
1. the frequency dividing unit divides the clock signal input by the clock signal input unit for multiple times to obtain a frequency dividing signal, and inputs the frequency dividing signal to the digital logic unit;
2. the digital logic unit can generate a retiming signal through the first frequency division signal and the second frequency division signal, so that the frequencies of the retiming signal and the second frequency division signal are consistent, and meanwhile, a rising edge transmission path of the retiming signal only passes through the first-stage 2/3 frequency divider and one NAND gate, so that the delay time is shortened, the processing effect of phase noise is improved, and the communication quality is improved.
Drawings
Fig. 1 is a block diagram of the structure of an embodiment of the present application.
Fig. 2 is a circuit schematic of a 2/3 frequency divider of an embodiment of the present application.
Fig. 3 is a timing diagram of the 2/3 divider.
Fig. 4 is a diagram of zero crossing and phase noise.
Fig. 5 is a schematic diagram of a digital logic cell of an embodiment of the present application.
Description of reference numerals: 1. a frequency dividing unit; 11. a multi-modulus frequency divider; 12. a digital frequency divider; 2. a digital logic unit; 3. a D flip-flop; 4. a mixer; 5. a clock signal input unit; 6. an antenna; 7. a low noise amplifier; 8. a demodulator; 9. a signal processing unit.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below with reference to fig. 1-5 and the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The embodiment of the application discloses a receiver with a phase noise optimization function. Referring to fig. 1, the receiver with a phase noise optimization function includes an antenna 6, a low noise amplifier 7, a mixer 4, a demodulator 8, and a signal processing unit 9; the output of antenna 6 is connected in low noise amplifier 7's input, and low noise amplifier 7's output is connected in the first input of mixer 4, and the output of mixer 4 is connected in demodulator 8, and the output of demodulator 8 is connected in signal processing unit 9's input, and signal processing unit 9's output is connected in outside host computer.
In this embodiment, the receiver with the phase noise optimization function further includes a frequency dividing unit 1, a digital logic unit 2, a D flip-flop 3, and a clock signal input unit 5; the output end of the clock signal input unit 5 is connected to the input end of the frequency dividing unit 1 and the clock signal input end of the D flip-flop 3 respectively, the output end of the frequency dividing unit 1 is connected to the input end of the digital logic unit 2, the output end of the digital logic unit 2 is connected to the data input end of the D flip-flop 3, and the output end of the D flip-flop 3 is connected to the mixer 4.
The antenna 6 is used for receiving the antenna 6 signal and transmitting the signal into the low noise amplifier 7;
the low noise amplifier 7 is used for receiving the antenna 6 signal, amplifying the antenna 6 signal to obtain an amplified antenna 6 signal, and then transmitting the amplified antenna 6 signal to the mixer 4;
the clock signal input unit 5 is used for generating a local oscillation signal and transmitting the local oscillation signal to the frequency divider and the D trigger 3;
the frequency divider is used for receiving the local oscillation signal and dividing the frequency of the local oscillation signal to obtain a frequency division signal;
the digital logic unit 2 is used for receiving the frequency division signal, generating a retiming signal according to the frequency division signal, and inputting the retiming signal into the D flip-flop 3;
the D trigger 3 is used for delaying and inputting a retiming signal into the frequency mixer 4 according to the local oscillation signal;
the mixer 4 is configured to perform frequency conversion processing on the received retimed signal and the antenna 6 signal to obtain an antenna 6 signal to be processed, and send the antenna 6 signal to be processed to the demodulator 8;
the signal processing unit 9 is used for processing the antenna 6 signal to be processed, so that the upper computer can receive the information transmitted by the antenna 6 signal.
In this embodiment, when the antenna 6 receives a signal from the external antenna 6, the signal from the antenna 6 is amplified by the low noise amplifier 7, the clock signal input unit 5 generates a local oscillation signal, the local oscillation signal is input into the digital logic unit 2 and the frequency dividing unit 1, the frequency dividing unit 1 divides the frequency of the local oscillation signal to obtain a frequency divided signal, the frequency divided signal received by the digital logic unit 2 generates a retimed signal and is input to the data input terminal of the D flip-flop 3, the D flip-flop 3 generates a frequency converted signal for frequency conversion of the signal from the antenna 6 according to the received retimed signal and the local oscillation signal, and transmits the frequency converted signal to the mixer 4, and the frequency converted signal at this time only passes through the frequency dividing unit 1 and the high speed digital unit, so that the delay time is reduced, the phase noise is reduced, the processing capability of the noise of the receiver is significantly improved, and the pass quality of the receiver is further improved.
As an alternative implementation manner of this embodiment, the clock signal input unit 5 includes a frequency synthesizer, and the output terminals of the frequency synthesizer are respectively connected to the clock signal input terminal of the frequency dividing unit 1 and the clock signal input terminal of the D flip-flop 3. The frequency synthesizer is configured to generate a local oscillator signal, which is a clock signal in this embodiment, and transmit the local oscillator signal to the frequency dividing unit 1 and the D flip-flop 3.
As another alternative to this embodiment, the clock signal input unit 5 includes an external clock signal input terminal, and the external clock signal input terminal may be connected to an external device capable of generating a local oscillation signal, such as an oscillation generator, so that the local oscillation signal is input into the frequency dividing unit 1 and the D flip-flop 3 through the external clock signal input terminal.
In this embodiment, the same local oscillator signal is used as the clock signal of the frequency dividing unit 1 and the D flip-flop 3, so that the controllable retiming function of the D flip-flop 3 can be realized, and the processing effect of the phase noise generated by the local oscillator signal is improved.
As an alternative implementation manner of this embodiment, the frequency dividing unit 1 includes a multi-modulus frequency divider 11, an input terminal of the multi-modulus frequency divider 11 is connected to an output terminal of the frequency synthesizer, and a first frequency dividing signal output terminal of the multi-modulus frequency divider 11 is connected to a first input terminal of the digital logic unit 2.
Because the local oscillator signal generated by the frequency synthesizer has only 2 octave bandwidth, the multi-mode frequency divider 11 can perform programmable frequency division on the local oscillator signal for wider frequency range, so as to realize wider receiving frequency range, and therefore, the multi-mode frequency divider 11 is adopted to perform frequency division on the local oscillator signal. However, the local oscillator signal received by the mixer 4 is usually a signal with a frequency below 1GHZ, and the multi-modulus frequency divider 11 can only divide the local oscillator signal by 1 GHZ.
In the present embodiment, the frequency-divided signal includes a first frequency-divided signal and a second frequency-divided signal; the multi-modulus frequency divider 11 divides the local oscillator signal to obtain a first frequency-divided signal, the digital frequency divider 12 further divides the frequency of the first frequency-divided signal to obtain a second frequency-divided signal, the multi-modulus frequency divider 11 inputs the first frequency-divided signal to the first input end of the digital logic unit 2, and the digital frequency divider 12 inputs the second frequency-divided signal to the second input end of the digital logic unit 2.
Since the digital frequency divider 12 divides the frequency of the first divided signal, the frequency of the first divided signal is greater than the frequency of the second divided signal.
Referring to fig. 1 and 2, in the present embodiment, the multi-modulus frequency divider 11 includes a plurality of 2/3 frequency dividers connected in series in sequence, the clock signal input terminal CLK of the first stage 2/3 frequency divider is connected to the output terminal of the frequency synthesizer, the CLKO terminal of the first stage 2/3 frequency divider is connected to the CLK terminal of the next stage 2/3 frequency divider, the CLKO terminal of the last stage 2/3 frequency divider is connected to the input terminal of the digital frequency divider 12, the CONO terminal of the first stage 2/3 frequency divider is connected to the first input terminal of the digital logic unit 2, and the CONO terminal of the next stage 2/3 frequency divider is connected to the CON terminal of the previous stage 2/3 frequency divider, thereby implementing the series connection of the plurality of 2/3 frequency dividers.
In the present embodiment, the second signal output terminal of the digital frequency divider 12 is connected to the control terminal SW of each 2/3 frequency divider, i.e. the SW signal is output to the control terminal SW of each 2/3 frequency divider through the digital frequency divider 12, so as to control the frequency dividing ratio of the 2/3 frequency divider through the SW terminal and the CON terminal of the 2/3 frequency divider.
Table 1 shows a table of characteristics of the 2/3 frequency divider.
Referring to table 1 and fig. 3, the signal at the CLKO terminal is 1 only when the signal at the SW terminal is 1 and the signal at the con terminal is 1, that is, the output signal at the CLKO terminal is divided by 3 at this time, otherwise, both are divided by 2.
Referring to fig. 4, in this embodiment, as the frequency of the local oscillator signal increases, a higher frequency division ratio is required, and at this time, the local oscillator signal undergoes multiple level inversions to generate phase noise, which causes a phase offset to occur at a zero crossing point of the local oscillator signal, and since the local oscillator signal passes through the multistage 2/3 frequency divider and the digital frequency divider 12, the phase noise of the multistage 2/3 frequency divider is accumulated in the local oscillator signal, which affects the zero crossing point of the local oscillator signal.
Referring to fig. 5, as an alternative implementation manner of this embodiment, the digital logic unit 2 includes a first nand gate and a second nand gate, a first signal input end of the first nand gate is connected to the first signal output end DCON of the digital frequency divider 12, a second signal input end of the first nand gate is connected to an output end of the second nand gate, an output end of the first nand gate is connected to a first signal input end of the second nand gate, a second signal input end of the second nand gate is connected to the CONO end of the first-stage 2/3 frequency divider, and an output end of the second nand gate is connected to the data input end of the D flip-flop 3.
The second frequency-divided signal output by the digital frequency divider 12 and the first frequency-divided signal output by the 2/3 frequency divider are respectively subjected to logic operation, so that the digital logic unit 2 generates a retiming signal according to the first frequency-divided signal and the second frequency-divided signal, and then the retiming signal is input into the D flip-flop 3.
The output frequency of the retiming signal at this time is completely the same as the output frequency of the second divided signal, but the transmission path of the rising edge of the retiming signal only passes through the first stage 2/3 frequency divider and one nand gate of the digital logic unit 2, so that the delay time is shortened, the retiming function of the D flip-flop 3 is realized, the frequency conversion signal output by the D flip-flop 3 is only delayed by the D flip-flop 3, and therefore the phase noise generated by the local oscillation signal in the transmission process is reduced, and the quality of the frequency conversion signal input into the mixer 4 is improved.
In this embodiment, since the transmission path of the retiming signal is long, the delay time of the retiming signal is longer than the period of the local oscillation signal. When the rising edge of the local oscillator signal comes, the retiming signal cannot accurately control the number of cycles delayed relative to the local oscillator signal, and the signal state of the retiming signal has randomness, which results in a high difficulty in processing phase noise. The clock signal input end of the D trigger 3 and the clock signal input end of the first-stage 2/3 frequency divider ensure that the local oscillation signals of the D trigger 3 and the first-stage 2/3 frequency divider are consistent, and accurate control can be performed on delay of a re-timing signal according to the local oscillation signals, so that the difficulty of processing phase noise is reduced, and the phase noise is more conveniently weakened.
The implementation principle of the receiver with the phase noise optimization function in the embodiment of the application is as follows: when the signal of the antenna 6 needs to be subjected to frequency mixing processing, the frequency synthesizer generates a local oscillation signal, the local oscillation signal is respectively transmitted to the D flip-flop 3 and the first-stage 2/3 frequency divider, the multistage 2/3 frequency divider divides the frequency of the local oscillation signal to obtain a first frequency division signal, the first frequency division signal is input into the digital frequency divider 12, the digital frequency divider 12 divides the frequency of the first frequency division signal to obtain a second frequency division signal, the digital logic unit 2 generates a retiming signal according to the first frequency division signal and the second frequency division signal and inputs the retiming signal into the D flip-flop 3, the retiming signal is transmitted from the frequency synthesizer to the D flip-flop 3 through the first-flop 2/3 frequency divider and the NAND gate of the digital logic unit 2, the delay time is reduced, a data input end signal and a clock signal of the D flip-flop 3 both bypass the whole chain of the frequency dividing unit 1, the phase noise generated by the multi-mode frequency divider 11 is greatly reduced, the processing capability of the phase noise of the receiver is improved, and the communication quality of the receiver is further improved.
The embodiment of the application provides a wireless communication system, which comprises the receiver and the transmitter with the phase noise optimization function; the transmitter is arranged to transmit antenna 6 signals and the receiver is arranged to receive antenna 6 signals and process the antenna 6 signals.
The foregoing is a preferred embodiment of the present application and is not intended to limit the scope of the application in any way, and any features disclosed in this specification (including the abstract and drawings) may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.
Claims (2)
1. A receiver with phase noise optimization function, comprising a frequency dividing unit (1), a digital logic unit (2), a D flip-flop (3), a mixer (4) and a clock signal input unit (5), wherein the clock signal input end of the frequency dividing unit (1) is connected to the clock signal input unit (5), the output end of the frequency dividing unit (1) is connected to the digital logic unit (2), the output end of the digital logic unit (2) is connected to the data input end of the D flip-flop (3), the clock signal input end of the D flip-flop (3) is connected to the clock signal input unit (5), and the output end of the D flip-flop (3) is connected to the mixer (4);
the clock signal input unit (5) is used for generating a local oscillation signal and inputting the local oscillation signal to the frequency division unit (1) and the D flip-flop (3);
the frequency division unit (1) is used for receiving the local oscillation signal and carrying out frequency division on the local oscillation signal for multiple times to obtain a frequency division signal;
the digital logic unit (2) is used for receiving the frequency division signal and generating a retiming signal according to the frequency division signal;
the D trigger (3) is used for delaying and inputting the retiming signal into the frequency mixer (4) according to the local oscillator signal;
the mixer (4) is used for carrying out frequency conversion processing on the received retiming signal and an antenna (6) signal to generate an antenna (6) signal to be processed, and sending the antenna (6) signal to be processed to a demodulator (8);
the frequency dividing unit (1) comprises a multi-modulus frequency divider (11), the input end of the multi-modulus frequency divider (11) is connected to the clock signal input unit (5), and the first signal output end of the multi-modulus frequency divider (11) is connected to the first input end of the digital logic unit (2);
the frequency dividing unit (1) further comprises a digital frequency divider (12), wherein the input end of the digital frequency divider (12) is connected to the second signal output end of the multi-modulus frequency divider (11), and the first signal output end of the digital frequency divider (12) is connected to the second input end of the digital logic unit (2);
the multi-modulus frequency divider (11) outputs a first frequency-divided signal, the digital frequency divider (12) outputs a second frequency-divided signal, and the frequency of the first frequency-divided signal is greater than that of the second frequency-divided signal;
the multi-modulus frequency divider (11) comprises a plurality of 2/3 frequency dividers which are sequentially connected in series, the input end of the 2/3 frequency divider of the first stage is connected to the clock signal input unit (5), the output end of the 2/3 frequency divider of the first stage is connected to the first signal output end of the multi-modulus frequency divider (11), and the output end of the 2/3 frequency divider of the last stage is connected to the second signal output end of the multi-modulus frequency divider (11);
the control ends of the 2/3 frequency dividers are connected to the second signal output end of the digital frequency divider (12);
the digital frequency divider (12) is used for controlling the frequency dividing ratio of a plurality of 2/3 frequency dividers;
the digital logic unit (2) comprises a first NAND gate and a second NAND gate, wherein a first signal input end of the first NAND gate is connected to a first signal output end of the digital frequency divider (12), a second signal input end of the first NAND gate is connected to a signal output end of the second NAND gate, an output end of the first NAND gate is connected to a first signal input end of the second NAND gate, a second signal input end of the second NAND gate is connected to a first signal output end of the multi-modulus frequency divider (11), and an output end of the second NAND gate is connected to a data input end of the D flip-flop (3);
the clock signal input unit (5) comprises a frequency synthesizer, and the output end of the frequency synthesizer is respectively connected with the clock signal input end of the frequency dividing unit (1) and the clock signal input end of the D trigger (3);
the frequency synthesizer is used for providing a local oscillator signal and transmitting the local oscillator signal to the frequency division unit (1) and the D trigger (3).
2. A wireless communication system comprising a transmitter and a receiver with phase noise optimization according to claim 1.
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| CN204425335U (en) * | 2015-03-26 | 2015-06-24 | 成都爱洁隆信息技术有限公司 | A kind of Beidou I navigation system transceiver chip structure |
| CN215835391U (en) * | 2021-07-01 | 2022-02-15 | 深圳捷扬微电子有限公司 | Digital radio frequency transmitter |
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