CN115549703B - Transmitter and transceiver integrated with CMOS power amplifier - Google Patents
Transmitter and transceiver integrated with CMOS power amplifier Download PDFInfo
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- CN115549703B CN115549703B CN202211227854.4A CN202211227854A CN115549703B CN 115549703 B CN115549703 B CN 115549703B CN 202211227854 A CN202211227854 A CN 202211227854A CN 115549703 B CN115549703 B CN 115549703B
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- 238000010586 diagram Methods 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 7
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B2001/0408—Circuits with power amplifiers
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Abstract
The invention provides an integrated CMOS power amplifier wide voltage transmitter, comprising: a transmitting module for transmitting signals, the transmitting module comprising a CMOS power amplifier; and the transmitter control module is electrically connected with the transmitting module and is used for controlling the transmitting frequency and transmitting power of the radio frequency signals transmitted by the transmitting module according to a network protocol and processing baseband signals. The transmitter can improve the integration level, reduce the module area and the number of module components, and further reduce the cost. The invention also provides an integrated CMOS power amplifier wide voltage transceiver.
Description
Technical Field
The present invention relates to the field of wireless communication technologies, and in particular, to an integrated CMOS power amplifier wide voltage transmitter and transceiver.
Background
Power Amplifiers (PA) are mainly used in transmitters and transceivers, at the final stage of the transmitting end, for amplifying the transmitted signal. The power amplifier mainly has indexes such as saturated power, efficiency, linearity and the like. Depending on the fabrication process, the transmitter and transceiver are typically CMOS processes, while the power amplifier is typically GaAs or other compound processes, which is typically difficult to integrate on the same chip as the transmitter or transceiver. The application of the integrated CMOS power amplifier in the field of the narrowband Internet of things (Narrow Band Internet of Things, NBIoT) is still blank. Fig. 1 is a schematic diagram of a narrowband internet of things transmitter in the prior art, referring to fig. 1, the existing narrowband internet of things transmitter comprises a power management module 1, a transmitter control module 2 and a transmitting module 3, a GaAs power amplifier 4 chip is separately arranged with the transmitter, the GaAs power amplifier 4 is connected with the transmitting module 3 through a power amplifier input matching module 5, and the split structure enables the module to occupy a larger area, and has low integration level and high cost.
Accordingly, there is a need to provide a new integrated CMOS power amplifier wide voltage transmitter and integrated CMOS power amplifier wide voltage transceiver that solves the above-mentioned problems of the prior art.
Disclosure of Invention
The invention aims to provide an integrated CMOS power amplifier wide voltage transmitter and an integrated CMOS power amplifier wide voltage transceiver, which can improve the integration level, reduce the module area and the number of module components, and further reduce the cost.
To achieve the above object, the integrated CMOS power amplifier wide voltage transmitter of the present invention includes:
A transmitting module for transmitting signals, the transmitting module comprising a CMOS power amplifier;
and the transmitter control module is electrically connected with the transmitting module and is used for controlling the transmitting frequency and transmitting power of the radio frequency signals transmitted by the transmitting module according to a network protocol and processing baseband signals.
The transmitter of the invention has the beneficial effects that: the CMOS power amplifier is integrated, so that the integration level can be improved, the module area is reduced, an additional power amplifier chip is not needed, the power amplifier input matching is not needed, the number of module components can be reduced, and the cost is reduced.
Optionally, the CMOS power amplifier includes a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, and a sixth NMOS, where the gate of the first NMOS is connected to the gate of the second NMOS, the gate of the third NMOS is connected to the gate of the fourth NMOS, the source of the first NMOS, the source of the second NMOS, the source of the third NMOS, and the source of the fourth NMOS are connected to the ground, the drain of the first NMOS and the drain of the third NMOS are connected to the source of the fifth NMOS, the drain of the second NMOS and the drain of the fourth NMOS are connected to the source of the sixth NMOS, and the gate of the fifth NMOS and the gate of the sixth NMOS are connected to each other and are connected to a bias voltage. The beneficial effects are that: the generation of non-linearities of the CMOS power amplifier can be reduced, and variations in phase difference between the output and input signals can be reduced, so that the transmitter can accommodate a larger voltage range.
Optionally, the CMOS power amplifier further includes a first resistor and a second resistor, where a source of the second NMOS tube is connected to one end of the first resistor, a source of the third NMOS tube is connected to one end of the second resistor, and a source of the first NMOS tube, another end of the first resistor, another end of the second resistor are connected to a source of the fourth NMOS tube and grounded. The beneficial effects are that: the current consumption can be reduced without affecting the overall efficiency of the CMOS power amplifier.
Optionally, the transmitting module further includes a digital-to-analog converter, a low-pass filter, and a mixer, where the digital-to-analog converter, the low-pass filter, the mixer, and the CMOS power amplifier are sequentially connected and transmit a radio frequency signal, and the CMOS power amplifier is configured to amplify the radio frequency signal.
Optionally, the CMOS power amplifier is connected to the antenna through a balun, and an impedance turns ratio of a radio frequency input end and a radio frequency output end of the balun is 1:n, where n is greater than or equal to 3. The beneficial effects are that: the use of balun with high turns ratio can reduce the load impedance of CMOS power amplifier so that sufficient power can be emitted also at low voltage.
Optionally, the system further comprises a power management module, wherein the power management module is used for supplying power to the transmitting module and the transmitter control module.
Optionally, the power management module includes a DC-DC converter or an LDO circuit, and the CMOS power amplifier is connected to a power source through the DC-DC converter or the LDO circuit. The beneficial effects are that: the transmitter can be adapted to a larger voltage range.
Optionally, the power management module further comprises a DC-DC converter and an LDO circuit, and the CMOS power amplifier is connected with a power supply through the LDO circuit and the DC-DC converter in sequence. The beneficial effects are that: the power supply ripple can be restrained, and output spurious emissions can be reduced.
Optionally, the transmitter is applied to the internet of things, the narrowband private network or the satellite internet.
The invention also provides an integrated CMOS power amplifier wide voltage transceiver, which is characterized by comprising a receiver and the transmitter. The transceiver has the beneficial effects that: the transceiver integrates the CMOS power amplifier, can improve the integration level, reduces the module area, does not need additional power amplifier chips, does not need power amplifier input matching, can reduce the number of module components and reduces the cost.
Drawings
Fig. 1 is a schematic diagram of a prior art narrowband internet of things transmitter;
FIG. 2 is a schematic diagram of a transmitter in some embodiments;
FIG. 3 is a schematic diagram of a transmitter in other embodiments;
FIG. 4 is a schematic diagram of turns of balun in some embodiments;
FIG. 5 is a side view of a balun laminate structure in accordance with some embodiments of the present invention;
FIG. 6 is a top view of the m3 metal layer;
FIG. 7 is a top view of the m2 metal layer;
FIG. 8 is a top view of the m1 metal layer;
FIG. 9 is a top view of the V1 layer;
fig. 10 is a circuit schematic of a high frequency CMOS power amplifier in some embodiments.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
Fig. 2 is a schematic diagram of a transmitter in some embodiments. Referring to fig. 2, the transmitter includes:
A transmitting module 3 for transmitting signals, said transmitting module comprising a CMOS power amplifier 31;
And the transmitter control module 2 is electrically connected with the transmitting module 3 and is used for controlling the transmitting frequency and transmitting power of the radio frequency signals transmitted by the transmitting module 3 and processing baseband signals according to a protocol of the narrowband internet of things.
The transmitter integrates the CMOS power amplifier, can improve the integration level, reduce the module area, does not need an additional power amplifier chip or power amplifier input matching, can reduce the number of module components and reduce the cost.
In some embodiments, the transmitter is applied to the internet of things, the narrowband private network, or the satellite internet.
Referring to fig. 2, the transmitting module 3 further includes a digital-to-analog converter 34, a low-pass filter 33, and a mixer 32, wherein the digital-to-analog converter 34, the low-pass filter 33, the mixer 32, and the CMOS power amplifier 31 are sequentially connected to and transmit a radio frequency signal, and the CMOS power amplifier 31 is configured to amplify the radio frequency signal.
In some embodiments, the CMOS power amplifier 31 includes a high frequency CMOS power amplifier 311 and a low frequency CMOS power amplifier 312, the mixer 32 includes a first mixer 321 and a second mixer 322, the low pass filter 33 includes a first low pass filter 331 and a second low pass filter 332, the digital-to-analog converter 34 includes a first digital-to-analog converter 341 and a second digital-to-analog converter 342, the first digital-to-analog converter 341, the first low pass filter 331, the first mixer 321 and the high frequency CMOS power amplifier 311 are sequentially connected to and transmit high frequency radio frequency signals, and the second digital-to-analog converter 342, the second low pass filter 332, the second mixer 322 and the low frequency CMOS power amplifier 312 are sequentially connected to and transmit low frequency radio frequency signals.
Fig. 3 is a schematic diagram of a transmitter in other embodiments. Referring to fig. 3, the high frequency CMOS power amplifier 311 is connected to the antenna 7 through the balun 6, and the impedance turns ratio of the rf input end and the rf output end of the balun 6 is 1:n, where n is greater than or equal to 3. For different voltages and output power, the value of N takes the corresponding optimal value, and when the voltage is 1.8v, the saturated power is more than or equal to 28dbm, and N is preferably 3. If the voltage is lower or the power is higher, the value of N is larger. The use of balun with high turns ratio can reduce the load impedance of CMOS power amplifier so that sufficient power can be emitted also at low voltage.
The theoretical value N 'of the balun is related to saturated power P sat (unit: W) and voltage VDD (unit: V) as N' =PA linearity and PA efficiency are higher when.
N corresponds to N' when the parasitic inductance and capacitance of the wiring or package in practical use are not considered.
In some embodiments, when the saturated power is 28dbm and the voltage is 1.8V, the linearity and the efficiency of the PA are higher when N is 2-4; when the saturated power is 28dbm and the voltage value is 2.5V, the linearity and the efficiency of the PA are higher when N is 1.5-2.5; when the saturated power is 28dbm and the voltage is 3.3V, the linearity and the efficiency of the PA are higher when N is 1-2.
Fig. 4 is a schematic diagram of balun turns in some embodiments. Referring to fig. 3 and 4, the radio frequency input port includes a first input port 61 and a second input port 62, and the radio frequency output port includes a first output port 63 and a second output port 64. The radio frequency input end adopts a mode of 3-circle impedance parallel connection, the radio frequency output end is 3-circle impedance, the impedance turns ratio of the radio frequency input end and the radio frequency output end of the balun 6 is 1:3, the radio frequency signal transmitted by the high-frequency CMOS power amplifier 311 is input by the first input port 61 and the second input port 62, and is transmitted to the antenna 7 by the first output port 63, and the second output port 64 is grounded. Fig. 5 is a side view of a stacked structure of a balun according to some embodiments of the present invention, and referring to fig. 5, the balun includes 3 metal layers and 2 VIA holes, the 3 metal layers are respectively an m1 metal layer, an m2 metal layer, and an m3 metal layer, and the 2 VIA holes are respectively a V1 layer and a V2 layer, where the V2 layer is empty. Fig. 6 is a top view of the m3 metal layer of fig. 5, fig. 7 is a top view of the m2 metal layer of fig. 5, fig. 8 is a top view of the m1 metal layer of fig. 5, and fig. 9 is a top view of the V1 layer of fig. 5.
In some embodiments, the balun 6 has an impedance-to-turns ratio of 1:1 or 1:2 between the rf input and rf output.
In some embodiments, the balun uses a chip of an integrated passive device (INTEGRATED PASSIVE DEVICE, IPD) process, and is very suitable for integrated passive devices, such as inductors, capacitors and the like, because the IPD process has larger substrate impedance and lower cost per unit area compared with the CMOS process, so that the working efficiency of the balun can be improved by using the IPD process.
Referring to fig. 2 and 3, the transmitter further comprises a power management module 1, the power management module 1 being configured to power the transmitting module 3 and the transmitter control module 2.
Referring to fig. 3, the transmitter control module 2 includes a phase-locked loop 21, the phase-locked loop 21 is configured to output a frequency signal to the transmitting module 3 to control a transmitting frequency, the phase-locked loop 21 includes a voltage-controlled oscillator 211, and the voltage-controlled oscillator 211 includes a second inductor (not shown in the drawing), and a center of the second inductor is disposed in the same horizontal direction as a center of the balun 6. In some embodiments, the center of the second inductance is disposed in the same vertical direction as the center of the balun 6. Setting the center of the second inductor and the center of the balun 6 in the same horizontal direction or the same vertical direction can solve the problem of pulling (pulling) the phase-locked loop by the CMOS power amplifier.
In some embodiments, the distance between the center of the second inductance and the center of the balun 6 is greater than or equal to 1mm. The distance between the center of the second inductor and the center of the balun 6 is set to be far, so that the problem that the CMOS power amplifier pulls a phase-locked loop (pulling) can be solved.
In some embodiments, the power management module includes a DC-DC converter or the LDO circuit through which the CMOS power amplifier is connected to a power supply. The transmitter can be adapted to a larger voltage range.
Referring to fig. 3, the power management module 1 includes a DC-DC converter 11, and the high frequency CMOS power amplifier 311 is connected to a VBAT pin 13 through the DC-DC converter 11 and to an external power source.
In some embodiments, the power management module further includes an LDO circuit, and the CMOS power amplifier is connected to a power supply through the LDO circuit and the DC-DC converter in sequence, so as to suppress power supply ripple and reduce output spurious.
Referring to fig. 3, the power management module 1 includes a DC-DC converter 11 and an LDO circuit 12, and the high frequency CMOS power amplifier 311 is connected to a power supply through the LDO circuit 12 and the DC-DC converter 11 in sequence.
Referring to fig. 3, the power supply path of the transmitter includes: the power supply is accessed through a VBAT pin 13, passes through the DC-DC converter 11, a first inductor 14 and the LDO circuit 12, and then supplies power to the high-frequency CMOS power amplifier 311 and the first mixer 321, wherein one end of the first inductor 14 is connected with the DC-DC converter 11, the other end is respectively connected with the LDO circuit 12 and the capacitor 15, and the capacitor 15 is grounded. The power path of the transmitter further comprises: the power is connected to the power supply through the VBAT pin 13, passes through the DC-DC converter 11, the first inductor 14 and the TP port 65, and then passes through the first input port 61 and the second input port 62 of the balun 6 to divide the current into two paths for transmission to the high frequency CMOS power amplifier 311.
In some embodiments, the CMOS power amplifier includes a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, and a sixth NMOS, where the gate of the first NMOS is connected to the gate of the second NMOS, the gate of the third NMOS is connected to the gate of the fourth NMOS, the source of the first NMOS, the source of the second NMOS, the source of the third NMOS are connected to the source of the fourth NMOS, and are grounded, the drain of the first NMOS and the drain of the third NMOS are connected to the source of the fifth NMOS, the drain of the second NMOS and the drain of the fourth NMOS are connected to the source of the sixth NMOS, and the gate of the fifth NMOS and the gate of the sixth NMOS are connected to each other and are connected to a bias voltage.
The second NMOS tube and the third NMOS tube adopt a cross pair mode, the first NMOS tube and the second NMOS tube, the third NMOS tube and the fourth NMOS tube are complementary pairs, and the first NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube form a differential structure. The parasitic capacitance generated by the NMOS tube can be expressed as the equivalent capacitance of the CMOS power amplifier by the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube, when the input power changes more, the change of the equivalent capacitance of the CMOS power amplifier is more obvious, and the nonlinearity of the CMOS power amplifier is more obvious. When the transmitter is a narrowband internet of things transmitter, because the narrowband internet of things transmitter is powered by a power supply, more low-voltage application scenes exist, and therefore the transmitter is required to work normally at low voltage, and in order to prolong the service life of a narrowband internet of things module battery, the narrowband internet of things is required to work normally at low voltage, and is usually lower than 2V. Under the low-voltage condition, the input equivalent capacitance of the CMOS power amplifier is generally larger along with the change of the input power than under the high-voltage condition, so that the cross complementary differential structure can enable the narrowband Internet of things transmitter to reduce the generation of nonlinearity under the low-voltage condition, and enable the narrowband Internet of things transmitter to adapt to a larger voltage range. In addition, as the narrow-band internet of things protocol requires 23dBm average power, the saturated power of the corresponding power amplifier exceeds 28dBm, and the power required by the narrow-band internet of things protocol is larger through multistage amplification, the narrow-band internet of things transmitter adopts a cross complementary differential structure and is connected with balun output signals, and the power amplifier can adapt to the power requirement of the narrow-band internet of things.
In some embodiments, the CMOS power amplifier further includes a first resistor and a second resistor, where a source of the second NMOS transistor is connected to one end of the first resistor, a source of the third NMOS transistor is connected to one end of the second resistor, and a source of the first NMOS transistor, another end of the first resistor, another end of the second resistor are connected to a source of the fourth NMOS transistor and grounded. The second NMOS tube and the third NMOS tube forming the cross pair are respectively connected with resistors, so that current consumption can be reduced, and the overall efficiency of the CMOS power amplifier is not affected.
Fig. 10 is a circuit schematic of a high frequency CMOS power amplifier in some embodiments. Referring to fig. 10, the high frequency CMOS power amplifier 311 includes a first NMOS transistor 3111, a second NMOS transistor 3112, a third NMOS transistor 3113, a fourth NMOS transistor 3114, a fifth NMOS transistor 3115, and a sixth NMOS transistor 3116, where a gate of the first NMOS transistor 3111 is connected to a gate of the second NMOS transistor 3112, a gate of the third NMOS transistor 3113 is connected to a gate of the fourth NMOS transistor 3114, a source of the first NMOS transistor 3111, a source of the second NMOS transistor 3112, a source of the third NMOS transistor 3113, and a source of the fourth NMOS transistor 3114 are connected to each other and connected to each other, a drain of the first NMOS transistor 3111 and a drain of the third NMOS transistor 3113 are connected to a source of the fifth NMOS transistor 3115, a drain of the second NMOS transistor 3112 and a drain of the fourth NMOS transistor 3114 are connected to a source of the sixth NMOS transistor 3116, and the gates of the fifth NMOS transistor 3115 and the sixth NMOS transistor 3116 are connected to each other (voltage bias is not shown in fig. 3116). The first NMOS transistor 3111 is connected to the first signal inlet 31111, the fourth NMOS transistor 3114 is connected to the second signal inlet 31141, the fifth NMOS transistor 3115 is connected to the first signal outlet 31151, and the sixth NMOS transistor 3116 is connected to the second signal outlet 31161.
Referring to fig. 10, the high frequency CMOS power amplifier 311 further includes a first resistor 3117 and a second resistor 3118, where a source of the second NMOS transistor 3112 is connected to one end of the first resistor 3117, a source of the third NMOS transistor 3113 is connected to one end of the second resistor 3118, and a source of the first NMOS transistor 3111, the other end of the first resistor 3117, and the other end of the second resistor 3118 are connected to the source of the fourth NMOS transistor 3114 and grounded.
The principle by which the CMOS power amplifier of the present invention can reduce the generation of nonlinearities is described in detail below. In the differential structure of the prior art, the NMOS transistor connected to the second signal inlet has g, s, and d ports, and a parasitic capacitance exists between each port, for example, the parasitic capacitance between g and s is Cgs, and the parasitic capacitance between g and d is Cgd. Meanwhile, this NMOS has a signal gain, denoted a (typically negative). At this time, the equivalent input capacitance Crfin _p of the second signal inlet may be approximately Crfin _p≡cgs-a×cgd. As the amplitude of the output signal increases, cgs and Cgd change, and the gain a also changes, which causes a change in the PA equivalent input capacitance, and in addition, AMAM, AMPM and the equivalent input capacitance are strongly correlated, and AMAM distortion refers to distortion on the amplitude of the output signal and the input signal, for example, when the amplitude of the input signal goes below a threshold voltage or above a saturation voltage, the output voltage signal is truncated or truncated, that is, AMAM distortion. AMPM distortion refers to a change in the amplitude of a nonlinear PA input signal, resulting in a change in the phase difference between the output and input signals. This can cause the AMAM, AMPM curves of the PA to deviate from ideal PA curves. In order to improve the linearity of PA, the actual AMAM and AMPM curves need to be close to the ideal curves, and the variation of PA equivalent input capacitance along with other factors, such as input power, process deviation and the like, needs to be reduced.
Referring to fig. 10, in the CMOS power amplifier of the present invention, the d-port of the fourth NMOS transistor 3114 is a negative swing, and the d-port of the third NMOS transistor 3113 is a positive swing. At this time, the equivalent input capacitance Crfin _p of the second signal inlet 31141 may be denoted as Crfin _p≡cgs4-a4×cgd4+cgs3+a3×cgd3≡2×cgs, and is designed to cancel a4×cgd4 and a3×cgd3 as much as possible. As the amplitude of the output signal increases, cgs, cgd vary, but the output capacitance is almost not as much related to the gains a and Cgd as compared to a conventional differential structure. Even though a and Cgd may vary with input/output power, the variation in the equivalent input capacitance of the second signal inlet 31141 and the first signal inlet 31111 may be smaller.
The AMPM distortion produced by the CMOS power amplifier is small with process fluctuations, since in conventional structures Crfin _p≡cgs-a Cgd, here 3 variables Cgs, A, cgd are all process dependent. In the CMOS power amplifier of the present invention Crfin _p≡cgs4-a4 cgd4+cgs3+a3 cgd3≡2 Cgs, only one variable of Cgs will change with process variation. Thus, the AMPM distortion generated by the CMOS power amplifier of the present invention is small with process fluctuations.
The invention also provides a transceiver comprising a receiver and the transmitter.
The transceiver of the invention integrates the CMOS power amplifier, can improve the integration level, reduce the module area, does not need additional power amplifier chips, does not need power amplifier input matching, can reduce the number of module components and reduce the cost.
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (9)
1. A transmitter integrating a CMOS power amplifier, comprising:
The transmitting module is used for transmitting signals and comprises a CMOS power amplifier, the CMOS power amplifier is connected to an antenna through a balun, the impedance turns ratio of a radio frequency input end and a radio frequency output end of the balun is 1:N, and N is greater than or equal to 3; the theoretical value N' of the balun is related to the saturated power Psat and the voltage VDD
N'=；
And the transmitter control module is electrically connected with the transmitting module and is used for controlling the transmitting frequency and transmitting power of the radio frequency signals transmitted by the transmitting module according to a network protocol and processing baseband signals.
2. The transmitter of claim 1, wherein the CMOS power amplifier comprises a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, and a sixth NMOS, wherein the gate of the first NMOS is in communication with the gate of the second NMOS, the gate of the third NMOS is in communication with the gate of the fourth NMOS, the source of the first NMOS, the source of the second NMOS, the source of the third NMOS is in communication with the source of the fourth NMOS, the drain of the first NMOS and the drain of the third NMOS are in communication with the source of the fifth NMOS, the drain of the second NMOS and the drain of the fourth NMOS are in communication with the source of the sixth NMOS, and the gate of the fifth NMOS and the gate of the sixth NMOS are in communication and are in communication with a bias voltage.
3. The transmitter of claim 2, wherein the CMOS power amplifier further comprises a first resistor and a second resistor, wherein a source of the second NMOS transistor is connected to one end of the first resistor, a source of the third NMOS transistor is connected to one end of the second resistor, and a source of the first NMOS transistor, the other end of the first resistor, and the other end of the second resistor are connected to the source of the fourth NMOS transistor and grounded.
4. The transmitter of claim 1, wherein the transmitting module further comprises a digital-to-analog converter, a low pass filter, and a mixer, the digital-to-analog converter, the low pass filter, the mixer, and the CMOS power amplifier being sequentially connected and transmitting a radio frequency signal, the CMOS power amplifier being configured to amplify the radio frequency signal.
5. The transmitter of claim 1, further comprising a power management module for powering the transmit module and the transmitter control module.
6. The transmitter of claim 5, wherein the power management module comprises a DC-DC converter or an LDO circuit, and wherein the CMOS power amplifier is connected to a power supply through the DC-DC converter or the LDO circuit.
7. The transmitter of claim 6, wherein the power management module further comprises a DC-DC converter and an LDO circuit, the CMOS power amplifier being connected to a power supply through the LDO circuit and the DC-DC converter in sequence.
8. The transmitter of claim 1, wherein the transmitter is applied to the internet of things, narrowband private network or satellite internet.
9. A transceiver integrated with a CMOS power amplifier, comprising a receiver and a transmitter as claimed in any one of claims 1 to 8.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211227854.4A CN115549703B (en) | 2022-10-09 | 2022-10-09 | Transmitter and transceiver integrated with CMOS power amplifier |
| PCT/CN2023/097733 WO2024077973A1 (en) | 2022-10-09 | 2023-06-01 | Cmos power amplifier integrated wide-voltage transmitter and transceiver |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211227854.4A CN115549703B (en) | 2022-10-09 | 2022-10-09 | Transmitter and transceiver integrated with CMOS power amplifier |
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| CN115549703A CN115549703A (en) | 2022-12-30 |
| CN115549703B true CN115549703B (en) | 2024-06-18 |
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| CN115549703B (en) * | 2022-10-09 | 2024-06-18 | 芯翼信息科技(上海)有限公司 | Transmitter and transceiver integrated with CMOS power amplifier |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111965605A (en) * | 2020-02-28 | 2020-11-20 | 加特兰微电子科技(上海)有限公司 | Frequency modulated continuous wave signal transmitting device, method of transmitting frequency modulated continuous wave signal, signal transmitting/receiving device, electronic device, and apparatus |
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| CN1148873C (en) * | 1998-07-24 | 2004-05-05 | 环球通讯科技半导体公司 | Single chip CMOS transmitter/receiver and VCO-mixer structure |
| US7301396B1 (en) * | 2004-12-16 | 2007-11-27 | Anadigics, Inc. | System and method for distortion cancellation in amplifiers |
| CN101944924B (en) * | 2010-09-30 | 2013-03-20 | 东南大学 | Broadband MIMO radio frequency transceiving system for next-generation wireless communication network |
| CN103516371B (en) * | 2013-09-18 | 2015-10-21 | 清华大学 | Configurable transmitting set |
| CN103762948B (en) * | 2013-12-24 | 2016-09-28 | 芯原微电子(上海)有限公司 | A kind of CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) |
| CN107204785B (en) * | 2017-04-23 | 2019-10-15 | 复旦大学 | A Configurable Low-Power All-Digital Transmitter |
| CN112702029B (en) * | 2021-03-25 | 2021-05-28 | 成都知融科技股份有限公司 | CMOS power amplifier chip with on-chip integrated detection function |
| CN115549703B (en) * | 2022-10-09 | 2024-06-18 | 芯翼信息科技(上海)有限公司 | Transmitter and transceiver integrated with CMOS power amplifier |
| CN115549608A (en) * | 2022-10-09 | 2022-12-30 | 芯翼信息科技(上海)有限公司 | Integrated high linearity CMOS power amplifier |
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| CN111965605A (en) * | 2020-02-28 | 2020-11-20 | 加特兰微电子科技(上海)有限公司 | Frequency modulated continuous wave signal transmitting device, method of transmitting frequency modulated continuous wave signal, signal transmitting/receiving device, electronic device, and apparatus |
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| CN115549703A (en) | 2022-12-30 |
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