CN115549655A - Delay device and delay control method - Google Patents

Abstract

The invention provides a delay device and a delay control method. The delay means comprises at least one current controlled delay group and at least one switch. The at least one current controlled delay group is coupled to the transmission line, each current controlled delay group including at least one current controlled delay, each current controlled delay providing a delay according to a control voltage. Switches are respectively coupled between the current control delay groups and the transmission conductors, and each of the switches is turned on or off according to a bit of an enable signal applied thereto. The invention can dynamically adjust the generated delay and is not influenced by parasitic capacitance.

Description

Delay device and delay control method

technical field

The invention relates to a delay device and a delay control method, in particular to a dynamically adjustable delay device and a delay control method which do not require an encoder.

Background technique

With the advancement of electronic technology, the design of integrated circuits has become an important key technology. In circuit design, it is often necessary to control the transmission delay on the transmission wire. In the prior art, there are many ways to adjust the transmission delay on the transmission wire. For example, setting the value of the capacitor on the transmission line or creating a delay by controlling the pull-up or pull-down current source of the buffer, the above-mentioned method, the amount of delay produced, may be affected by the parasitic capacitance transmitted to the line, which is difficult to control, or can be manipulated The adjustment range of the delay amount is often limited, which cannot meet the requirements of design specifications. In addition, in the prior art, it is often necessary to set up a complex decoder to program the transmission delay of the provided transmission wire, and this method is also difficult to control the linearity of the transmission delay adjustment, and cannot provide high-precision design specification requirements.

Contents of the invention

The invention is directed to a delay device and a delay control method, which can dynamically adjust the generated delay without the need of an encoder, and can not be affected by parasitic capacitance.

According to an embodiment of the invention, the delay means comprises at least one current controlled delay and at least one switch. The current-controlled delay groups are coupled to the transmission line, each current-controlled delay group includes at least one current-controlled delay, and each current-controlled delay provides a delay according to a control voltage. Switches are respectively coupled between the current-controlled delay groups and the transmission wires, each of the switches being turned on or off according to a bit of an enable signal applied thereto.

According to an embodiment of the present invention, the delay control method includes: setting at least one current control delay group on the transmission wire, each current control delay group including at least one current control delay; providing a control voltage to each current control delay to make Each current-controlled delay provides a delay; a plurality of switches are provided between the transmission wire and the current-controlled delay group; and a corresponding bit of an enable signal is provided to each switch so that each switch is turned on or off.

Description of drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain principles of the invention.

FIG. 1 is a schematic diagram of a delay device according to an embodiment of the present invention;

2 is a schematic circuit diagram of a delay device according to another embodiment of the present invention;

3A and 3B are schematic diagrams of other implementations of the current-controlled delay in the delay device of the embodiment of the present invention;

4 is a schematic diagram of a delay device according to another embodiment of the present invention;

5A and 5B are equivalent circuit diagrams when the delay device 400 in the embodiment of FIG. 4 of the present invention performs a delay adjustment action;

FIG. 6 is a flowchart of a delay control method according to an embodiment of the present invention.

Explanation of reference numbers

100, 200, 400: delay device;

110～1N0: current control delay group;

410: enable signal generator

420: Control voltage generator

BUF1, BUF2: buffers;

D11～DN1: Diodes;

DC11～DCNM, DC11A～DCNMB: current control delayer;

EN: enable signal;

EN<0>～EN<N-1>: bits;

IN: input signal;

M11～MN1, M31, M32, M33: transistors;

MP1, MP2, MN1, MN2: transistors;

OUT: output signal;

SW1～SWN, SW1A～SWNB: switches;

TWR, TWR1, TWR2: transmission wires;

VC: control voltage;

VCC: power supply voltage;

VSS: reference ground;

S610-S640: control steps.

detailed description

In the following detailed description, reference is made to the accompanying drawings which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise.

Please refer to FIG. 1 , which is a schematic diagram of a delay device according to an embodiment of the present invention. The delay device 100 includes a plurality of current-controlled delay groups 110-1N0 and a plurality of switches SW1-SWN. Wherein, each current-controlled delay group may include at least one current-controlled delay. In some embodiments, the number of current-controlled delays included in each current-controlled delay group may be different. For example, as shown in Figure 1, the first current control delay group 110 includes a current control delay DC11; the second current control delay group 110 includes two current control delays DC21, DC22; the Nth current control delay group 1N0 includes M current-controlled delays DCN1 -DCNM, wherein M may be equal to 2 ^N-1 , and N is a positive integer. That is to say, in this embodiment, among the current-controlled delay groups 110 - 1N0 , the ratio of the number of current-controlled delays included in two adjacent current-controlled delay groups is 1:2. In this embodiment, the number ratio of the current-controlled delays respectively included in the current-controlled delay groups 110˜1N0 is 1:2:4: . . . :2 ^N−1 .

The switches SW1-SWN are respectively coupled between the current-controlled delay groups 110-1N0 and the transmission wire TWR. In this embodiment, the transmission wire TWR may be coupled between the buffer BUF1 and the buffer BUF2. The input terminal of the buffer BUF1 receives the input signal IN, and the output terminal of the buffer BUF2 provides the output signal OUT. The switches SW1˜SWN respectively receive a plurality of bits EN<0>˜EN<N−1> of the enable signal EN. Wherein, bit EN<0> may be the least significant bit (Least Significant Bit, LSB) of the enable signal EN, and bit EN<N-1> may be the most significant bit (Most Significant Bit, MSB) of the enable signal EN.

In other embodiments of the present invention, the minimum number of current control delay groups may be one, and the minimum number of correspondingly connected switches may also be one. However, there can be one or more current-controlled delays included in each current-controlled delay group, and there is no specific limit on the number.

On the other hand, the number of current-controlled delays in the current-controlled delay groups 110-1N0 can be determined according to the number of bits EN<0>-EN<N-1> of the enable signal EN received by the switches SW1-SW Bit high and low order to set. Wherein, the current control delay group 110 coupled to the switch SW1 receiving the least significant bit (bit EN<0>) of the enable signal EN includes only one (=2 ⁰ ) current control delay DC11; the receive enable signal The current-controlled delay group 110 coupled to the switch SW2 of the second least significant bit of EN (bit EN<1>) includes two (=2 ¹ ) current-controlled delays DC21 and DC22 . By analogy, the current-controlled delay group 110 coupled to the switch SWN receiving the most significant bit (bit EN<N-1>) of the enable signal EN includes M (=2 ^N-1 ) current-controlled delays DCN1~DCNM. That is to say, the bit order of the plurality of bits EN<0>˜EN<N−1> of the enable signal EN is positively related to the number of the current-controlled delays DCN1-DCNM in the corresponding current-controlled delay groups 110-1N0.

In this embodiment, each current-controlled delay receives the control voltage VC and provides a delay according to the control voltage VC. Each current-controlled delay device can generate current internally according to the control voltage VC, and determine the provided delay amount through the charging or discharging behavior of the current. The adjustment of the delay amount of signal transmission on the transmission wire TWR can be performed by controlling the turn-on or turn-off of each switch. Wherein, when all the switches SW1˜SWN are turned off according to the bits EN<0>˜EN<N> of the enable signal EN respectively, the delay of signal transmission on the transmission wire TWR is minimum. When at least one of the switches SW1 - SWN is turned on according to multiple bits of the enable signal EN, the delay of signal transmission on the transmission wire TWR can be increased. Therefore, the improvement degree of the delay amount of signal transmission on the transmission wire TWR can be determined by the number of current-controlled delays operatively connected to the transmission wire TWR. Taking the example that each of the current control delays DCN1~DCNM can provide the same unit delay X, when only the switch SW1 is turned on, the delay of signal transmission on the transmission wire TWR can be increased by 1X, when only When the switch SW2 is turned on, the delay of signal transmission on the transmission wire TWR can be increased by 2X. By analogy, when only the switch SWN is turned on, the delay of signal transmission on the transmission wire TWR can be increased by 2 ^N−1 X. Of course, in this embodiment, multiple switches SW1 - SWN can also be turned on at the same time. For example, when the switches SW1 and SW2 are both turned on, the delay of signal transmission on the transmission wire TWR can be increased by 3X. From the above description, it can be known that when all the switches SW1 ˜ SWN are turned on, the delay of signal transmission on the transmission wire TWR can be increased by a maximum value equal to (2 ^N −1)X.

In addition, in the embodiment of the present invention, the delay amount of signal transmission on the transmission wire TWR can also be adjusted by adjusting the control voltage VC. Wherein, by adjusting the control voltage VC, each of the current-controlled delays DCN1 - DCNM can provide the same unit delay X'. When only the switch SW1 is turned on, the delay amount of signal transmission on the transmission wire TWR can be changed to 1X′. When the switches SW1 and SW2 are both turned on, the delay of signal transmission on the transmission wire TWR can be increased by 3X′. From the above description, it can be seen that when all the switches SW1 ˜ SWN are turned on, the delay of signal transmission on the transmission wire TWR can be increased by a maximum value equal to (2 ^N −1)X′.

It is worth mentioning that, in the embodiment of the present invention, the number of bits of the enable signal EN can be set according to actual design requirements, and there is no specific limit on the number of bits. Wherein when the delay adjustment in the design specification requires relatively high resolution, the enable signal EN may have a relatively high number of bits, for example, 8 or 16 bits. Wherein when the delay adjustment in the design specification requires a relatively low resolution, the enable signal EN may have a relatively low number of bits, such as 2 or 4 bits.

In addition, in this embodiment, each current-controlled delay can have the same circuit structure and can provide the same delay.

Please refer to FIG. 2 below. FIG. 2 is a schematic circuit diagram of a delay device according to another embodiment of the present invention. The delay device 200 includes a plurality of switches SW˜SWN and a plurality of current-controlled delay groups. The plurality of current-controlled delay groups are respectively coupled to the transmission wire TWR through the switches SW˜SWN.

The transmission wire TWR is coupled between the buffers BUF1 and BUF2. The buffer BUF1 includes transistors MP1 and MN1 connected in series between the power supply voltage VCC and the reference ground terminal VSS. The control terminals of the transistors MP1 and MN1 receive the input signal IN, and the coupled terminals of the transistors MP1 and MN1 are coupled to the transmission wire TWR. The buffer BUF2 includes transistors MP2 and MN2 connected in series between the power supply voltage VCC and the reference ground terminal VSS. Control terminals of the transistors MP2 and MN2 are coupled to the transmission wire TWR, and terminals coupled to the transistors MP1 and MN1 generate an output signal OUT. The buffers BUF1 and BUF2 in this embodiment are inverters. In other embodiments, the buffers BUF1 and BUF2 can be any buffer circuits without any limitation.

In this embodiment, each of the current-controlled delays DC11 - DCNM has the same circuit structure. Taking the current-controlled delay DC11 as an example, the current-controlled delay DC11 includes a transistor M21 and a diode D21 . The transistor M21 and the diode D21 are connected in series between the switch SW1 and the reference ground terminal VSS. The control terminal of the transistor M21 receives the control voltage VC, and provides current according to the control voltage VC. The anode of the diode D21 is coupled to the transistor M21, and the cathode of the diode D21 is coupled to the reference ground terminal VSS. The current provided by the transistor M21 can be charged or discharged through the diode D21, thereby generating a delay. The current controlled delay DN1 includes a transistor MN1 and a diode DN1. The transistor MN1 and the diode DN1 have the same electrical characteristics as the transistor M11 and the diode D11 respectively.

The current control delays DC11 to DCNM can roughly adjust the delay amount of signal transmission on the transmission wire TWR according to the control voltage VC. By turning on or off each of the switches SW1 to SWN, fine adjustment of the delay amount of signal transmission on the transmission wire TWR can be performed.

Incidentally, in this embodiment, the coupling order of the transistor M21 and the diode D21 in the current control delay DC11 can be interchanged, and is not limited to that shown in FIG. 2 .

Please refer to FIG. 3A and FIG. 3B below. FIG. 3A and FIG. 3B are schematic diagrams of other implementations of the current-controlled delay device in the delay device according to the embodiment of the present invention. In FIG. 3A , the current-controlled delay 310 includes transistors M31 and M32 connected in series. The transistor M32 is an N-type transistor and is coupled in a diode configuration. The first terminal of the transistor M32 is coupled to the control terminal and is coupled to the transistor M31. The second terminal of the transistor M32 is coupled to the reference ground terminal VSS. The control terminal of the transistor M31 receives the control voltage VC, and generates a current according to the control voltage VC.

In FIG. 3B , the current-controlled delay 320 includes transistors M31 and M33 connected in series. The transistor M33 is a P-type transistor, and is also coupled in a diode configuration. Wherein the second terminal of the transistor M33 is coupled to the control terminal and is coupled to the reference ground terminal VSS. The second terminal of the transistor M32 is coupled to the transistor M31. The control terminal of the transistor M31 receives the control voltage VC, and generates current according to the control voltage VC.

Please refer to FIG. 4 below, which is a schematic diagram of a delay device according to another embodiment of the present invention. The delay device 400 includes current-controlled delays DC11A˜DCNMA, DC11B˜DCNMB, switches SW1A˜SWNA, SW1B˜SWNB, an enable signal generator 410 and a control voltage generator 420 . The current-controlled delays DC11A-DCNMA are coupled to the transmission wire TWR1 through the switches SW1A-SWNA, and the current-controlled delays DC11B-DCNMB are coupled to the transmission wire TWR2 through the switches SW1B-SWNB. The current control delays DC11A-DCNMA and the switches SW1A-SWNA are used to adjust the signal transmission delay on the transmission wire TWR1, and the current control delays DC11B-DCNMB and the switches SW1B-SWNB are used to adjust the signal transmission delay on the transmission wire TWR2.

Regarding the adjustment action of the signal transmission delay, it has been described in detail in the aforementioned embodiments, and will not be repeated here. Different from the previous embodiments, the enable signal generator 410 in this embodiment is coupled to the switches SW1A˜SWNA, SW1B˜SWNB. The enable signal generator 410 is used to generate the enable signal EN, and control the switches SW1A˜SWNA, SW1B˜SWNB to be turned on or off through multiple bits of the enable signal EN. In this embodiment, the enable signal generator 410 can generate multiple bits of the enable signal EN according to the delay fine adjustment signal, and the enable signal generator 410 can encode according to the delay fine adjustment signal to generate the enable signal Multiple bits of EN.

The control voltage generator 420 is coupled to the current-controlled delays DC11A˜DCNMB for generating the control voltage VC. The control voltage generator 420 adjusts the control voltage VC according to the delay coarse adjustment mechanism. Among them, the control voltage generator 420 can reduce the delay provided by each current control delay device DC11A~DCNMB by increasing the control voltage VC, and the control voltage generator 420 can increase the delay of each current control delay by decreasing the control voltage VC. The amount of delay provided by DC11A~DCNMB. Taking the control voltage generator 420 performing a coarse delay adjustment mechanism according to a digital signal to generate the control voltage VC as an example, the control voltage generator 420 may be a digital-to-analog conversion circuit.

For details of the adjustment action, refer to FIGS. 5A and 5B . 5A and 5B are equivalent circuit diagrams when the delay device 400 in the embodiment of FIG. 4 performs a delay adjustment operation. In FIG. 5A, when all the switches SW1A-SWNB are turned off, all the current-controlled delays DC11A-DCNMB are electrically isolated from the transmission wires TWR1, TWR2. At this time, there is a minimum signal transmission delay on the transmission wires TWR1 and TWR2. In FIG. 5B, when all the switches SW1A-SWNB are turned on, all the current-controlled delays DC11A-DCNMA are electrically connected to the transmission wire TWR1, and all the current-controlled delays DC11B-DCNMB are connected to the transmission wire TWR2. electrical connection. At this time, the transmission wires TWR1 and TWR2 both have the maximum signal transmission delay.

Certainly, the switches SW1A˜SWNB in the embodiment of the present invention are not limited to be fully turned on or fully turned off. The delay device 400 can select the switches SW1A˜SWNB to be turned on according to the required delay amount. And the signal transmission delay on the transmission wires TWR1 and TWR2 can be adaptively adjusted by dynamically adjusting the turned-on switch.

Please refer to FIG. 6 below. FIG. 6 is a flowchart of a delay control method according to an embodiment of the present invention. In step S610, at least one current-controlled delay group is set on the transmission wire, each current-controlled delay group includes at least one current-controlled delay, and, in step S620, a control voltage is provided to the current-controlled delay so that each A current controlled delay provides the delay. In step S630, a switch is respectively set between the transmission wire and each current control delay group. Next, in step S640 , provide corresponding bits of the enable signal to each switch to turn on or turn off each switch.

The implementation details of the above steps have been described in detail in the aforementioned multiple embodiments, and will not be repeated here.

According to the above, the embodiments of the present invention provide at least one current-controlled delay group on the transmission line, and make each current-controlled delay group have one or more current-controlled delays. And by setting a switch between each current control delay group and the transmission wire. By controlling the on or off of each switch, the number of current-controlled delays actually connected to the transmission wire can be controlled, and the transmission delay amount of the transmission wire can be effectively controlled. Based on the setting of the current control delay group, the delay device of the embodiment of the present invention can achieve digital delay programming action without setting a complex decoder. Moreover, the present invention simultaneously provides two mechanisms of coarse adjustment (adjustment of control voltage) and fine adjustment (adjustment of switch on or off) to adjust the delay amount, which can expand the adjustment range and resolution. And effectively improve the linearity of delay adjustment. The current-controlled retarder of the present invention can also reduce the image caused by parasitic capacitance by means of current control.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (16)

1. A delay device, comprising:

at least one set of current controlled delays coupled to a transmission line, each set of current controlled delays comprising at least one current controlled delay, each current controlled delay providing a delay according to a control voltage; and

at least one switch respectively coupled between the at least one current controlled delay group and the transmission wire, each of the at least one switch being turned on or off according to a bit of an enable signal applied thereto.

2. The delay device of claim 1, wherein each of the current controlled delays comprises:

a first transistor for providing current according to the control voltage; and

and the delay unit and the first transistor are coupled between the transmission wire and a reference ground terminal in series, and the delay unit performs charging or discharging action according to the current so as to provide the delay.

3. The delay device of claim 2, wherein the delay cells are diodes.

4. The delay device of claim 2, wherein the delay unit is a second transistor, a first terminal of the second transistor is coupled to the first transistor, a control terminal of the second transistor is coupled to a first terminal of the second transistor, a second terminal of the second transistor is coupled to the ground reference, and the second transistor is an N-type transistor.

5. The delay device of claim 2, wherein the delay unit is a second transistor, a first terminal of the second transistor is coupled to the first transistor, a control terminal of the second transistor is coupled to a second terminal of the second transistor, a second terminal of the second transistor is coupled to the ground reference, and the second transistor is a P-type transistor.

6. The delay device of claim 1, wherein the ratio of the number of current controlled delays included in two adjacent current controlled delay groups is 1.

7. The delay device of claim 1, wherein each bit of the enable signal controls the on or off of a switch.

8. The delay device of claim 7, wherein a bit order of each bit of the enable signal is positively correlated to a number of the plurality of current controlled delays of the corresponding set of current controlled delays.

9. The delay device of claim 1, further comprising:

an enable signal generator coupled to each of the at least one switch for generating the enable signal for respectively controlling each switch according to the delay fine adjustment signal.

10. The delay device of claim 1, further comprising:

and the control voltage generator is coupled with the current control delayer and used for generating the control voltage and adjusting the control voltage according to a delay coarse adjustment mechanism.

11. A delay control method, comprising:

arranging at least one current control delay group on a transmission wire, wherein each current control delay group comprises at least one current control delayer;

providing a control voltage to each of said current controlled delays to cause each of said current controlled delays to provide a delay;

a switch is respectively arranged between the transmission wire and each current control delay group; and

the corresponding bit of the enable signal is provided to each switch to enable each switch to be turned on or off respectively.

12. The delay control method of claim 11, wherein a first transistor is provided in each of the current control delayers, so that the first transistor provides current according to the control voltage; and

causing the current to perform a charging or discharging action on a delay cell to provide the delay.

13. The delay control method of claim 11, further comprising:

and making the ratio of the number of the current control delayers included in two adjacent current control delay groups to be 1.

14. The delay control method of claim 11, further comprising:

and enabling each bit of the enable signal to correspondingly control the on or off of one switch.

15. The delay control method of claim 14, wherein a bit order of each bit of the enable signal is positively correlated to a number of the plurality of current control delayers of the corresponding set of current control delays.

16. The delay control method of claim 11, further comprising:

generating the enable signal according to a delay fine adjustment signal; and

and adjusting the control voltage according to a delay coarse adjustment mechanism.

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