CN115513190A - 包含半导体裸片的多个瓦片式堆叠的半导体装置组合件 - Google Patents
包含半导体裸片的多个瓦片式堆叠的半导体装置组合件 Download PDFInfo
- Publication number
- CN115513190A CN115513190A CN202210992379.3A CN202210992379A CN115513190A CN 115513190 A CN115513190 A CN 115513190A CN 202210992379 A CN202210992379 A CN 202210992379A CN 115513190 A CN115513190 A CN 115513190A
- Authority
- CN
- China
- Prior art keywords
- semiconductor dies
- stack
- semiconductor
- shingle
- shingle stack
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 239
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 34
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims 2
- 238000010168 coupling process Methods 0.000 claims 2
- 238000005859 coupling reaction Methods 0.000 claims 2
- 230000000712 assembly Effects 0.000 description 8
- 238000000429 assembly Methods 0.000 description 8
- 230000008901 benefit Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 230000001965 increasing effect Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000004606 Fillers/Extenders Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 241000724291 Tobacco streak virus Species 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48105—Connecting bonding areas at different heights
- H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49112—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
- H01L2224/49176—Wire connectors having the same loop shape and height
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Semiconductor Memories (AREA)
- Die Bonding (AREA)
Abstract
本公开涉及包含半导体裸片的多个瓦片式堆叠的半导体装置组合件。一种半导体装置组合件,其包含:衬底,其具有多个外部连接件;半导体裸片的第一瓦片式堆叠,其直接安置于所述衬底上的第一位置上方且经电耦合到所述多个外部连接件的第一子组;及半导体裸片的第二瓦片式堆叠,其直接安置于所述衬底上的第二位置上方且经电耦合到所述多个外部连接件的第二子组。所述半导体装置组合件进一步包含囊封剂,所述囊封剂至少部分地囊封所述衬底、所述第一瓦片式堆叠,及所述第二瓦片式堆叠。
Description
分案申请
本发明专利申请是申请日为2018年9月7日、申请号为201880072433.4、发明名称为“包含半导体裸片的多个瓦片式堆叠的半导体装置组合件”的发明专利申请案的分案申请。
技术领域
本发明大体上涉及半导体装置,且更特定来说,涉及包含半导体裸片的多个瓦片式堆叠的半导体装置组合件。
背景技术
包含存储器芯片、微处理器芯片及成像器芯片的封装式半导体裸片通常包含安装于衬底上且装入塑料保护覆盖物中或由导热盖覆盖的一或多个半导体裸片。裸片可包含有源电路(例如,提供功能特征,例如存储器单元、处理器电路及/或成像器装置)及/或无源特征(例如,电容器、电阻器等)以及电连接到电路的接合垫。接合垫可电连接到保护覆盖物外的端子以允许裸片连接到更高级电路。
为提供额外功能,可将额外半导体裸片添加到半导体装置组合件。包含额外半导体裸片的一种方法涉及将裸片堆叠于衬底上方。为促进将裸片电连接到衬底,可呈瓦片式堆叠布置裸片,其中每一裸片从下方裸片水平偏移以留下(例如,使用线接合)可接合到衬底上的对应接合指部的裸片的暴露接触垫。此瓦片式堆叠方法的缺点是归因于添加到堆叠的每一额外裸片的悬垂量增加,而使可以此方式堆叠的裸片的数目受限。
为解决此限制,裸片的瓦片式堆叠可包含呈瓦片式方式布置且沿相同方向(例如,如图1中所展示)或沿相反方向(如图2中所展示)偏移的裸片的多个群组。在此方面,图1说明半导体装置组合件100,其中衬底101上的裸片的瓦片式堆叠110包含裸片104的两个群组102及103,其沿相同偏移方向叠置且通过线接合121电连接到衬底101上的接合指部120。参考图1可见,裸片104的第一群组102的线接合121位于第二群组103的悬垂区域111下方,且因此必须在将裸片104的第二群组103堆叠于第一群组102上方之前形成。此外,第二群组103的最底部裸片104必须在第一群组102的最顶部裸片104上方隔开达足够距离(例如,由较厚层裸片附接材料105提供)以允许另存线接合121。因此,此布置的缺点包含必须反复地执行多次堆叠及线接合操作,并且裸片附接材料厚度不同,从而增加制造成本及复杂性。
形成图2中所说明的半导体装置组合件存在类似挑战,其中裸片群组沿相反偏移方向叠置。在此方面,图2说明半导体装置组合件200,其中衬底201上的裸片的瓦片式堆叠210包含裸片204的两个群组202及203,其沿相反偏移方向叠置且通过线接合221电连接到衬底201上的接合指部220。如参考图2可见,裸片204的第一群组202的至少一些线接合221位于第二群组203的悬垂区域211下方,且因此必须在将裸片204的第二群组203堆叠于第一群组202上方之前形成。因此,此布置的缺点包含必须反复地执行多次堆叠及线接合操作,并且在衬底中提供额外接合指部,从而增加制造成本及复杂性。
附图说明
图1说明包含半导体裸片的瓦片式堆叠的半导体装置组合件。
图2说明包含半导体裸片的瓦片式堆叠的半导体装置组合件。
图3说明根据本技术的实施例的包含半导体裸片的多个瓦片式堆叠的半导体装置组合件的简化截面图。
图4说明根据本技术的实施例的包含半导体裸片的多个瓦片式堆叠的半导体装置组合件的简化平面图。
图5说明根据本技术的实施例的包含半导体裸片的多个瓦片式堆叠的半导体装置组合件的简化平面图。
图6说明根据本技术的实施例的包含半导体裸片的多个瓦片式堆叠的半导体装置组合件的简化平面图。
图7说明根据本技术的实施例的包含半导体裸片的多个瓦片式堆叠的半导体装置组合件的简化平面图。
图8说明根据本技术的实施例的包含半导体裸片的多个瓦片式堆叠的半导体装置组合件的简化截面图。
图9说明根据本技术的实施例的包含半导体裸片的多个瓦片式堆叠的半导体装置组合件的简化截面图。
图10是说明根据本技术的一个实施例的制造半导体装置组合件的方法的流程图。
图11是展示包含根据本技术的实施例配置的半导体装置组合件的系统的示意图。
具体实施方式
在下文描述中,论述众多特定细节以提供对本技术的实施例的透彻且可行的描述。然而,相关领域的技术人员将认识到,可在无一或多个特定细节的情况下实践本发明。在其它情况下,未展示或未详细描述通常与半导体装置相关联的众所周知的结构或操作,以避免模糊本技术的其它方面。一般来说,应理解,除本文中所揭示的那些特定实施例之外的各种其它装置、系统及方法可在本技术的范围内。
如上文所论述,增加半导体装置组合件中的瓦片式堆叠中的半导体裸片的数目存在克服成本昂贵的制造挑战(例如,多次反复堆叠及线接合操作,改变裸片到裸片间距等)。因此,根据本技术的半导体装置组合件的若干实施例可提供具有半导体裸片的多个瓦片式堆叠的半导体装置组合件以克服这些挑战。
在此方面,本技术的若干实施例涉及半导体装置组合件,其包含:衬底,其具有多个外部连接件;半导体裸片的第一瓦片式堆叠,其直接安置于所述衬底上的第一位置上方且经电耦合到所述多个外部连接件的第一子组;及半导体裸片的第二瓦片式堆叠,其直接安置于所述衬底上的第二位置上方且经电耦合到所述多个外部连接件的第二子组。所述半导体装置组合件可进一步包含囊封剂,所述囊封剂至少部分地囊封所述衬底、所述第一瓦片式堆叠及所述第二瓦片式堆叠。
下文描述半导体装置的若干实施例的特定细节。术语“半导体装置”通常是指包含半导体材料的固态装置。半导体装置可包含例如从晶片或衬底单粒化的半导体衬底、晶片或裸片。在整个本发明中,半导体装置通常在半导体裸片的上下文中描述;然而,半导体装置不限于半导体裸片。
术语“半导体装置封装”可指具有经并入到共同封装中的一或多个半导体装置的布置。半导体封装可包含外壳或壳体,所述外壳或壳体部分地或完全地囊封至少一个半导体装置。半导体装置封装还可包含中介层衬底,所述中介层衬底承载一或多个半导体装置且经附接到所述壳体或以其它方式并入到所述壳体中。术语“半导体装置组合件”可指一或多个半导体装置、半导体装置封装及/或衬底(例如,中介层、支撑件或其它合适衬底)的组合件。半导体装置组合件可(例如)是以离散封装形式、条带或矩阵形式及/或晶片面板形式制造。如本文中所使用,术语“垂直”、“横向”、“上”及“下”可指半导体装置或装置组合件中的特征鉴于附图中所展示的定向的相对方向或位置。例如,“上”或“最上”可分别是指比相同特征的另一特征或部分更靠近或最接近页面的顶部定位的特征。然而,这些术语应被广义地解释为包含具有其它定向(例如倒置或倾斜定向)的半导体装置,其中顶部/底部、上面/下面、上方/下方、上/下及左/右可取决于定向而互换。
图3是根据本技术的实施例的包含半导体裸片的多个瓦片式堆叠的半导体装置组合件的简化截面图。半导体装置组合件300包含至少部分地由囊封剂330环绕的衬底301、半导体裸片304的第一瓦片式堆叠302及半导体裸片304的第二瓦片式堆叠303(以虚线说明以指示其从截面图平面的凹陷位置)。如参考图3可见,第一瓦片式堆叠302及第二瓦片式堆叠303中的每一者包含四个半导体裸片304。每一堆叠302及303的最底部裸片直接耦合到衬底301,且每一堆叠302及303中的每一裸片304(除最底部裸片之外)沿大致相同方向从紧邻其下方的裸片304偏移达约相同距离(例如,不同于图1及2中所说明的瓦片式堆叠,其中堆叠中的偏移距离可变化(如图1中),或其中堆叠中的偏移方向可变化(如图2中))。
半导体装置组合件300进一步包含将每一堆叠302及303中的每一裸片304连接到衬底301的线接合321。更特定来说,每一堆叠302及303中的每一裸片304经连接到衬底301上的一或多个接合指部320,一或多个接合指部320各自又(例如,经由通孔322)连接到组合件300的对应一或多个外部触点,例如焊料球323。在此方面,因为任一堆叠302及303中无裸片304位于另一裸片304的悬垂物下方(例如,不同于图1及2),所以可在单次操作(例如,不被另一堆叠操作中断)中形成线接合321,且每一接合指部320可仅连接到单个线接合321(例如,不同于图1)。
根据本技术的一个方面,半导体装置组合件可在衬底上的不同位置中具有半导体裸片的多个瓦片式堆叠。此参考图4更好地可见,图4说明根据本技术的实施例的包含半导体裸片的多个瓦片式堆叠的半导体装置组合件的简化平面图。半导体装置组合件400包含衬底401、半导体裸片404的第一瓦片式堆叠402及半导体裸片404的第二瓦片式堆叠403。第一瓦片式堆叠402经安置于衬底401上的第一位置中,且第二瓦片式堆叠403经安置于从第一位置横向偏移的第二位置中。如参考图4可见,第一瓦片式堆叠402及第二瓦片式堆叠403中的每一者包含八个半导体裸片404。每一堆叠402及403的最底部裸片直接耦合到衬底401,且每一堆叠402及403中的每一裸片404(除最底部裸片之外)沿大致相同方向从紧邻其下方的裸片404偏移达约相同距离(例如,不同于图1及2中所说明的瓦片式堆叠,其中堆叠中的偏移距离可变化(如图1中),或其中堆叠中的偏移方向可变化(如图2中))。
半导体装置组合件400进一步包含将每一堆叠402及403中的每一裸片404连接到衬底401的线接合421。更特定来说,每一堆叠402及403中的每一裸片404通过多个线接合421连接到衬底401上的对应多个接合指部420。因为任一堆叠402及403中无裸片404位于另一裸片404的悬垂物下方(例如,不同于图1及2),所以可在单次操作(例如,不被另一堆叠操作中断)中形成线接合421,且每一接合指部420可仅连接到单个线接合421(例如,不同于图1)。
如上文所陈述,半导体装置组合件中的半导体裸片可包含提供各种不同功能的裸片(例如,逻辑、存储器、传感器等)。在其中瓦片式存储器裸片的堆叠包含于半导体装置组合件中的实施例中,包含存储器裸片的多个堆叠的优点是可将存储器裸片的不同堆叠专用于不同存储器通道(例如,在其中每一堆叠对应于一个通道的1对1关系中,或在其中多个堆叠对应于每一通道或甚至多个通道对应于每一堆叠的n对1或1对n关系中)。
根据本技术的一个方面,与单个较大堆叠相对照,在半导体装置组合件中包含半导体裸片的两个或两个以上瓦片式堆叠的另一优点是在组合件的布局中提供额外灵活性,其可允许额外装置硬件包含于组合件中。例如,半导体装置组合件400包含I/O扩充器440,I/O扩充器440可方便地定位成相邻于半导体裸片404的每一堆叠402及403的接合指部420,以在半导体装置组合件400是封装式存储器装置时促进额外连接性。
根据本技术的一个方面,在半导体装置组合件中提供裸片的多个瓦片式堆叠的又一优点是可实现的封装高度降低(例如,通过使用较少裸片的多个堆叠,而非裸片的单个较高堆叠)。替代地,另一优点可包含使用较厚半导体裸片(例如,其可比较薄裸片更容易制造),同时维持类似于使用具有较多数目个较薄裸片的单个堆叠的半导体装置组合件的封装高度。
根据本技术的一个方面,与单个较大堆叠相对照,在半导体装置组合件中包含半导体裸片的两个或两个以上瓦片式堆叠的额外优点是组合件所经历的翘曲减少及组合件的外部触点上的物理应力对应地减小。在此方面,具有通常被安置于组合件中间的裸片的单个堆叠的组合件在通常位于堆叠的下方及外围内的区域中经历物理应力升高(例如,归因于翘曲及热效应),所述区域对应于封装衬底的大体上中心区域(例如,其中许多组合件焊料接点可专用于发信号及供电)。此会降低组合件与更高级电路(例如,模块板、封装上封装中介层或类似物)之间的焊料接点的可靠性。在其中裸片的两个或两个以上堆叠安置于组合件衬底上的不同位置中的组合件中,组合件中间的物理应力倾向于较低,如果可能,那么在封装的较外围区域中发生应力升高(例如,其中封装触点可仅专用于机械坚固性,且其中成功地操作组合件无需电连接)。
与具有单个堆叠的组合件相比,本技术的又一优点涉及具有半导体裸片的多个堆叠的半导体装置组合件所经历的热改进。在此方面,归因于由硅及底部填充层、胶带附接或其它粘合剂的交替层引起的热障,具有较少裸片(例如,具有较少裸片到裸片接口)的堆叠的热阻抗低于具有较多裸片的堆叠,即使具有较厚裸片的堆叠也是如此。因此,与具有较多半导体裸片的单个堆叠的半导体装置组合件相比,使用改进式热阻抗,具有半导体裸片的多个堆叠的半导体装置组合件可在较大输入功率下操作,同时在可接受温度范围内执行。
尽管在前述实例中已结合半导体裸片的两个瓦片式堆叠来描述及说明半导体装置组合件,但在其它实施例中可包含更多堆叠。例如,图5是根据本技术的实施例的包含半导体裸片的四个瓦片式堆叠的半导体装置组合件的简化平面图。如参考图5可见,半导体装置组合件500包含衬底501及半导体裸片的四个瓦片式堆叠502到505,其中特征类似于上文参考图3及4更详细论述的那些特征。瓦片式堆叠502到505中的每一者经安置于衬底501上的不同位置中(例如,在相邻、非重叠位置中)。尽管在图5中所说明的实例中瓦片式堆叠502到505被展示为彼此间隔开,但在其它实施例中,半导体装置组合件可包含彼此紧邻的瓦片式堆叠(例如,在衬底上的不同非重叠位置中,但其之间无空间)。
尽管在前述实例中已结合各自具有不同偏移方向的半导体裸片的瓦片式堆叠描述及说明半导体装置组合件,但在其它实施例中裸片的一些或所有瓦片式堆叠可共享偏移方向。例如,图6是根据本技术的实施例的包含半导体裸片的多个瓦片式堆叠的半导体装置组合件的简化平面图。如参考图6可见,半导体装置组合件600包含衬底601及半导体裸片的四个瓦片式堆叠602到605,其中特征类似于上文参考图3及4更详细论述的那些特征。瓦片式堆叠602到605中的每一者经安置于衬底601上的不同位置中(例如,在相邻、非重叠位置中),且瓦片式堆叠都共享相同偏移方向。在图7中所说明的又一实施例中,半导体装置组合件700包含衬底701及半导体裸片的四个瓦片式堆叠702到705。一些堆叠共享一个偏移方向(例如,堆叠702及703),且其它堆叠共享相反偏移方向(例如,堆叠704及705)。
尽管在一些实施例中提供半导体裸片的多个瓦片式堆叠可允许仅需要单个线接合步骤的制造方法,但在其它实施例中半导体装置组合件可包含其中裸片偏移方向或裸片偏移距离在单个堆叠内变化的半导体裸片的多个瓦片式堆叠。例如,图8说明根据本技术的实施例的包含半导体裸片的多个瓦片式堆叠的半导体装置组合件的简化截面图。半导体装置组合件800包含衬底801及半导体裸片的两个堆叠802及803。堆叠802及803中的每一者包含瓦片式半导体裸片的群组,其中裸片群组之间的叠置偏移量具有不连续性。尽管这些不连续性可能需要反复堆叠及线接合步骤,但图8中所说明的半导体装置组合件800仍拥有归于半导体装置组合件具有较少半导体裸片的多个堆叠代替较多裸片的单个堆叠的优点(例如,改进式刚性、热性能、功率处置等)。类似地,图9说明根据本技术的实施例的包含半导体裸片的多个瓦片式堆叠的半导体装置组合件的简化截面图。半导体装置组合件900包含衬底901及半导体裸片的两个堆叠902及903。堆叠902及903中的每一者包含瓦片式半导体裸片的群组,其中裸片群组之间的叠置偏移量具有不连续性。尽管这些不连续性可能需要反复堆叠及线接合步骤,但图9中所说明的半导体装置组合件900仍拥有归于半导体装置组合件具有较少半导体裸片的多个堆叠代替较多裸片的单个堆叠的优点(例如,改进式刚性、热性能、功率处置等)。
图10是说明制造半导体装置组合件的方法的流程图。所述方法包含:提供衬底(框1010);在所述衬底上将第一多个半导体裸片堆叠成第一瓦片式堆叠(框1020);及在所述衬底上将第二多个半导体裸片堆叠成第二瓦片式堆叠(框1030)。在此方面,所述第一多个半导体裸片可直接堆叠于所述衬底上的第一位置上,且所述第二多个半导体裸片可直接堆叠于所述衬底上的第二位置上。所述方法进一步包含:将所述第一多个半导体裸片及所述第二多个半导体裸片线接合到所述衬底(框1040),其可在堆叠所述第一瓦片式堆叠及所述第二瓦片式堆叠之后执行;及提供囊封剂以至少部分地囊封所述衬底、所述第一瓦片式堆叠及所述第二瓦片式堆叠(框1050)。所述线接合可在不被任何堆叠中断的单次操作中执行。
所述方法还可进一步包含:将第三多个半导体裸片堆叠成第三瓦片式堆叠;将第四多个半导体裸片堆叠成第四瓦片式堆叠;及在堆叠所述第三瓦片式堆叠及所述第四瓦片式堆叠之后,将所述第三多个半导体裸片及所述第四多个半导体裸片线接合到所述衬底。在一个实施例中,将所述第一多个半导体裸片及所述第二多个半导体裸片线接合到所述衬底可在堆叠所述第三瓦片式堆叠及所述第四瓦片式堆叠之后执行。
尽管在前述实例中,半导体装置组合件已被说明及描述为包含半导体裸片的瓦片式堆叠,但在本技术的其它实施例中,半导体装置组合件可包含利用不同拓扑(例如,垂直堆叠、部分瓦片式堆叠等)及互连技术(例如,TSV、光学互连、电感互连等)的半导体裸片的多个堆叠。
上文参考图3到10所描述的半导体装置组合件中的任一者可并入到无数更大及/或更复杂系统中的任一者中,所述系统的代表性实例是图11中示意性地展示的系统1100。系统1100可包含半导体装置组合件1102、电源1104、驱动器1106、处理器1108及/或其它子系统或组件1110。半导体装置组合件1102可包含大体上类似于上文参考图3到10所描述的半导体装置的那些特征的特征。所得系统1100可执行各种功能中的任一者,例如存储器存储、数据处理及/或其它合适功能。因此,代表性系统1100可包含(但不限于)手持型装置(例如,移动电话、平板计算机、数字阅读器及数字音频播放器)、计算机、车辆、电器及其它产品。系统1100的组件可经容置于单个单元中或经分布于多个互连单元上(例如,通过通信网络)。系统1100的组件还可包含远程装置及各种计算机可读媒体中的任一者。
从前文将了解,本文中已出于说明目描述本发明的特定实施例,但可在不脱离本发明的范围的情况下进行各种修改。因此,除受所附权利要求书限制之外,本发明不受限。
Claims (25)
1.一种半导体装置组合件,其包括:
衬底,其包含多个外部连接件;
半导体裸片的第一瓦片式堆叠,其直接安置于所述衬底上的第一位置上方且经电耦合到所述多个外部连接件的第一子组;
第一I/O扩充器,其对应于所述第一瓦片式堆叠且直接安置在所述衬底上方;
半导体裸片的第二瓦片式堆叠,其直接安置于所述衬底上的第二位置上方且经电耦合到所述多个外部连接件的第二子组;
第二I/O扩充器,其对应于所述第二瓦片式堆叠且直接安置在所述衬底上方;及
囊封剂,其至少部分地囊封所述衬底、所述第一瓦片式堆叠、所述第二瓦片式堆叠、所述第一I/O扩充器及所述第二I/O扩充器,
其中半导体裸片的所述第一瓦片式堆叠以第一1对1关系对应于所述半导体装置组合件的第一存储器通道,
其中半导体裸片的所述第二瓦片式堆叠以第二1对1关系对应于所述半导体装置组合件的第二存储器通道。
2.根据权利要求1所述的半导体装置组合件,其中:
半导体裸片的所述第一瓦片式堆叠是通过第一多个线接合电连接到所述多个外部连接件的所述第一子组,且
半导体裸片的所述第二瓦片式堆叠是通过第二多个线接合电连接到所述多个外部连接件的所述第二子组。
3.根据权利要求1所述的半导体装置组合件,其中:
所述衬底包含对应于所述第一瓦片式堆叠的第一多个接合指部及对应于所述第二瓦片式堆叠的第二多个接合指部,
所述第一多个接合指部中的每一者直接耦合到所述第一多个线接合中的仅一者,且
所述第二多个接合指部中的每一者直接耦合到所述第二多个线接合中的仅一者。
4.根据权利要求1所述的半导体装置组合件,其中所述第一瓦片式堆叠及所述第二瓦片式堆叠包含相同数目个半导体裸片。
5.根据权利要求4所述的半导体装置组合件,其中所述数目是两个、四个、八个或十六个中的一者。
6.根据权利要求1所述的半导体装置组合件,其中:
所述第一瓦片式堆叠包含所述第一瓦片式堆叠的最低半导体裸片及经堆叠于所述第一瓦片式堆叠的所述最低半导体裸片上方的至少一个上半导体裸片,且
所述第一瓦片式堆叠的每一上半导体裸片沿第一方向从正下方的半导体裸片偏移达第一偏移量。
7.根据权利要求6所述的半导体装置组合件,其中:
所述第二瓦片式堆叠包含所述第二瓦片式堆叠的最低半导体裸片及经堆叠于所述第二瓦片式堆叠的所述最低半导体裸片上方的至少一个上半导体裸片,且
所述第二瓦片式堆叠的每一上半导体裸片沿第二方向从正下方的半导体裸片偏移达第二偏移量。
8.根据权利要求7所述的半导体装置组合件,其中所述第一偏移量等于所述第二偏移量。
9.根据权利要求7所述的半导体装置组合件,其中所述第一方向等同于所述第二方向。
10.根据权利要求7所述的半导体装置组合件,其中所述第一方向与所述第二方向相反。
11.根据权利要求7所述的半导体装置组合件,其中所述第一方向与所述第二方向正交。
12.根据权利要求1所述的半导体装置组合件,其进一步包括:
半导体裸片的第三瓦片式堆叠,其直接安置于所述衬底上的第三位置上方且经电耦合到所述多个外部连接件的第三子组;及
半导体裸片的第四瓦片式堆叠,其直接安置于所述衬底上的第四位置上方且经电耦合到所述多个外部连接件的第四子组。
13.根据权利要求12所述的半导体装置组合件,其中:
半导体裸片的第三瓦片式堆叠直接布置在半导体裸片的所述第一瓦片式堆叠上方且经电耦合到所述多个外部连接件的第三子组,且
半导体裸片的所述第四瓦片式堆叠直接布置在半导体裸片的所述第二瓦片式堆叠上方且经电耦合到所述多个外部连接件的第四子组。
14.如权利要求1所述的半导体装置组合件,其进一步包括:
第一裸片附着膜,其在半导体裸片的所述第一瓦片式堆叠与半导体裸片的所述第三瓦片式堆叠之间,所述第一裸片附着膜比在半导体裸片的所述第一瓦片式堆叠中的相邻者之间或在半导体裸片的所述第三瓦片式堆叠中的相邻者之间的任何其他裸片附着膜为厚,及
第二裸片附着膜,其在半导体裸片的所述第二瓦片式堆叠与半导体裸片的所述第四瓦片式堆叠之间,所述第二裸片附着膜比在半导体裸片的所述第二瓦片式堆叠中的相邻者之间或在半导体裸片的所述第四瓦片式堆叠中的相邻者之间的任何其他裸片附着膜为厚。
15.一种制造存储器装置的方法,其包括:
提供衬底;
在所述衬底上,将第一多个半导体裸片堆叠成第一瓦片式堆叠;
在所述衬底上,将第二多个半导体裸片堆叠成第二瓦片式堆叠;
在堆叠所述第一及第二瓦片式堆叠之后,将所述第一及第二多个半导体裸片线接合到所述衬底;
将对应于所述第一瓦片式堆叠的第一I/O扩充器直接安置在所述衬底上方;
将对应于所述第二瓦片式堆叠的第二I/O扩充器直接安置在所述衬底上方;及
提供囊封剂,以至少部分地囊封所述衬底、所述第一瓦片式堆叠、所述第二瓦片式堆叠、所述第一I/O扩充器及所述第二I/O扩充器,
其中半导体裸片的所述第一瓦片式堆叠以第一1对1关系对应于所述半导体装置组合件的第一存储器通道,
其中半导体裸片的所述第二瓦片式堆叠以第二1对1关系对应于所述半导体装置组合件的第二存储器通道。
16.根据权利要求15所述的方法,其中在单个操作中执行所述将所述第一及第二多个半导体裸片线接合到所述衬底,且不会被任何堆叠中断。
17.根据权利要求16所述的方法,其中:
所述第一多个半导体裸片直接堆叠于所述衬底上的第一位置上方,且
所述第二多个半导体裸片直接堆叠于所述衬底上的第二位置上方。
18.根据权利要求16所述的方法,其进一步包括:
将第三多个半导体裸片堆叠成第三瓦片式堆叠;
将第四多个半导体裸片堆叠成第四瓦片式堆叠;及
在堆叠所述第三及第四瓦片式堆叠之后,将所述第三及第四多个半导体裸片线接合到所述衬底。
19.根据权利要求18所述的方法,其中将所述第一及第二多个半导体裸片线接合到所述衬底在堆叠所述第三及第四瓦片式堆叠之后执行。
20.根据权利要求18所述的方法,其中:
半导体裸片的所述第三瓦片式堆叠直接布置在半导体裸片的所述第一瓦片式堆叠上方,且
半导体裸片的所述第四瓦片式堆叠直接布置在半导体裸片的所述第二瓦片式堆叠上方。
21.根据权利要求20所述的方法,其中:
第一裸片附着膜,其在半导体裸片的所述第一瓦片式堆叠与半导体裸片的所述第三瓦片式堆叠之间,所述第一裸片附着膜比在半导体裸片的所述第一瓦片式堆叠中的相邻者之间或在半导体裸片的所述第三瓦片式堆叠中的相邻者之间的任何其他裸片附着膜为厚,及
第二裸片附着膜,其在半导体裸片的所述第二瓦片式堆叠与半导体裸片的所述第四瓦片式堆叠之间,所述第二裸片附着膜比在半导体裸片的所述第二瓦片式堆叠中的相邻者之间或在半导体裸片的所述第四瓦片式堆叠中的相邻者之间的任何其他裸片附着膜为厚。
22.根据权利要求15所述的方法,其中所述衬底包含多个外部连接件,且其中将所述第一多个半导体裸片线接合到所述衬底包括将所述第一多个半导体裸片电耦合到所述多个外部连接件的第一子组。
23.根据权利要求22所述的方法,其中将所述第二多个半导体裸片线接合到所述衬底包括将所述第二多个半导体裸片电耦合到所述多个外部连接件的第二子组。
24.根据权利要求15所述的方法,其中所述第一瓦片式堆叠及所述第二瓦片式堆叠包含相同数目个半导体裸片。
25.根据权利要求24所述的方法,其中所述数目是两个、四个、八个或十六个中的一者。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/806,808 US10312219B2 (en) | 2017-11-08 | 2017-11-08 | Semiconductor device assemblies including multiple shingled stacks of semiconductor dies |
US15/806,808 | 2017-11-08 | ||
PCT/US2018/050075 WO2019094098A1 (en) | 2017-11-08 | 2018-09-07 | Semiconductor device assemblies including multiple shingled stacks of semiconductor dies |
CN201880072433.4A CN111316436A (zh) | 2017-11-08 | 2018-09-07 | 包含半导体裸片的多个瓦片式堆叠的半导体装置组合件 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201880072433.4A Division CN111316436A (zh) | 2017-11-08 | 2018-09-07 | 包含半导体裸片的多个瓦片式堆叠的半导体装置组合件 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN115513190A true CN115513190A (zh) | 2022-12-23 |
Family
ID=66328870
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201880072433.4A Pending CN111316436A (zh) | 2017-11-08 | 2018-09-07 | 包含半导体裸片的多个瓦片式堆叠的半导体装置组合件 |
CN202210992379.3A Pending CN115513190A (zh) | 2017-11-08 | 2018-09-07 | 包含半导体裸片的多个瓦片式堆叠的半导体装置组合件 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201880072433.4A Pending CN111316436A (zh) | 2017-11-08 | 2018-09-07 | 包含半导体裸片的多个瓦片式堆叠的半导体装置组合件 |
Country Status (5)
Country | Link |
---|---|
US (3) | US10312219B2 (zh) |
KR (2) | KR102342277B1 (zh) |
CN (2) | CN111316436A (zh) |
TW (1) | TWI725338B (zh) |
WO (1) | WO2019094098A1 (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10312219B2 (en) * | 2017-11-08 | 2019-06-04 | Micron Technology, Inc. | Semiconductor device assemblies including multiple shingled stacks of semiconductor dies |
KR102708517B1 (ko) * | 2019-10-15 | 2024-09-24 | 에스케이하이닉스 주식회사 | 적층 반도체 칩을 포함하는 반도체 패키지 |
US11456022B2 (en) * | 2020-06-30 | 2022-09-27 | Western Digital Technologies, Inc. | Distributed grouped terminations for multiple memory integrated circuit systems |
US11309281B2 (en) * | 2020-08-26 | 2022-04-19 | Micron Technology, Inc. | Overlapping die stacks for NAND package architecture |
KR20220055112A (ko) | 2020-10-26 | 2022-05-03 | 삼성전자주식회사 | 반도체 칩들을 갖는 반도체 패키지 |
KR20220067572A (ko) | 2020-11-16 | 2022-05-25 | 삼성전자주식회사 | 메모리 패키지 및 이를 포함하는 저장 장치 |
US11502053B2 (en) * | 2020-11-24 | 2022-11-15 | Micron Technology, Inc. | Bond pad connection layout |
KR20230000249A (ko) * | 2021-06-24 | 2023-01-02 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
US11942430B2 (en) * | 2021-07-12 | 2024-03-26 | Micron Technology, Inc. | Stacked die modules for semiconductor device assemblies and methods of manufacturing stacked die modules |
US11869626B2 (en) * | 2021-10-15 | 2024-01-09 | Micron Technology, Inc. | Internal and external data transfer for stacked memory dies |
US12362319B2 (en) * | 2022-05-20 | 2025-07-15 | Micron Technology, Inc. | Cross stack bridge bonding devices and associated methods |
JP2024034905A (ja) * | 2022-09-01 | 2024-03-13 | キオクシア株式会社 | 半導体装置およびその製造方法 |
US20240079369A1 (en) * | 2022-09-06 | 2024-03-07 | Micron Technology, Inc. | Connecting semiconductor dies through traces |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20060041538A (ko) | 2004-11-09 | 2006-05-12 | 삼성전자주식회사 | 단일 에지 패드를 갖는 반도체 칩을 포함하는 반도체 패키지 |
US20060267173A1 (en) * | 2005-05-26 | 2006-11-30 | Sandisk Corporation | Integrated circuit package having stacked integrated circuits and method therefor |
TW200814249A (en) | 2006-09-12 | 2008-03-16 | Chipmos Technologies Inc | Stacked chip package structure with lead-frame having bus bar |
US7687921B2 (en) * | 2008-05-05 | 2010-03-30 | Super Talent Electronics, Inc. | High density memory device manufacturing using isolated step pads |
KR20110138788A (ko) | 2010-06-22 | 2011-12-28 | 하나 마이크론(주) | 적층형 반도체 패키지 |
US8415808B2 (en) * | 2010-07-28 | 2013-04-09 | Sandisk Technologies Inc. | Semiconductor device with die stack arrangement including staggered die and efficient wire bonding |
KR101831692B1 (ko) | 2011-08-17 | 2018-02-26 | 삼성전자주식회사 | 기능적으로 비대칭인 전도성 구성 요소들을 갖는 반도체 소자, 패키지 기판, 반도체 패키지, 패키지 적층 구조물 및 전자 시스템 |
KR20130090173A (ko) * | 2012-02-03 | 2013-08-13 | 삼성전자주식회사 | 반도체 패키지 |
US8796098B1 (en) * | 2013-02-26 | 2014-08-05 | Cypress Semiconductor Corporation | Embedded SONOS based memory cells |
KR20140109134A (ko) * | 2013-03-05 | 2014-09-15 | 삼성전자주식회사 | 멀티-채널을 갖는 반도체 패키지 및 관련된 전자 장치 |
KR102001880B1 (ko) * | 2013-06-11 | 2019-07-19 | 에스케이하이닉스 주식회사 | 적층 패키지 및 제조 방법 |
KR102247916B1 (ko) * | 2014-01-16 | 2021-05-04 | 삼성전자주식회사 | 계단식 적층 구조를 갖는 반도체 패키지 |
US9418974B2 (en) | 2014-04-29 | 2016-08-16 | Micron Technology, Inc. | Stacked semiconductor die assemblies with support members and associated systems and methods |
KR102192848B1 (ko) | 2014-05-26 | 2020-12-21 | 삼성전자주식회사 | 메모리 장치 |
KR102254104B1 (ko) * | 2014-09-29 | 2021-05-20 | 삼성전자주식회사 | 반도체 패키지 |
US9478494B1 (en) * | 2015-05-12 | 2016-10-25 | Harris Corporation | Digital data device interconnects |
US10312219B2 (en) * | 2017-11-08 | 2019-06-04 | Micron Technology, Inc. | Semiconductor device assemblies including multiple shingled stacks of semiconductor dies |
-
2017
- 2017-11-08 US US15/806,808 patent/US10312219B2/en active Active
-
2018
- 2018-09-07 KR KR1020217012444A patent/KR102342277B1/ko active Active
- 2018-09-07 WO PCT/US2018/050075 patent/WO2019094098A1/en active Application Filing
- 2018-09-07 CN CN201880072433.4A patent/CN111316436A/zh active Pending
- 2018-09-07 KR KR1020207015519A patent/KR20200067902A/ko not_active Ceased
- 2018-09-07 CN CN202210992379.3A patent/CN115513190A/zh active Pending
- 2018-09-20 TW TW107133100A patent/TWI725338B/zh active
-
2019
- 2019-04-15 US US16/383,903 patent/US10522507B2/en active Active
- 2019-09-23 US US16/578,592 patent/US11094670B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
KR102342277B1 (ko) | 2021-12-22 |
US10312219B2 (en) | 2019-06-04 |
TW201931549A (zh) | 2019-08-01 |
TWI725338B (zh) | 2021-04-21 |
US10522507B2 (en) | 2019-12-31 |
US20190244930A1 (en) | 2019-08-08 |
KR20210050587A (ko) | 2021-05-07 |
CN111316436A (zh) | 2020-06-19 |
US11094670B2 (en) | 2021-08-17 |
US20200020667A1 (en) | 2020-01-16 |
WO2019094098A1 (en) | 2019-05-16 |
US20190139934A1 (en) | 2019-05-09 |
KR20200067902A (ko) | 2020-06-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11094670B2 (en) | Semiconductor device assemblies including multiple shingled stacks of semiconductor dies | |
KR101906269B1 (ko) | 반도체 패키지 및 그 제조 방법 | |
US11848323B2 (en) | Semiconductor devices with package-level configurability | |
US20090001540A1 (en) | Stackable Package by Using Internal Stacking Modules | |
US11908833B2 (en) | Overlapping die stacks for nand package architecture | |
US11410969B2 (en) | Semiconductor device assemblies including multiple stacks of different semiconductor dies | |
CN101355067A (zh) | 多芯片模块的改进的电连接 | |
KR102736239B1 (ko) | 인터포즈 브리지를 가진 모듈들이 스택된 반도체 패키지 | |
US20160322338A1 (en) | Semiconductor Packages Having Package-On-Package Structures | |
TW201923989A (zh) | 具有探針後可組態度之半導體裝置 | |
CN115224012A (zh) | 具有多个衬底和裸片堆叠的半导体装置 | |
CN113053858A (zh) | 具有扇出边沿的面对面半导体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |