CN115513174A - Semiconductor structures and methods of forming them - Google Patents

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate comprises a first conductive structure and a device structure, the substrate further comprises a first dielectric layer, a second dielectric layer and an etching stop layer, and a resistance layer is arranged in the second dielectric layer; forming a first opening and a second opening in the second dielectric layer, wherein the etching stop layer on the first conductive structure is exposed at the bottom of the first opening, and the resistor layer is exposed at the bottom of the second opening; forming an intermediate conductive film on the exposed surface of the resistance layer by adopting a selective film forming process; after the intermediate conductive film is formed, etching the exposed etching stop layer until the surface of the first conductive structure is exposed; after the exposed etching stop layer is etched, a second conductive structure is formed in the first opening; and forming a third conductive structure in the second opening after etching the exposed etching stop layer. Therefore, the difficulty of the manufacturing process of the semiconductor structure can be reduced, and the performance and the reliability of the semiconductor structure are better.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a forming method thereof.

Background technique

At present, in the semiconductor manufacturing process, an etching process is used to form an opening in the interlayer dielectric layer, and then a conductive material is deposited in the opening to form an electrical connection structure for the electrical connection between semiconductor devices. craft.

However, in existing semiconductor structures, it is difficult to balance the performance and reliability of the semiconductor structure while reducing the difficulty of the manufacturing process of the semiconductor structure.

Contents of the invention

The technical problem to be solved by the present invention is to provide a semiconductor structure and its forming method, so as to improve the performance and reliability of the semiconductor structure while reducing the difficulty of the manufacturing process of the semiconductor structure.

In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate includes a first conductive structure and a device structure, and the substrate also includes a semiconductor structure located between the first conductive structure and the device structure The first dielectric layer, the second dielectric layer on the first dielectric layer, and the etching stop layer between the first dielectric layer and the second dielectric layer, the second dielectric layer has a resistance layer; The second conductive structure in the second dielectric layer, the second conductive structure penetrates the etching stop layer, the second conductive structure is in contact with the top surface of the first conductive structure; the intermediate conductive film in the second dielectric layer, the The intermediate conductive film is also located on the top surface of the resistance layer; the third conductive structure is located in the second medium layer, and the third conductive structure is also located on the surface of the intermediate conductive film.

Optionally, the material of the intermediate conductive film includes fluorine-free tungsten.

Optionally, the thickness of the intermediate conductive film is more than 2 nanometers.

Optionally, the material of the second conductive structure includes tungsten containing fluorine, and the material of the third conductive structure includes tungsten containing fluorine.

Optionally, the material of the first conductive structure includes cobalt.

Optionally, the material of the resistance layer includes titanium nitride.

Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first conductive structure and a device structure, and the substrate further includes a first dielectric layer in between, a second dielectric layer on the first dielectric layer, and an etching stop layer between the first dielectric layer and the second dielectric layer, the second dielectric layer has a resistance layer therein; A first opening and a second opening are formed in the second dielectric layer, the bottom of the first opening exposes the etch stop layer on the first conductive structure, and the bottom of the second opening exposes the resistance layer; using selective Film forming process, forming an intermediate conductive film on the surface of the exposed resistance layer; after forming the intermediate conductive film, etching the exposed etching stop layer until the surface of the first conductive structure is exposed; After etching, a second conductive structure is formed in the first opening; after the exposed etching stop layer is etched, a third conductive structure is formed in the second opening.

Optionally, the material of the intermediate conductive film includes fluorine-free tungsten.

Optionally, the material of the resistance layer includes titanium nitride.

Optionally, the selective film-forming process for forming the fluorine-free tungsten includes a selective atomic layer deposition process.

Optionally, the reactive gas used in the selective atomic layer deposition process includes tungsten pentachloride.

Optionally, the parameters of the selective atomic layer deposition process further include: the reaction gas used also includes hydrogen; the reaction temperature is 350°C-450°C.

Optionally, while forming the second conductive structure, a third conductive structure is formed, wherein the materials of the second conductive structure and the third conductive structure include fluorine-containing tungsten.

Optionally, the process of forming the fluorine-containing tungsten includes a selective metal deposition process.

Optionally, the reaction gas used in the selective metal deposition process includes tungsten hexafluoride.

Optionally, the thickness of the intermediate conductive film is more than 2 nanometers, and the thickness of the intermediate conductive film is smaller than the depth of the second opening.

Optionally, the method for etching the exposed etch stop layer includes: after forming the intermediate conductive film, etching back the exposed etch stop layer until the surface of the first conductive structure is exposed.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the formation process of the semiconductor structure provided by the technical solution of the present invention, after the first opening and the second opening are formed, the second conductive structure and the third conductive structure are formed. Therefore, not only the patterns of the first opening and the second opening can be transferred through one mask layer, but also the number of mask layers and the number of etching steps performed on the second dielectric layer are reduced. Also, the material of the second conductive structure and the material of the third conductive structure can be planarized in one planarization step to form the second conductive structure and the third conductive structure. Therefore, the manufacturing process of the semiconductor structure is simplified and the difficulty of the manufacturing process of the semiconductor structure is reduced. On this basis, since there is an etch stop layer between the first dielectric layer and the second dielectric layer, and before etching the exposed etch stop layer, a selective film-forming process is used, and the exposed resistive layer An intermediate conductive film is formed on the surface. Therefore, on the one hand, the material of the intermediate conductive film is selectively formed on the surface of the resistance layer by using a selective film-forming process, thereby realizing the realization of the intermediate conductive film with simple process steps. Formation. On the other hand, the intermediate conductive film can protect the resistance layer during the process of forming the second conductive structure, reduce the loss of the resistance layer in the process of forming the second conductive structure, and enable the resistance layer to pass through the intermediate conductive film and connect with the third conductive structure. A good electrical connection is formed between them, so that the performance and reliability of the semiconductor structure are good. To sum up, the method for forming the semiconductor structure can reduce the difficulty of the manufacturing process of the semiconductor structure while improving the performance and reliability of the semiconductor structure.

Further, since the material of the intermediate conductive film includes fluorine-free tungsten, the intermediate conductive film and the first conductive structure are both metal materials, therefore, the second conductive structure and the third conductive structure can be formed simultaneously by the same selective metal deposition process. The conductive structure further simplifies the formation process of the semiconductor structure.

Further, since the reactive gas used in the selective atomic layer deposition process includes tungsten pentachloride, the selective atomic layer deposition process has high selectivity for materials, and it is very easy to use titanium nitride, fluorine-containing tungsten, aluminum, etc. Metal surface growth, therefore, when the material of the resistance layer includes the above materials, the material of the intermediate conductive film can be formed on the surface of the resistance layer with high selectivity through the selective atomic layer deposition process, thereby forming the material of the intermediate conductive film Fewer steps, large process window and easy to implement.

Description of drawings

1 to 3 are schematic cross-sectional structure diagrams of each step of a method for forming a semiconductor structure;

FIG. 4 to FIG. 9 are schematic cross-sectional structure diagrams of the formation process of the semiconductor structure according to an embodiment of the present invention.

detailed description

As mentioned in the background, it is difficult for the existing semiconductor structure to reduce the difficulty of the manufacturing process of the semiconductor structure while taking into account the performance and reliability of the semiconductor structure, which will be described in detail below with reference to the accompanying drawings.

1 to 3 are schematic cross-sectional structure diagrams of various steps in a method for forming a semiconductor structure.

Referring to FIG. 1 , a substrate (not shown) is provided, the substrate includes a dielectric layer 100 , and a first conductive layer 110 and a resistive layer 120 are respectively provided in the dielectric layer 100 .

The material of the first conductive layer 110 is cobalt, and the material of the resistance layer 120 is titanium nitride.

Please continue to refer to FIG. 1, a first opening 131 and a second opening 132 are formed in the dielectric layer 100, wherein the bottom of the first opening 131 exposes the top surface of the first conductive layer 110, and the bottom of the second opening 132 exposes the top surface of the resistive layer 120. noodle.

Referring to FIG. 2 , a selective tungsten deposition process is used to form a first plug 140 in the first opening 131 , and the first plug 140 is in contact with the top surface of the first conductive layer 110 .

The material of the first plug 140 includes tungsten, which has low resistance and can effectively reduce the parasitic resistance of the semiconductor structure and improve the performance of the semiconductor structure.

Referring to FIG. 3 , a second plug 150 is formed in the second opening 132 .

As the process node is further reduced, the critical dimensions of the first conductive layer 110 and the resistive layer 120 are reduced, and the device density is increased, so that the critical dimensions of the first opening 131 and the second opening 132 are reduced, and the first opening 131 and the second opening 132 are reduced. The distance between the two openings 132 is reduced, which leads to complex manufacturing process, small process window and high process difficulty for forming the first opening 131 and the second opening 132 respectively with different mask layers.

In the above method, in order to simplify the manufacturing process of the semiconductor structure, the patterns of multiple photoresist layers are transferred to the same mask layer, and the dielectric layer 100 is etched with the same mask layer as a mask, and the second layer is formed at the same time. An opening 131 and a second opening 132 . Therefore, on the one hand, the number of mask layers and the number of etching steps performed on the dielectric layer 100 are reduced. On the other hand, after filling the material of the first plug 140 and the material of the second plug 150, the material of the first plug 140 and the material of the second plug 150 can be planarized in one planarization step, so that The planarization process has few steps and is simple.

However, since the first opening 131 and the second opening 132 are formed at the same time, the surface of the resistance layer 120 is exposed during the formation of the first plug 140, so the selective tungsten deposition process causes damage to the resistance layer 120, on the one hand , resulting in poor performance of the semiconductor structure, and on the other hand, resulting in poor contact between the resistance layer 120 and the second plug 150 , causing a high risk of device connection abnormalities in the semiconductor structure, resulting in poor reliability of the semiconductor structure. Specifically, when pretreatment is performed on the top surface of the first conductive layer 110, the hydrogen and oxygen used in the pretreatment process will react with the material of the resistance layer 120, so that a part of the material of the resistance layer 120 is changed from titanium nitride to rich Titanium (rich Ti), thus, the fluorine-containing reactive gas used in the selective metal deposition process is easy to etch and consume the resistance layer 120, so that the second opening 132 is directly below (as shown in Figure 2 area A), and the second opening The resistance layer 120 on both sides directly below (as shown in area B in FIG. 2 ) is lost, resulting in poor contact between the second plug 150 and the resistance layer 120 (as shown in area C in FIG. 3 ), resulting in a breakdown of the semiconductor structure. Poor performance and reliability.

To sum up, it is difficult to take into account the performance and reliability of the semiconductor structure while reducing the difficulty of the manufacturing process of the semiconductor structure.

In order to solve the above-mentioned technical problems, the embodiment of the present invention provides a semiconductor structure and its formation method. Due to the selective film formation process, an intermediate conductive film is formed on the surface of the exposed resistance layer; after the intermediate conductive film is formed, the exposed Etching the etch stop layer until the surface of the first conductive structure is exposed; after etching the exposed etch stop layer, a second conductive structure is formed in the first opening, and a third conductive structure is formed in the second opening. structure. Therefore, the performance and reliability of the semiconductor structure can be improved while reducing the difficulty of the manufacturing process of the semiconductor structure.

In order to make the above objects, features and beneficial effects of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 4 to FIG. 9 are schematic cross-sectional structure diagrams of the formation process of the semiconductor structure according to an embodiment of the present invention.

Please refer to FIG. 4 , a substrate 200 is provided, and the substrate 200 includes: a first conductive structure 240 and a device structure (not shown), a first dielectric layer 210 between the first conductive structure 240 and the device structure, and a first dielectric layer 210 between the first conductive structure 240 and the device structure. A second dielectric layer 220 on the dielectric layer 210, and an etching stop layer 230 located between the first dielectric layer 210 and the second dielectric layer 220, the second dielectric layer 220 has a resistance layer 250 therein.

The device structure includes one or all of PMOS transistors and NMOS transistors.

The material of the first dielectric layer 210 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbide The combination.

In this embodiment, the material of the first dielectric layer 210 includes silicon oxide.

The material of the second dielectric layer 220 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbide The combination.

In this embodiment, the material of the second dielectric layer 220 includes silicon oxide.

The function of the etching stop layer 230 is, on the one hand, to protect the first dielectric layer 210 and the first conductive structure 240 during the process of forming the resistance layer 250, and reduce the impact of the process of forming the resistance layer 250 on the first dielectric layer 210. and the damage caused by the first conductive structure 240 . On the other hand, as an etching stop layer when the first opening is subsequently formed, the risk of over-etching to the first conductive structure 240 is reduced.

Not only that, the etch stop layer 230 can also protect the first conductive structure during the subsequent formation of the intermediate conductive film, reducing the risk of damage to the first conductive structure caused by the process of forming the intermediate conductive film, thereby improving the performance of the semiconductor structure better.

The material of the etching stop layer 230 is different from that of the first dielectric layer 210 , and the material of the etching stop layer 230 is different from that of the second dielectric layer 220 .

The material of the etch stop layer 230 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbide The combination.

In this embodiment, the material of the etching stop layer 230 includes silicon nitride.

In this embodiment, the thickness of the etching stop layer 230 is above 10 angstroms.

The thickness of the etching stop layer 230 is too small, and it is easy to be consumed to expose the first conductive structure 240 during the subsequent etching process of forming the first opening, causing the first conductive structure 240 to be damaged. Therefore, the etching stop layer 230 has an appropriate thickness, that is, the thickness of the selective etching stop layer 230 is more than 10 angstroms, which can further reduce the risk of damage to the first conductive structure 240 during the etching process for forming the first opening, Improved performance and reliability of semiconductor structures.

In this embodiment, the first conductive structure 240 is electrically interconnected with the device structure.

In this embodiment, the material of the first conductive structure 240 includes cobalt.

The resistance layer 250 is located on the surface of the etching stop layer 230 .

In this embodiment, the material of the resistance layer 250 includes titanium nitride.

The projection of the first conductive structure 240 on the surface of the substrate 200 and the projection of the resistive layer 250 on the surface of the substrate do not overlap.

In this embodiment, the method for forming the first conductive structure 240 and the etching stop layer 230 includes: forming a first conductive opening (not shown) in the first dielectric layer 210; Forming a first conductive film on the surface of a dielectric layer; planarizing the first conductive film until the surface of the first dielectric layer 210 is exposed to form a first conductive structure 240; on the surface of the first dielectric layer 210 and the first conductive structure 240 An etching stop layer 230 is formed on the surface.

The process of forming the first conductive film is at least one of metal plating process, chemical vapor deposition process, atomic layer deposition process and selective metal growth process.

In this embodiment, the method for forming the resistance layer 250 and the second dielectric layer 220 includes: forming a device material layer (not shown) on the surface of the etching stop layer 230; patterning the device material layer to form a resistance Layer 250 : forming a second dielectric layer 220 on the surface of the etching stop layer 230 and the surface of the resistance layer 250 .

Referring to FIG. 5 , a first opening 261 and a second opening 262 are formed in the second dielectric layer 220 , the bottom of the first opening 261 exposes the etch stop layer 230 on the first conductive structure 240 , and the first opening 261 The bottom of the second opening 262 exposes the resistive layer 250 .

The second opening 262 provides a space for the subsequent formation of the intermediate conductive film and the third conductive structure.

The method for forming the first opening 261 and the second opening 262 includes: forming a mask layer 263 on the surface of the second dielectric layer 220; forming a first opening photoresist layer (not shown) on the surface of the mask layer 263, the The first opening photoresist layer exposes at least part of the surface of the mask layer 263 on the first conductive structure 240; using the first opening photoresist layer as a mask to etch the mask layer 263 until the second dielectric layer 220 is exposed surface, a first mask opening 264 is formed in the mask layer 263; a second opening photoresist layer (not shown) is formed on the surface of the mask layer 263, and the second opening photoresist layer exposes the resistance layer 250 At least part of the surface of the mask layer 263 on the surface; the second opening photoresist layer is used as a mask to etch the mask layer 263 until the surface of the second dielectric layer 220 is exposed, and a second mask is formed in the mask layer 263 Opening 265; after forming the first mask opening 264 and the second mask opening 265, use the mask layer 263 as a mask to etch the second dielectric layer 220 until the surface of the etching stop layer 230 and the resistance layer 250 are exposed surface to form a first opening 261 and a second opening 262 .

The process of etching the second dielectric layer 220 includes: one or a combination of a dry etching process and a wet etching process.

In this embodiment, the dry etching process is used to etch the second dielectric layer 220, which is beneficial to improve the morphology of the formed first opening 261 and the second opening 262, thereby improving the performance of the formed semiconductor structure.

It should be understood that the first mask opening 264 may be formed before the second mask opening 265 , and the first mask opening 264 may also be formed before the second mask opening 265 according to the actual sequence requirements of the process steps.

In other embodiments, the method for forming the first opening and the second opening includes: forming a mask layer on the surface of the second dielectric layer; forming an opening photoresist layer on the surface of the mask layer, and the opening photoresist layer exposes At least part of the surface of the mask layer on the first conductive structure and the resistance layer; using the opening photoresist layer as a mask, etch the mask layer until the surface of the second dielectric layer is exposed, forming a first mask in the mask layer film opening and second mask opening; after forming the first mask opening and the second mask opening, use the mask layer as a mask to etch the second dielectric layer until the etching stop layer and the surface of the resistance layer are exposed .

In this embodiment, after the first opening 261 and the second opening 262 are formed, the mask layer 263 is removed.

Referring to FIG. 6 , an intermediate conductive film 270 is formed on the exposed surface of the resistive layer 250 by a selective film forming process.

By adopting a selective film forming process, the formation of the intermediate conductive film 270 can be realized with relatively simple and convenient process steps.

The function of the intermediate conductive film 270 is to protect the resistive layer 250 during subsequent etching of the exposed etching stop layer 230 and formation of the second conductive structure and the third conductive structure.

Since there is an etch stop layer 230 between the first dielectric layer 210 and the second dielectric layer 220, and before the subsequent etching of the exposed etch stop layer 230, an intermediate conductive film 270 is formed on the surface of the exposed resistance layer 250 Therefore, during the process of forming the intermediate conductive film 270, the first conductive structure 240 is covered by the etch stop layer 230, so that the intermediate conductive film 270 can be selectively formed on the surface of the resistance layer 250 by a selective film forming process. materials, and further, the formation of the intermediate conductive film 270 is achieved with simple process steps.

In this embodiment, the material of the intermediate conductive film 270 includes fluorine free tungsten (FFW, Fluorine Free W). Specifically, the material of the intermediate conductive film 270 includes fluorine-free tungsten means: the material of the intermediate conductive film 270 includes tungsten, and the material of the intermediate conductive film 270 does not contain fluorine.

Since the material of the intermediate conductive film 270 includes fluorine-free tungsten, the intermediate conductive film 270 and the first conductive structure 240 are both metal materials. Therefore, the second conductive structure can be formed at the same time with the same selective metal deposition process. structure and the third conductive structure, further simplifying the formation process of the semiconductor structure.

In this embodiment, the selective film forming process includes a selective atomic layer deposition process. The intermediate conductive film 270 formed by the selective atomic layer deposition process has better compactness, so it can better protect the resistance layer 250 .

Specifically, the reaction gas used in the selective atomic layer deposition process includes tungsten pentachloride. Thus, the formation of the material of the third conductive film 272 including fluorine-free tungsten is realized.

Since the reactive gas used in the selective atomic layer deposition process includes tungsten pentachloride, the selective atomic layer deposition process has high selectivity for materials, and it is very easy to be on the surface of metals such as titanium nitride and fluorine-containing tungsten and aluminum. Therefore, when the material of the resistance layer 250 includes the above-mentioned materials (titanium nitride, etc.), the material of the intermediate conductive film 270 can be formed on the surface of the resistance layer 250 with high selectivity through the selective atomic layer deposition process, Therefore, the steps for forming the intermediate conductive film 270 are few, the process window is large, and it is easy to implement.

In this embodiment, the thickness of the intermediate conductive film 270 is more than 2 nanometers, and the thickness of the intermediate conductive film 270 is smaller than the depth of the second opening 262 .

On the one hand, by making the thickness of the intermediate conductive film 270 more than 2 nanometers, the material continuity of the intermediate conductive film 270 is ensured, which is conducive to the complete coverage of the intermediate conductive film 270 on the surface of the resistance layer 250, so as to improve the subsequent formation of the intermediate conductive film 270. When the second conductive structure and the third conductive structure are used, the protection ability of the resistance layer 250 reduces the risk of loss of the resistance layer 250 caused by the subsequent process of forming the second conductive structure and the third conductive structure. On the other hand, the deposition rate of selective atomic layer deposition process is low, and the excessive thickness of the intermediate conductive film 270 not only leads to material waste, but also increases process time and reduces process efficiency. Therefore, selecting an appropriate thickness range of the intermediate conductive film 270, that is, making the thickness of the intermediate conductive film 270 smaller than the depth of the second opening 262 can enable the intermediate conductive film 270 to better protect the resistance layer 250 while avoiding Material waste and increased process efficiency.

In this embodiment, the parameters of the selective film forming process further include: the reaction gas used also includes hydrogen; the reaction temperature is 350°C-450°C.

In this embodiment, the parameters of the selective atomic layer deposition process further include: the gas used also includes nitrogen.

Specifically, during the selective atomic layer deposition process, tungsten pentachloride is injected into the cavity several times, wherein the duration of each injection of tungsten pentachloride is 0.1 to 2 seconds. After feeding tungsten pentachloride each time, nitrogen penetrating is used for purging, and unadsorbed tungsten pentachloride is discharged out of the cavity, wherein, the duration of each feeding nitrogen is 0.5 seconds to 3 seconds. After removing unadsorbed tungsten pentachloride each time, continue to feed hydrogen to react with adsorbed tungsten pentachloride to form a part of the conductive protective film 250 material comprising fluorine-free tungsten, wherein the duration of feeding hydrogen each time is 0.5 seconds to 3 seconds.

By adopting the parameters of the selective film forming process, the thickness of the formed intermediate conductive film 270 can be realized within the thickness range of the intermediate conductive film 270 , thereby taking into account the protection effect on the resistance layer 250 and the process efficiency.

Referring to FIG. 7 , after the intermediate conductive film 270 is formed, the exposed etch stop layer 230 is etched until the surface of the first conductive structure 240 is exposed.

Since the exposed etch stop layer 230 is etched after the formation of the intermediate conductive film 270, the intermediate conductive film 270 can protect the resistance layer 250 during the process of etching the exposed etch stop layer 230, reducing the The risk of damage to the resistance layer 250 caused by the etching process is reduced, thereby improving the performance and reliability of the semiconductor structure.

In this embodiment, the method for etching the exposed etch stop layer 230 includes: after forming the intermediate conductive film 270 , etching back the exposed etch stop layer 230 until the surface of the first conductive structure 240 is exposed.

Since the material of the intermediate conductive film 270 and the material of the second dielectric layer 220 are different from the material of the etch stop layer 230, during the process of etching the exposed etch stop layer 230, the etching process can While the etch stop layer 230 has a relatively high etch rate, it also has a relatively low etch rate for the material of the intermediate conductive film 270 and the material of the second dielectric layer 220, thus, the exposed material can be etched by etching back. The etch stop layer 230.

Since the exposed etch stop layer 230 can be etched by etching back after the formation of the intermediate conductive film 270, the photoresist layers and mask layers that need to be used in the semiconductor manufacturing process are reduced, thereby simplifying the semiconductor manufacturing process. The manufacturing process of the structure.

The etching process for the exposed etching stop layer 230 includes: one or a combination of a dry etching process and a wet etching process.

In this embodiment, the exposed etching stop layer 230 is etched by a dry etching process, which is beneficial to improving the morphology of the semiconductor structure, thereby improving the performance of the formed semiconductor structure.

After etching the exposed etch stop layer 230 , a second conductive structure is formed in the first opening 261 , and a third conductive structure is formed in the second opening 262 .

Because after the first opening 261 and the second opening 262 are formed, the second conductive structure and the third conductive structure are formed. Therefore, not only the patterns of the first opening 261 and the second opening 262 can be transferred through a mask layer (the mask layer 263 shown in FIG. 5 ), the number of mask layers and the second dielectric layer 220 the number of etching steps performed. Also, the material of the second conductive structure and the material of the third conductive structure can be planarized in one planarization step to form the second conductive structure and the third conductive structure. Therefore, the manufacturing process of the semiconductor structure is simplified and the difficulty of the manufacturing process of the semiconductor structure is reduced.

On this basis, since there is an etch stop layer 230 between the first dielectric layer 220 and the second dielectric layer 230, and before etching the exposed etch stop layer 230, a selective film-forming process is used. An intermediate conductive film 270 is formed on the exposed surface of the resistive layer 250 . Therefore, on the one hand, the material of the intermediate conductive film 270 is selectively formed on the surface of the resistance layer 250 by using a selective film forming process, thereby realizing the formation of the intermediate conductive film 270 with simple process steps. On the other hand, the intermediate conductive film 270 can protect the resistive layer 250 during the process of forming the second conductive structure, reduce the loss of the resistive layer 250 in the process of forming the second conductive structure, and enable the resistive layer 250 to pass through the intermediate conductive film 270. A good electrical connection is formed between the third conductive structures, thus, the performance and reliability of the semiconductor structure are good.

To sum up, the method for forming the semiconductor structure can reduce the difficulty of the manufacturing process of the semiconductor structure while improving the performance and reliability of the semiconductor structure.

For the specific process of forming the second conductive structure and the third conductive structure, please refer to FIG. 8 to FIG. 9 .

Referring to FIG. 8 , after etching the exposed etch stop layer 230 , a pretreatment step is performed on the exposed surface of the first conductive structure 240 and the surface of the intermediate conductive film 270 .

Through the pretreatment step, the natural oxide film and residual pollutants on the surface of the first conductive structure 240 and the surface of the intermediate conductive film 270 can be removed, so as to improve the performance and reliability of the semiconductor structure.

Since the pretreatment step is performed after the intermediate conductive film 270 is formed on the surface of the resistance layer 250, the intermediate conductive film 270 can protect the resistance layer 250 in the pretreatment step, avoiding the pretreatment step. The hydrogen and oxygen used in the process react with the material of the resistance layer 250, avoiding the transformation of a part of the material of the resistance layer 250 from titanium nitride to rich titanium, thereby improving the performance and reliability of the semiconductor structure. At the same time, the risk of etching the titanium-rich material by the reactive gas in the subsequent process of forming the materials of the second conductive structure and the third conductive structure is also avoided. Thus, the intermediate conductive film 270 can protect the resistive layer 250 during the process of forming the second conductive structure, reduce the loss of the resistive layer 250 in the process of forming the second conductive structure, and enable the resistive layer 250 to pass through the intermediate conductive film 270 and communicate with the first conductive layer. A good electrical connection is formed between the three conductive structures, so that the performance and reliability of the semiconductor structure are good.

Please refer to FIG. 9, after the pretreatment step, a selective metal deposition process is used to deposit a conductive material layer (not shown) in the first opening 261 and the second opening 262, and the surface of the conductive material layer is higher than the first opening 262. The surface of the second dielectric layer 220; a sacrificial layer (not shown) is formed on the surface of the second dielectric layer 220 and the surface of the conductive material layer, the surface of the sacrificial layer is higher than the surface of the conductive material layer; the sacrificial layer and the conductive material layer are planarized, Until the surface of the second dielectric layer 220 is exposed, the second conductive structure 281 is formed in the first opening 261 , and the third conductive structure 282 is formed in the second opening 262 .

Specifically, in this embodiment, the third conductive structure 282 is formed at the same time as the second conductive structure 281 is formed, thereby further simplifying the manufacturing process.

In this embodiment, the material of the second conductive structure 281 includes fluorine-containing tungsten, and the material of the third conductive structure 282 includes fluorine-containing tungsten. Specifically, the material of the second conductive structure 281 and the third conductive structure 282 includes fluorine-containing tungsten means: the material of the second conductive structure 281 and the third conductive structure 282 includes tungsten, and the second conductive structure 281 and the third conductive structure The material of structure 282 contains fluorine element.

Specifically, the reaction gas used in the selective metal deposition process includes tungsten hexafluoride. Therefore, the materials of the second conductive structure 281 and the third conductive structure 282 contain fluorine element.

In other embodiments, the process of forming the second conductive structure and the third conductive structure includes: a metal plating process or a chemical vapor deposition process.

In other embodiments, the materials of the second conductive structure and the third conductive structure include: a combination of one or more of copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum .

In this embodiment, the sacrificial layer provides sacrificial material for the planarization process. It should be understood that the sacrificial layer will be removed during the planarization process.

In this embodiment, the planarization process includes a chemical mechanical polishing process.

Correspondingly, an embodiment of the present invention also provides a semiconductor structure formed by the above method, please continue to refer to 9, the semiconductor structure includes: a substrate 200 (as shown in FIG. 4 ), and the substrate 200 includes a first conductive structure 240 and the device structure (not shown), the first dielectric layer 210 between the first conductive structure 240 and the device structure, the second dielectric layer 220 on the first dielectric layer 210, and the first dielectric layer 210 and The etch stop layer 230 between the second dielectric layer 220, the second dielectric layer 220 has a resistance layer 250 therein; the second conductive structure 281 located in the second dielectric layer 220, the second conductive structure 281 penetrates through the etched An etch stop layer 230, the second conductive structure 281 is in contact with the top surface of the first conductive structure 240; an intermediate conductive film 270 located in the second dielectric layer 220, the intermediate conductive film 270 is also located on the top surface of the resistance layer 250 the third conductive structure 282 located in the second dielectric layer 220, the third conductive structure 282 is also located on the surface of the intermediate conductive film 270;

The device structure includes one or all of PMOS transistors and NMOS transistors.

The material of the first dielectric layer 210 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbide The combination.

In this embodiment, the material of the first dielectric layer 210 includes silicon oxide.

The material of the second dielectric layer 220 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbide The combination.

In this embodiment, the material of the second dielectric layer 220 includes silicon oxide.

The material of the etching stop layer 230 is different from that of the first dielectric layer 210 , and the material of the etching stop layer 230 is different from that of the second dielectric layer 220 .

The material of the etch stop layer 230 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbide The combination.

In this embodiment, the material of the etching stop layer 230 includes silicon nitride.

In this embodiment, the thickness of the etching stop layer 230 is above 10 angstroms.

The projection of the first conductive structure 240 on the surface of the substrate 200 and the projection of the resistive layer 250 on the surface of the substrate do not overlap.

In this embodiment, the first conductive structure 240 is electrically interconnected with the device structure.

In this embodiment, the material of the first conductive structure 240 includes cobalt.

The resistance layer 250 is located on the surface of the etching stop layer 230 .

In this embodiment, the material of the resistance layer 250 includes titanium nitride.

In this embodiment, the material of the intermediate conductive film 270 includes fluorine-free tungsten.

In this embodiment, the thickness of the intermediate conductive film 270 is more than 2 nanometers, and the thickness of the intermediate conductive film 270 is smaller than the depth of the second opening 262 (as shown in FIG. 6 ).

In this embodiment, the material of the second conductive structure 281 includes fluorine-containing tungsten, and the material of the third conductive structure 282 includes fluorine-containing tungsten.

In other embodiments, the materials of the second conductive structure and the third conductive structure include: a combination of one or more of copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum .

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (17)

1. A semiconductor structure, characterized in that, comprising: a substrate, the substrate comprising a first conductive structure and a device structure, the substrate further comprising a first dielectric layer located between the first conductive structure and the device structure, a second dielectric layer located on the first dielectric layer, and an etch stop layer located between the first dielectric layer and the second dielectric layer, the second dielectric layer having a resistance layer therein; a second conductive structure located in the second dielectric layer, the second conductive structure penetrates the etch stop layer, and the second conductive structure is in contact with the top surface of the first conductive structure; An intermediate conductive film located in the second dielectric layer, the intermediate conductive film is also located on the top surface of the resistance layer; a third conductive structure located in the second dielectric layer, the third conductive structure is also located in the intermediate conductive film surface. 2. The semiconductor structure according to claim 1, wherein the material of the intermediate conductive film comprises fluorine-free tungsten. 3. The semiconductor structure according to claim 1, wherein the thickness of the intermediate conductive film is more than 2 nanometers. 4. The semiconductor structure according to claim 1, wherein the material of the second conductive structure includes tungsten containing fluorine, and the material of the third conductive structure includes tungsten containing fluorine. 5. The semiconductor structure of claim 1, wherein the material of the first conductive structure comprises cobalt. 6. The semiconductor structure of claim 1, wherein a material of the resistive layer comprises titanium nitride. 7. A method for forming a semiconductor structure, comprising: A substrate is provided, the substrate includes a first conductive structure and a device structure, and the substrate further includes a first dielectric layer located between the first conductive structure and the device structure, a second dielectric layer located on the first dielectric layer, and an etch stop layer located between the first dielectric layer and the second dielectric layer, the second dielectric layer having a resistance layer therein; forming a first opening and a second opening in the second dielectric layer, the bottom of the first opening exposes the etching stop layer on the first conductive structure, and the bottom of the second opening exposes the resistance layer; Selective film forming process is used to form an intermediate conductive film on the surface of the exposed resistance layer; After forming the intermediate conductive film, etching the exposed etching stop layer until the surface of the first conductive structure is exposed; forming a second conductive structure in the first opening after etching the exposed etch stop layer; After etching the exposed etch stop layer, a third conductive structure is formed in the second opening. 8. The method for forming a semiconductor structure according to claim 7, wherein the material of the intermediate conductive film comprises fluorine-free tungsten. 9. The method for forming a semiconductor structure according to claim 8, wherein the material of the resistance layer comprises titanium nitride. 10 . The method for forming a semiconductor structure according to claim 9 , wherein the selective film-forming process for forming the fluorine-free tungsten comprises a selective atomic layer deposition process. 11 . 11. The method for forming a semiconductor structure according to claim 10, wherein the reactive gas used in the selective atomic layer deposition process comprises tungsten pentachloride. 12 . The method for forming a semiconductor structure according to claim 11 , wherein the parameters of the selective atomic layer deposition process further include: the reaction gas used also includes hydrogen; and the reaction temperature is 350°C-450°C. 13. The method for forming a semiconductor structure according to claim 8, wherein a third conductive structure is formed at the same time as the second conductive structure is formed, wherein the materials of the second electrical structure and the third conductive structure include Fluorinated tungsten. 14. The method for forming a semiconductor structure according to claim 13, wherein the process of forming the fluorine-containing tungsten comprises a selective metal deposition process. 15. The method for forming a semiconductor structure according to claim 14, wherein the reaction gas used in the selective metal deposition process contains tungsten hexafluoride. 16. The method for forming a semiconductor structure according to claim 7, wherein the thickness of the intermediate conductive film is more than 2 nanometers, and the thickness of the intermediate conductive film is smaller than the depth of the second opening. 17. The method for forming a semiconductor structure according to claim 7, wherein the method for etching the exposed etch stop layer comprises: after forming the intermediate conductive film, etching back the exposed etch stop layer, until the surface of the first conductive structure is exposed.

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