CN115498013B - A method for preparing a termination region of a power chip, a structure of the termination region, and a power chip - Google Patents

Abstract

A preparation method of a power chip termination region, a termination region structure and a power chip, wherein the preparation method comprises the following steps: providing an N-type substrate; forming a P+ grounding ring on the N-type substrate; forming a field oxide layer correspondingly at the position of the N-type substrate corresponding to the termination region; the termination region comprises a corner region and a parallel region, the parallel region is provided with a first P-type ring structure, the corner region is provided with a second P-type ring structure, and the first P-type ring structure and the second P-type ring structure are positioned in the field oxide layer region. The technical scheme has the beneficial effects that through the structural arrangement of the parallel area and the corner area of the termination area, the P+ grounding ring determines the first electric field intensity of the corner, and the electric field intensity can be adjusted by the first P-type ring P+ grounding ring, so that the design can use the minimum curvature, the electric field intensity is increased by avoiding the power line crowding caused by the corner, the width of the field termination area can be effectively reduced, and the total area of the chip is reduced, thereby reducing the cost.

Description

A method for preparing a termination region of a power chip, a structure of the termination region, and a power chip

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a termination region of a power chip and a method for preparing a power chip.

Background technique

The insulated gate bipolar transistor (IGBT) is a new type of power electronic device that combines MOS field effect and bipolar transistor. It not only has the advantages of large input resistance, easy drive and simple control of MOSFET, but also has the advantages of low on-state voltage and large on-state current of bipolar transistor. In the on state, the current is mainly conducted by the cell region; when the block is closed, the device needs to withstand a certain voltage resistance, and its voltage resistance depends on the location of the electric field distribution inside the device where the high electric field spike accumulates and collapses. It has now become one of the core components in modern power electronic circuits and is widely used in transportation, energy, industry, household appliances and other fields. Most of the application scenarios of IGBT are used under high power and high current, and many times multiple chips need to be connected in parallel, so the consistency of parameters is very high.

However, the structure of the entire chip includes two parts: the cell area and the termination area. The design rule of the device cell area is that the cell area of the device itself is a plane composed repeatedly in the two-dimensional direction, but the edge of the cell area loses its symmetry, so a termination area structure is needed to dissipate the electric field distribution of the device when it is turned off, so that the device can meet the rated withstand voltage requirements. Therefore, in the design of the device, it is necessary to pay attention to the distribution of the electric field inside its cell and the boundary of the termination area. Based on this consideration, the main termination area structures of current technology are: field plate structure (Field Plate), floating ring (Floating Ring), junction boundary extension (Junction Termination Extension) and reduced surface electric field structure (ReSurf), which mainly extends the junction depletion area of the boundary as far as possible to reach the edge breakdown voltage value. However, this design method can still cope with devices with lower rated voltages. For devices with higher rated voltages, the design cost of the device will be higher, and the efficiency will be further reduced.

Summary of the invention

In view of the above problems existing in the termination region in the prior art, a method for preparing a power chip termination region is provided for improving the withstand voltage of the termination region in a high-power chip.

Another object of the present invention is to provide a method for preparing a power chip for improving the withstand voltage of the termination region in a high-power chip.

The specific technical solutions are as follows:

A method for preparing a termination region of a power chip, comprising the following steps:

Providing an N-type substrate;

forming a P+ grounding ring on the N-type substrate;

Forming a field oxide layer at a position corresponding to the termination region of the N-type substrate;

The termination area includes a corner area and a parallel area. The parallel area is provided with a first P-type ring structure. The corner area is provided with a second P-type ring structure. The first and second P-type ring structures are located in a non-field oxide layer area.

Preferably, the P-type ring is linearly arranged in the silicon surface exposed between the two field oxide layers.

Preferably, the first P+ grounding ring between the termination region and the cell region is located at the intersection of the corner region and the flat edge region of the termination region.

Preferably, the method of forming the P+ grounding ring includes:

Determine the first location of the P+ ground ring domain;

Exposing the first position using mask 1;

A predetermined dose of P-type ions is implanted into the exposed first position.

Preferably, the method for forming the field oxide layer comprises:

determining a second position of the field oxide layer;

Exposing the second position using a second mask;

Etching the exposed second position to form a first groove;

The field oxide layer is deposited in the first trench.

Preferably, the method for forming the P-type ring includes:

Placing a third photomask on the top of the N-type substrate, wherein the third photomask has a predetermined number of through holes at positions corresponding to positions other than the field oxide layer, and predetermined intervals are provided between the through holes;

Implanting a predetermined dose of P-type ions into the through hole;

A P-type ring is formed by a wet oxidation process and buried in a position other than the field oxide layer;

The oxide layer position is exposed through mask 4, and a predetermined dose of arsenic ions is implanted.

Preferably, the implantation dose of the P-type ions is: boron /100KeV /4.0-8.0E14cm-2.

Preferably, the implantation dose of the P-type ions is: boron /360KeV /1.0-4.0E14cm-2.

Also included is a structure of a termination area of a power chip, which includes:

A P+ grounding ring is formed on the N-type substrate;

Forming a field oxide layer at a position corresponding to the termination region of the N-type substrate;

The termination area includes a corner area and a parallel area. The parallel area is provided with a first P-type ring structure. The corner area is provided with a second P-type ring structure. The first and second P-type ring structures are located in a non-field oxide layer area.

Also included is a power chip, wherein the termination region structure of the power chip adopts the termination region structure as described in claim 9.

The above technical solution has the following advantages or beneficial effects:

Through the parallel area and corner area structure setting of the termination area, the P+ grounding ring determines the first electric field strength of the corner. The electric field strength can be adjusted by the first P-type ring P+ grounding ring, so that the design can use a larger curvature to avoid the crowding of power lines caused by the corners and increase the electric field strength. It can effectively reduce the width of the field termination area and thus reduce the total chip area and reduce costs;

It can suppress the interface charge and mobile ion ability of the silicon/oxide layer, which will cause the breakdown voltage to drop. It should be noted that most of the time when the voltage breakdown is caused by the bend, the arc of the bend is increased to reduce the electric field strength or the spacing of the P-type ring in the termination area is increased to increase the breakdown voltage value, which will increase the chip cost. However, this method does not require the addition of a P+ grounding ring. The concentration and mask of the P-type ring at the bend can be adjusted, the P+ concentration and spacing design can be used to optimize the electric field strength, or the polycrystalline silicon field plate extension method can be used to introduce the electric field into the spaced field oxide layer area to reduce the breakdown problem.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the present invention will be described more fully with reference to the attached drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

FIG1 is a schematic flow diagram of an embodiment of a method for preparing a termination region of a power chip according to the present invention;

FIG2 is a schematic structural diagram of a parallel region in an embodiment of a method for preparing a termination region of a power chip according to the present invention;

FIG3 is a schematic structural diagram of a corner area in an embodiment of a method for preparing a termination area of a power chip according to the present invention;

FIG4 is a schematic structural diagram of a corner area in an embodiment of a method for preparing a termination area of a power chip according to the present invention;

FIG5 is a schematic structural diagram of a corner area in an embodiment of a method for preparing a termination area of a power chip according to the present invention;

6-11 are partial exploded structural schematic diagrams of corresponding process schematic diagrams of an embodiment of a method for preparing a termination region of a power chip according to the present invention;

FIG12 is a schematic structural diagram of a termination region B and a cell region A in an embodiment of a method for preparing a termination region of a power chip according to the present invention;

Detailed ways

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

As shown in FIG1 , an embodiment of a method for preparing a termination region of a power chip includes the following steps:

An N-type substrate 1 is provided; the material of the N-type substrate 1 is an N-type substrate with a base concentration of 1.0e14 cm-3 in the lattice direction;

A P+ grounding ring is formed on the N-type substrate 1;

A field oxide layer 3 is formed at a position corresponding to the termination region of the N-type substrate 1;

As shown in FIG. 2-3 , the termination region includes a corner region and a parallel region. The parallel region is provided with a first P-type ring structure, and the corner region is provided with a second P-type ring structure. The first and second P-type ring structures are located outside the field oxide layer 3 region.

It should be noted that the parallel area is shown in FIG2 , and the direction shown in FIG2 is a schematic diagram of the design of the unit flat area of the four flat sides of the chip;

The middle STI Region can be completed in two ways

1.STIFOX process

2. STI + TEOS Oxide deposited process

The silicon-based surface exposed in the middle may be implanted with a Linear P TOP Ring (a linear P-type ring at the top position) or a Linear P burrier Ring (a buried P-type ring) structure, etc. In this embodiment, a buried P-type ring is preferred.

The corner area is shown in Figure 3, and the layout design diagram of the corners of the chip is shown in Figure 4. The first floating field ring spacing extending or connected to the field plate of P+ is corrected, or the polysilicon field plate extending from the top of the P+ grounding ring area reaches the middle field oxide layer 3 area as shown in Figure 5.

Power semiconductor devices include planar gate/trench gate MOSFET transistors, insulated gate bipolar transistors (IGBTs), rectifiers and synchronous rectifiers. These semiconductor device chips (dies) are divided into three parts: active area, gate area and field termination area according to the function of the IGBT chip. The active area and gate area, also known as the cell area, are the functional areas of the chip, which mainly affect the voltage and current related parameters of the chip, such as: on-voltage, gate voltage, switching and short-circuit characteristics, etc. The field termination area of the current technology is the edge area of the chip. The terminal structure combined with field limiting rings (FLRs) and field plates (FPs) is generally used to provide a passive area for connection and channel cutoff. It mainly minimizes the electric field around the active area and is not used for conducting current. Generally, by increasing the number and width of the field limiting rings and the length of the field plates, the device's voltage resistance can be improved. In addition, in order to improve the high-temperature performance of the chip, semi-insulating materials such as oxygen-doped semi-insulating polycrystalline silicon (SIPOS) are used to improve the high-temperature voltage resistance of the chip, effectively block ion contamination of the device, and improve the reliability of the device.

In the prior art, the design of a field termination region with a higher breakdown voltage capability than the active region is mostly determined by selecting the appropriate ring width, number and length of the field plate. However, there is a nonlinear relationship between the device's withstand voltage and the number of rings, ring width and field plate length. The value increases with the rated voltage of the device. For example, for turbines and hydroelectric generators, the voltage is 3300V, or 6500V and above, and the required field termination region withstand voltage width will inevitably increase. Therefore, how to design an optimized termination region structure that can improve the ion resistance is a major technical difficulty.

This application is to deal with the problem that the rated voltage of the device is getting higher and higher, and the withstand voltage width of the field termination area is bound to increase, which further makes the device larger and larger and the cost increases. It uses the structural setting of the parallel area and the corner area of the termination area, including the setting of the P-type ring, to increase the P area depletion area, so the distance can be shortened, and further set the N ion layer above the P-type ring. The N ion layer can effectively suppress the interface charge and mobile ion ability of the silicon/oxide layer, which will cause the breakdown voltage to drop.

It should be noted that the preparation process of the termination zone corresponds to that shown in Figures 6-11:

In a preferred embodiment, the P-type ring is linearly arranged in the silicon surface exposed between the two field oxide layers 3 in the termination region.

In a preferred embodiment, as shown in FIG12 , the first P+ grounding ring between the termination region B and the cell region A is located at the intersection of the first corner region and the flat edge region of the termination region, and further, the spacing between the two is 1.0-4.0 um. The schematic diagram of the structure of the termination region B and the cell region A is shown in FIG12 .

In this embodiment, the corner area P+ and the flat area P+ have a higher electric field strength due to the curvature radius, and the corner area P+ is improved to enlarge the curvature radius to reduce the electric field strength, and the electric field strength of the corner area is optimized in coordination with the linear P-type ring adjustment. The existing processing method directly extends the flat area design to the corner area, which is why the termination area failure point often occurs at the junction of the corner area or on the corner area.

In a preferred embodiment, the method for forming a P+ grounding ring includes: determining a first position of a P+ grounding ring region; exposing the first position using a photomask; and implanting a predetermined dose of P-type ions into the exposed first position. Preferably, the implantation dose of the P-type ions is: boron /100KeV /4.0-8.0E14cm-2.

In a preferred embodiment, the method for forming the field oxide layer 3 includes: determining a second position of the field oxide layer 3; exposing the second position using a second photomask; etching the exposed second position to form a first groove;

A field oxide layer 3 is deposited in the first trench. In this embodiment, the first trench can be formed by using a LOCOSFOX process.

In a preferred embodiment, the method for forming a P-type ring includes:

The photomask 3 is placed on the top of the N-type substrate 1; the photomask 3 has a predetermined number of through holes at positions corresponding to the non-field oxide layer 3, and predetermined intervals are set between the through holes;

A predetermined dose of P-type ions is implanted into the through hole. Preferably, the implantation dose of the P-type ions is boron /100KeV /4.0-8.0E14cm-2.

A P-type ring is formed by a wet oxidation process and buried under the field oxide layer 3;

The oxide layer position is exposed through mask 4, and a predetermined dose of arsenic ions, Arsenic /2.0e12cm-2/100-200KeV, is implanted.

The technical solution of the present invention also includes an embodiment of a termination area of a power chip, which includes:

A P+ grounding ring is formed on the N-type substrate 1;

A field oxide layer 3 is formed at a position corresponding to the termination region of the N-type substrate 1;

The termination region includes a corner region and a parallel region, the parallel region is provided with a first P-type ring structure, the corner region is provided with a second P-type ring structure, and the first and second P-type ring structures are located in a region other than the field oxide layer 3 .

The technical solution of the present invention also includes an embodiment of a power chip, wherein the termination region structure of the power chip adopts the above-mentioned termination region structure.

The technical aspects of the present invention also include an embodiment of a method for preparing a power chip, as shown in FIGS. 6-11 , which includes the following steps:

Providing an N-type substrate 1;

Forming a P+ grounding ring on the N-type substrate 1;

A field oxide layer 3 is formed at a position corresponding to the termination region of the N-type substrate 1;

The termination region includes a corner region and a parallel region, the parallel region is provided with a first P-type ring structure, the corner region is provided with a second P-type ring structure, and the first and second P-type ring structures are located in a region other than the field oxide layer 3;

Continue to form a polycrystalline silicon layer on the top of the substrate 1 and extend to the field oxide layer 3;

Performing a backside process to sequentially form a cutoff layer and a P-type layer on the bottom of the substrate 1 facing away from the polycrystalline silicon layer;

Continue to perform metal layer layout on the polysilicon layer.

In this embodiment, the preparation process of the termination region has been described in detail in the above-mentioned preparation process of the termination region, and will not be repeated here.

The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. A method for fabricating a termination region of a power chip, comprising the steps of:

Providing an N-type substrate;

forming a P+ grounding ring on the N-type substrate;

Forming field oxide layers at intervals corresponding to the positions of the corresponding termination areas of the N-type substrate;

the termination region comprises a corner region and a parallel region, the parallel region is provided with a first P-type ring structure, the corner region is provided with a second P-type ring structure, and the first P-type ring structure and the second P-type ring structure are positioned in the N-type substrate and are not in the field oxide layer region;

the second P-type ring structure and the field oxide layer are alternately arranged at intervals;

The first and second P-type rings are linearly arranged in the silicon surface exposed between the two field oxide layers;

The first P+ grounding ring between the termination region and the cell region is arranged at the junction of the corner region and the parallel region of the termination region.

2. The method of claim 1, wherein the method of forming the p+ ground ring comprises:

Determining a first position of the P+ grounding ring region;

Exposing the first position by using a mask;

Implanting P-type ions at a predetermined dose to the exposed first location.

3. The method of manufacturing according to claim 1, wherein the method of forming the field oxide layer comprises:

determining a second location of the field oxide layer;

Exposing the second position by using a second photomask;

etching the exposed second position to form a first groove;

And depositing and forming the field oxide layer in the first groove.

4. The method of manufacturing according to claim 1, wherein the method of forming the P-type ring comprises:

Placing a third photomask on the top of the N-type substrate, wherein the third photomask is provided with a preset number of through holes corresponding to the positions of the field oxide layers, and preset intervals are arranged among the through holes;

implanting P-type ions with preset doses into the through holes;

And forming a P-type ring by adopting a wet oxidation process and burying the P-type ring at a position which is not the field oxide layer.

5. The method of claim 2, wherein the P-type ions are implanted at a dose of: the boun/100 KeV/4.0-8.0E14cm-2.

6. The method of claim 4, wherein the P-type ions are implanted at a dose of: the boron/360 KeV/1.0-4.0E14cm-2.

7. A structure of a termination region of a power chip, wherein a method for manufacturing the structure of the termination region of the power chip is manufactured by using the manufacturing method of any one of claims 1 to 6, and the structure of the termination region of the power chip includes:

a P+ grounding ring is formed on the N-type substrate;

forming a field oxide layer correspondingly at the position of the N-type substrate corresponding to the termination region;

The termination region comprises a corner region and a parallel region, the parallel region is provided with a first P-type ring structure, the corner region is provided with a second P-type ring structure, and the first P-type ring structure and the second P-type ring structure are positioned in the field oxide layer region.

8. A power chip, wherein the termination region structure of the power chip adopts the termination region structure of claim 7.