CN115497932A - Bidirectional TVS device and preparation method thereof - Google Patents

Abstract

Disclosed is a bidirectional TVS device and its preparation method. The device comprises: a substrate of a first doping type; an epitaxial layer of a second doping type located on the substrate, wherein the second doping type and the first The doping type is opposite; the isolation structure extends from the surface of the epitaxial layer into the substrate, and defines mutually isolated first regions, second regions, third regions, fourth regions, and The fifth area; wherein, the first diode, the second diode, the third diode and the fourth diode are respectively formed in the first area, the second area, the third area, and the fourth area, and in A triode is formed in the fifth region; and a metal interconnection structure, connecting the cathodes of the first diode and the third diode to the first potential of the triode, and connecting the cathodes of the second diode and the fourth diode The anode is connected at the second potential of the triode.

Description

A kind of bidirectional TVS device and preparation method thereof

technical field

The invention relates to the technical field of semiconductors, in particular to a bidirectional TVS device and a preparation method thereof.

Background technique

Transient Voltage Suppressor (TVS) device or Electro-Static Discharge (ESD) protection device is a voltage clamping overvoltage protection device used to protect electronic equipment from transient high energy impact damage , can change the high impedance between its two poles to low impedance at the speed of picoseconds, absorb surge power up to several thousand watts, so as to avoid damage to electronic equipment.

Traditional TVS devices are basically Zener tube type structures, and the manufacturing process is relatively simple. Generally, a PN junction is directly formed on a P+ substrate/N+ substrate through heterogeneous doping. Traditional TVS devices are mainly used in power supply, switch, and audio ports in consumer electronics products (such as mobile phones, computers, digital cameras, etc.). Generally above 20pF. But for the protection of high-speed communication ports (such as USB3.0 port, DisplayPort port, SATA3.0 port, HDMI2.0 port), traditional TVS devices are not suitable, because high-speed communication has extremely high data transmission rate, such as The data transmission rate of the industrial automation network is greater than 480M/s, and some high-speed data transmission rates reach more than 10G/s, which requires the TVS device capacitance of the line protection to be extremely low, not greater than 1.0pF, otherwise the data will be lost during transmission and cannot be used The circuit works normally. At the same time, the ESD capability is extremely high, not lower than 12kV.

Another TVS device adopts a silicon controlled rectifier (Silicon Controlled Rectifiers, SCR) structure. Although the SCR structure has the advantages of high current discharge efficiency, strong antistatic ability, low static leakage, and small parasitic capacitance, its trigger voltage is high. , The opening speed is slow, and the maintenance voltage (VH) is only 1~2V, which is lower than the working voltage of the protected device, which may easily cause latch-up problems, making it unsuitable for application in power protection circuits. The working voltage of the power supply protection circuit is generally about 5V, so SCR devices with large hysteresis cannot be used. Therefore, it is necessary to develop a new type of ultra-low capacitance TVS device, which must not only meet the requirements of small parasitic capacitance of high-speed communication ports, but also meet the requirements of low clamping voltage of power protection circuit, high peak current I _PP , high ESD capability and holding voltage (VH) greater than the operating voltage requirement.

Contents of the invention

In view of the above problems, the object of the present invention is to provide a bidirectional TVS device and its preparation method, which have the advantages of low clamping voltage, high _IPP , high ESD capability and sustaining voltage greater than working voltage.

The first aspect of the present invention provides a bidirectional TVS device, including:

a substrate of the first doping type;

an epitaxial layer of a second doping type on the substrate, wherein the second doping type is opposite to the first doping type;

an isolation structure extending from the surface of the epitaxial layer into the substrate, defining mutually isolated first regions, second regions, third regions, fourth regions, and fifth regions in the epitaxial layer; wherein , the first diode, the second diode, the third diode and the fourth diode are respectively formed in the first region, the second region, the third region and the fourth region, and the fifth region is formed triode; and

A metal interconnection structure, connecting the cathodes of the first diode and the third diode to the first potential of the triode, and connecting the anodes of the second diode and the fourth diode to the first potential of the triode two potentials.

Preferably, the anode of the first diode and the cathode of the second diode are connected to the first channel; the cathode of the first diode, the cathode of the third diode, and the collector of the triode connected to the power supply terminal; the anode of the second diode, the emitter of the triode and the anode of the fourth diode are grounded; the anode of the third diode and the fourth diode The negative terminal of the connected to the second channel.

Preferably, it also includes:

a well region located in the epitaxial layer of the fifth region, the well region having a first doping type;

a first doped region of a first doping type in the epitaxial layer of the first region, the second region, the third region and the fourth region; and

The second doped region of the second doping type is located in the epitaxial layer of the first region, the second region, the third region, the fourth region and the well region of the fifth region;

In the first area, the second area, the third area, and the fourth area, the first doped region, the second doped area, and the epitaxial layer constitute the first diode, the second diode, and the third diode, respectively. tube and the fourth diode; in the fifth region, the second doped region and the well region form a triode.

Preferably, the first doped region of the first doping type is also located in the well region of the fifth region, and the first doped region in the fifth region is short-circuited with the second doped region forming the emitter of the triode, so that In the fifth region, a triode with a base and an emitter short-circuited is formed.

Preferably, in the first region, the second region, the third region, and the fourth region, a well region is further included, the well region is located in the epitaxial layer, and the first doped region is located in the well region , the second doped region is located outside the well region.

Preferably, an isolation layer is included, the isolation layer is located between the substrate and the epitaxial layer, and the isolation structure penetrates the epitaxial layer and the isolation layer from the surface of the epitaxial layer and extends to the in the substrate.

Preferably, the isolation layer is an intrinsic semiconductor layer or an insulating layer.

Preferably, the first doped region includes:

an implanted region of the first doping type; and/or

a deep trench filled with semiconductor material of the first doping type;

The second doped region includes:

an implanted region of the second doping type; and/or

A deep trench is filled with semiconductor material of a second doping type.

Preferably, the width of the first doped region and the second doped region is 1.5um-20um, and the junction depth is 0.3um-2um.

Preferably, the tops of the first doped region and the second doped region have a width of 1um-3um and a depth of 2um-6um.

Preferably, in the first region, the second region, the third region and the fourth region, the first doped regions and the second doped regions are alternately arranged.

Preferably, in the fifth region, the top view shape of the first doped region and the second doped region is one of strip shape, rectangle shape, zigzag shape, ring shape or a combination thereof.

Preferably, the first area, the second area, the third area and the fourth area are arranged in a matrix, and the fifth area is located in the central area of the matrix.

Preferably, the third diode has the same area and structure as the second diode, and the fourth diode has the same area and structure as the first diode.

The second aspect of the present invention provides a method for preparing a bidirectional TVS device, comprising:

forming an epitaxial layer of a second doping type on a substrate of the first doping type, wherein the second doping type is opposite to the first doping type;

forming an isolation structure, the isolation structure extending from the surface of the epitaxial layer into the substrate, defining mutually isolated first regions, second regions, third regions, fourth regions, and The fifth area; wherein, the first diode, the second diode, the third diode and the fourth diode are respectively formed in the first area, the second area, the third area, and the fourth area, and in forming a triode in the fifth region; and

forming a metal interconnection structure, the metal interconnection structure connects the cathodes of the first diode and the third diode to the first potential of the triode, and connects the anodes of the second diode and the fourth diode connected to the second potential of the triode.

Preferably, the anode of the first diode and the cathode of the second diode are connected to the first channel; the cathode of the first diode, the cathode of the third diode, and the collector of the triode connected to the power supply terminal; the anode of the second diode, the emitter of the triode and the anode of the fourth diode are grounded; the anode of the third diode and the fourth diode The negative terminal of the connected to the second channel.

Preferably, before or after forming the isolation structure, further comprising:

forming a well region in the epitaxial layer of the fifth region, the well region having a first doping type;

forming a first doped region of a first doping type in the epitaxial layer of the first region, the second region, the third region, and the fourth region; and

forming a second doped region of the second doping type in the epitaxial layer of the first region, the second region, the third region, the fourth region and the well region of the fifth region;

In the first area, the second area, the third area, and the fourth area, the first doped region, the second doped area, and the epitaxial layer constitute the first diode, the second diode, and the third diode, respectively. tube and the fourth diode; in the fifth region, the second doped region and the well region form a triode.

Preferably, before or after forming the isolation structure, it further includes: forming a first doped region of the first doping type in the fifth region, the first doped region in the fifth region is connected with the triode emitter The second doped region is short-circuited to form a triode in which the base and the emitter are short-circuited in the fifth region.

Preferably, before or after forming the isolation structure, it further includes: forming a well region in the epitaxial layer in the first region, the second region, the third region, and the fourth region, and the first doped region is located in the well region, and the second doped region is located outside the well region.

Preferably, before forming the epitaxial layer, it also includes: forming an isolation layer on the substrate, and the isolation structure penetrates the epitaxial layer and the isolation layer from the surface of the epitaxial layer and extends to the substrate. Bottom.

Preferably, the isolation layer is an intrinsic semiconductor layer or an insulating layer.

Preferably, the first doped region includes:

an implanted region of the first doping type; and/or

a deep trench filled with semiconductor material of the first doping type;

The second doped region includes:

an implanted region of the second doping type; and/or

A deep trench is filled with semiconductor material of a second doping type.

Preferably, the implantation region of the first doping type or the implantation region of the second doping type is formed by ion implantation.

Preferably, the method of forming a deep trench filled with a semiconductor material of the first doping type or a semiconductor material of the second doping type comprises:

forming deep grooves extending from the surface of the epitaxial layer to the interior of the epitaxial layer; and

The deep groove is filled with a semiconductor material of the first doping type or a semiconductor material of the second doping type to form a first doping region or a second doping region.

Preferably, the semiconductor material of the first doping type is polysilicon doped with boron; the doping concentration is 1E17-1E20 cm-3; the semiconductor material of the second doping type is polysilicon doped with phosphorus, and the doping concentration is 1E17～1E20 cm-3.

Preferably, the width of the first doped region and the second doped region is 1.5um-20um, and the junction depth is 0.3um-2um.

Preferably, the tops of the first doped region and the second doped region have a width of 1um-3um and a depth of 2um-6um.

Preferably, in the first region, the second region, the third region and the fourth region, the first doped regions and the second doped regions are alternately arranged.

Preferably, in the fifth region, the top view shape of the first doped region and the second doped region is one of strip shape, rectangle shape, zigzag shape, ring shape or a combination thereof.

Preferably, the first area, the second area, the third area and the fourth area are arranged in a matrix, and the fifth area is located in the central area of the matrix.

Preferably, the third diode has the same area and structure as the second diode, and the fourth diode has the same area and structure as the first diode.

The bidirectional TVS device and the preparation method thereof provided by the present invention adopt a diode and a voltage stabilizing transistor to be integrated into a bidirectional TVS device, and integrate the advantages of the small capacitance of the diode and the Snapback effect of the short circuit between the base and the emitter of the triode, which can Taking into account the advantages of diodes and triodes, it has the characteristics of small capacitance, low residual voltage and appropriate voltage.

In a preferred embodiment, the triode whose base and emitter are short-circuited constitutes the regulator part of the bidirectional TVS device, which has a Snapback characteristic compared with the bidirectional TVS device in the prior art.

Optionally, the triode constitutes the voltage regulator part of the bidirectional TVS device, the base of the triode is open, holes cannot flow out through the base, and the PN junction formed by the base and emitter of the triode has a small opening When the current, generally uA level.

Further, by adjusting the spacing between the second doped regions in the fifth region (the distance between the collector and the emitter of the triode, that is, the width of the base region of the triode) and the implantation dose of the second doped region and the well region That is to say, the breakdown voltage and negative resistance can be adjusted, so that the sustaining voltage of the bidirectional TVS device is greater than the operating voltage, so that it will not cause latch-up problems, and it can also lower the clamping voltage under high current conditions. Power consumption will be less.

Further, since the first diode is exactly the same as the third diode, the second diode is exactly the same as the diode and share the triode, the forward and reverse breakdown voltages of the bidirectional TVS device are equal, and the forward and reverse breakdown voltages are equal. Good voltage consistency.

In a preferred embodiment, the isolation layer is an intrinsic semiconductor layer, and an intrinsic semiconductor layer is provided between the substrate and the epitaxial layer, so that the substrate, the isolation layer, and the The epitaxial layer forms a vertical PIN junction. Compared with the PN junction, the PIN junction can significantly reduce the carrier concentration, thereby reducing the capacitance.

In a preferred embodiment, the isolation layer is an insulating layer, so that the TVS device forms a silicon-on-insulator (SOI, Silicon on Insulator) structure, and devices in different regions are separated by an isolation layer with good insulating properties. The separation can eliminate the opening of bulk silicon parasitic devices, reduce the parasitic capacitance and leakage current between the substrate and the epitaxial layer, and have the advantages of high integration and good radiation resistance.

In a preferred embodiment, the first doped region and/or the second doped region in the triode and/or diode are formed by using a deep trench filling process, and an electric field is introduced from the surface of the device to the inside of the epitaxial layer, improving the device stability and surge immunity.

Furthermore, the first doped region and/or the second doped region of the deep groove structure enables the triode and/or diode to have a larger effective area, which can significantly improve the anti-surge capability and reduce the clamping voltage.

Furthermore, the lateral diffusion of the deep groove structure in the triode and/or diode is small, and under the same area, more minimum repeating units can be made, which improves the current density per unit area and further improves the anti-surge and anti-ESD capabilities of the device. promote.

Furthermore, the ion implantation process is limited by the capability of the implanter, and the ion implantation dose can only be up to 1.0E16 cm ^-2 , and the deep trench filling process is used to form the first doped region and/or The second doping region can make the doping concentration of the first doping region and the second doping region higher, which can improve the emission efficiency of the triode and reduce the contact resistance, thereby improving the _IPP capability and reducing the clamping voltage.

In a preferred embodiment, in the fifth region, the first doped region and the second doped region are arranged in a "back shape", and the second doped region arranged in a "back shape" forms a triode, and current can pass through the inner The collector electrode of the ring flows into the emitter electrode of the outer ring, which increases the perimeter area ratio and improves the emission efficiency and anti-surge capability of the triode current.

In a preferred embodiment, in the fifth region, the first doped region and the second doped region are arranged in a "ring shape", and the second doped region arranged in a "ring shape" forms a triode, and current can pass through The collector electrode of the inner ring flows into the emitter electrode of the outer ring, which increases the perimeter area ratio, improves the emission efficiency and surge resistance of the triode current, and makes the electric field distribution more smooth.

Description of drawings

Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above-mentioned and other objects, features and advantages of the present invention will be more clear, in the accompanying drawings:

Figure 1 shows the electrical I-V curves of the forward and reverse directions of the bidirectional TVS device;

Fig. 2 shows the schematic diagram of the circuit connection structure of the first bidirectional TVS device in the prior art;

Fig. 3 shows the schematic diagram of the circuit connection structure of the second bidirectional TVS device in the prior art;

FIG. 4 shows a schematic diagram of a circuit connection structure of a third bidirectional TVS device in the prior art;

Fig. 5 shows the sectional view of the bidirectional TVS device of the first embodiment of the present invention;

6 shows a top view of the arrangement of the well region, the first doped region and the second doped region in the bidirectional TVS device according to the first embodiment of the present invention;

Fig. 7 shows the schematic diagram of the circuit connection structure of the bidirectional TVS device of the first embodiment of the present invention;

8a to 8c show schematic diagrams of current flow when the first channel I/O1 is applied with a high potential and the second channel I/O2 is applied with a low potential in the bidirectional TVS device according to the first embodiment of the present invention;

9a to 9i show cross-sectional views of various stages in the preparation process of the bidirectional TVS device according to the first embodiment of the present invention;

Fig. 10 shows the sectional view of the bidirectional TVS device of the second embodiment of the present invention;

11 shows a cross-sectional view of a bidirectional TVS device according to a third embodiment of the present invention;

12 shows a cross-sectional view of a bidirectional TVS device according to a fourth embodiment of the present invention;

13a to 13k show cross-sectional views of various stages in the preparation process of the bidirectional TVS device according to the fourth embodiment of the present invention;

14 shows a cross-sectional view of a bidirectional TVS device according to a fifth embodiment of the present invention;

15a to 15h show cross-sectional views of various stages in the fabrication process of the bidirectional TVS device according to the fifth embodiment of the present invention;

16 shows a cross-sectional view of a bidirectional TVS device according to a sixth embodiment of the present invention;

Fig. 17 shows the top view of the bidirectional TVS device of the seventh embodiment of the present invention;

Fig. 18 shows the top view of the bidirectional TVS device of the eighth embodiment of the present invention;

FIG. 19 shows a top view of a bidirectional TVS device according to a ninth embodiment of the present invention;

20a to 20c are schematic diagrams of the current flow when the first channel I/O1 is applied with a high potential and the second channel I/O2 is applied with a low potential in the bidirectional TVS device according to the tenth embodiment of the present invention.

detailed description

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the various figures, identical elements are indicated with similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown.

The invention can be embodied in various forms, some examples of which are described below.

Compared with the unidirectional ultra-low capacitance TVS device, the forward and reverse directions of the bidirectional TVS device are basically symmetrical, so that in practical applications, the two directions of the circuit can be protected at the same time, so the application range is wider. The structure of the bidirectional TVS device of the prior art does not usually possess the Snapback effect (negative resistance effect), and Fig. 1 shows the electric IV curve of the positive and negative two directions of the bidirectional TVS device; in Fig. 1, the curve A shows The IV curve of the device without the Snapback feature, Curve B shows the IV curve of the device with the Snapback feature, where, under the same I _PP , the clamping voltage V _CB of the device with the Snapback feature is significantly lower than that without the Snapback feature characteristic of the device clamping voltage V _CA .

There are roughly three types of bidirectional TVS devices in the prior art, and Figure 2 shows a schematic diagram of the circuit connection structure of the first bidirectional TVS device in the prior art; wherein, as shown in Figure 2a, the bidirectional TVS device connects two unidirectional Ultra-low-capacitance TVS devices are connected in series, and each unidirectional ultra-low-capacitance TVS device connects a low-capacitance first diode D1 in series with a traditional voltage-stabilizing TVS diode Z1, and then another low-capacitance second diode D2 is formed in parallel. Alternatively, as shown in Figure 2b, the bidirectional TVS device connects unidirectional low capacitance diodes with low integration in series.

Although the capacitance of the first bidirectional TVS device is much lower than that of a single TVS device at the same voltage, its forward and reverse characteristics are still equivalent to an ordinary diode. The first bidirectional TVS device has the following disadvantages: two sets of chips are connected in series, and the cost is high; it is difficult to package two sets of chips in a smaller package; it does not have the Snapback effect (negative resistance effect), and the clamping voltage is relatively high.

Fig. 3 shows the schematic diagram of the circuit connection structure of the second bidirectional TVS device in the prior art; The TVS diode Z1 is connected in antiparallel with another set of low-capacitance second diodes D2 and voltage-stabilizing TVS diode Z2 in series.

The second type of bidirectional TVS device has a higher integration degree and lower capacitance, which meets general low-capacitance application scenarios. However, the forward and reverse sides of the bidirectional TVS device are respectively composed of a voltage-stabilizing TVS diode Z1 and a voltage-stabilizing TVS diode Z2. This will make it difficult to achieve the same forward and reverse withstand voltage, which does not meet the application scenarios with high symmetry requirements. At the same time, the structure does not have the Snapback effect, and the clamping voltage is relatively high.

Fig. 4 shows the schematic diagram of the circuit connection structure of the third kind of bidirectional TVS device in the prior art; , a low-capacitance third diode D3, a low-capacity fourth diode D4, and a voltage regulator tube Z1, wherein the first diode D1 and the second diode D2 are connected in parallel, and the third and second diodes The diode D3 and the fourth diode D4 are connected in parallel, the first diode D1 and the second diode D2 connected in parallel and the third diode D3 and the fourth diode D4 connected in parallel are respectively connected with the voltage regulator tube Z1 connection.

The forward and reverse channels of the third bidirectional TVS device share the same regulator tube Z1, so the problem of bad voltage symmetry will not occur. However, the third type of bidirectional TVS device does not have the Snapback effect, and the clamping voltage is relatively high. At the same time, the use of a buried layer with a high doping concentration will lead to relatively large parasitic capacitance.

Fig. 5 shows the sectional view of the bidirectional TVS device of the first embodiment of the present invention; As shown in Fig. A doping region 107, a plurality of second doping regions 108, a dielectric layer 109 and a metal interconnection structure.

The isolation layer 102 is located on the substrate 101, the epitaxial layer 103 is located on the isolation layer 102, wherein the substrate 101 has a first doping type, and the isolation layer 102 is an intrinsic semiconductor layer , the epitaxial layer 103 has a second doping type opposite to the first doping type. In this embodiment, the substrate 101 is, for example, a P-substrate, and the epitaxial layer 103 is, for example, an N-epitaxial layer.

The isolation structure 105 extends from the surface of the epitaxial layer 103 toward the direction of the substrate 101 , the isolation structure 105 penetrates the epitaxial layer 103 and the isolation layer 102 , and extends into the substrate 101 . The isolation structure 105 isolates the epitaxial layer 103 to form multiple regions. In this embodiment, the multiple regions are respectively one triode region and four diode regions. Specifically, the epitaxial layer 103 is isolated by the isolation structure 105 to form a first region 1031, a second region 1032, a third region 1033, a fourth region 1034 and a fifth region 1035, wherein the first region 1031, The second region 1032 , the third region 1033 and the fourth region 1034 are diode regions, and the fifth region 1035 is a triode region.

In this embodiment, the first area 1031 , the second area 1032 , the third area 1033 and the fourth area 1034 are arranged in a matrix, and the fifth area 1035 is located in the central area of the matrix, but it is not limited thereto.

In this embodiment, the isolation structure 105 includes an isolation trench, a gate oxide layer (not shown in the figure) covering the sidewall and bottom of the isolation trench, and polysilicon filled inside the isolation trench, that is, the The gate oxide layer is located between the polysilicon and the isolation trench.

The plurality of first doped regions 107 and the plurality of second doped regions 108 respectively extend from the surface of the epitaxial layer 103 to the interior of the epitaxial layer 103 . Wherein, the first doped region 107 has a first doping type, and the second doped region 108 has a second doping type. In this embodiment, the first doped region 107 is, for example, a P+ doped region, and the second doped region 108 is, for example, an N+ doped region.

Optionally, the epitaxial layer 103 further includes a well region 106, the well region 106 extends from the surface of the epitaxial layer 103 to the inside of the epitaxial layer 103, in the first region 1031, the second region 1032, and the third region 1033 , In the fourth region 1034, the first doped region 107 is located in the well region 106, and in the fifth region 1035, the first doped region 107 and the second doped region 108 are both located in the well region 106 In the well region 106. Wherein, the well region 106 has the first doping type, and the well region 106 is, for example, a P-type well region.

Further, the length of the well region 106 is greater than the lengths of the first doped region 107 and the second doped region 108, and the width of the well region 106 is greater than that of the first doped region 107 and the The width of the second doped region 108 and the depth of the well region 106 are greater than the depths of the first doped region 107 and the second doped region 108 .

In this embodiment, the well region 106 in the diode region (the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034) can make the electric field distribution more uniform and prevent the electric field from breaking down on the device surface. It can significantly improve the anti-surge and anti-static capabilities of the forward diode, making the device more stable and better in performance.

Fig. 6 shows a top view of the arrangement of the well region, the first doped region and the second doped region in the bidirectional TVS device according to the first embodiment of the present invention; referring to Fig. 5 and Fig. 6 , in the first region 1031, In the second region 1032 , the third region 1033 and the fourth region 1034 , the first doped region 107 , the second doped region 108 and the well region 106 are arranged in parallel strips, wherein the The first doped region 107 is located in the well region 106, the second doped region 108 is located in the epitaxial layer 103 outside the well region 106, and the first doped region 107 and the second doped region The impurity regions 108 are distributed alternately. In the fifth region 1035, the well region 106 is in a rectangular shape, a plurality of first doped regions 107 and a plurality of second doped regions 108 are arranged in parallel strips, and a plurality of the first doped regions 107 and A plurality of the second doped regions 108 are located inside the well region 106 . In a specific embodiment, the number of the first doped regions 107 is 3-50; the number of the second doped regions 108 is 3-50.

Further, in the first region 1031, the first doped region 107 in one well region 106, the adjacent second doped region 108 and the epitaxial layer 103 form a first diode D1, wherein, The first doped region 107 in the first region 1031 is the anode of the first diode D1, and the second doped region 108 in the first region 1031 is the anode of the first diode D1. negative electrode. The first region 1031 includes at least one first diode D1, and when the first region 1031 includes a plurality of first diodes D1, the plurality of first diodes D1 are connected in parallel.

In the second region 1032, the first doped region 107 in one well region 106, the adjacent second doped region 108 and the epitaxial layer 103 form a second diode D2, wherein the second region The first doped region 107 in 1032 is the anode of the second diode D2, and the second doped region 108 in the second region 1032 is the cathode of the second diode D2. The second region 1032 includes at least one second diode D2, and when the first region 1031 includes a plurality of second diodes D2, the plurality of second diodes D2 are connected in parallel.

In the third region 1033, the first doped region 107 in one well region 106, the adjacent second doped region 108 and the epitaxial layer 103 form a third diode D3, and in the fourth region 1034, The first doped region 107 in one well region 106 , the adjacent second doped region 108 and the epitaxial layer 103 form a fourth diode D4 . In order to maintain good symmetry, the area, structure and number of the third diode D3 are exactly the same as those of the second diode D2; the area, structure and number of the fourth diode D4 are exactly the same as those of the first diode D1 .

In a specific embodiment, in the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034, the width of the first doped region 107 and the second doped region 108 is 1.5um～10um, the length is 30um～200um, and the junction depth is 0.3um～2um. The width, length and depth of the first doped region 107 in the first region 1031 and the third region 1033 are all equal, and the width, length and depth of the second doped region 108 are all equal; the second region 1032 and the fourth region 1034 The width, length and depth of the first doped region 107 are equal, and the width, length and depth of the second doped region 108 are equal, so that the current capability in the forward and reverse directions is the same.

Further, in the fifth region 1035 , the well region 106 and the second doped region 108 in the well region 106 form an NPN transistor. Specifically, two adjacent second doped regions 108 constitute the collector and emitter of the NPN transistor respectively, and the well region 106 between the two second doped regions 108 constitutes the base of the NPN transistor. The first doped region 107 is arranged in the middle and the edge of the well region 106, and the first doped region 107 is connected to the second doped region 108 forming the emitter of the NPN transistor through a metal interconnection structure. Together, so that the base and emitter of the NPN transistor are shorted. Further, the magnitude of the trigger current can be controlled by setting the number and area of the first doped region 107 .

In a specific embodiment, in the fifth region 1035, the width of the first doped region 107 and the second doped region 108 is 1.5um-10um, the length is 100um-300um, and the junction depth is 0.3um-2um; the distance between adjacent first doped regions 107 and between adjacent first doped regions 107 and second doped regions 108 is 0.5um-5um.

Further, the dielectric layer 109 is located on the surface of the epitaxial layer 103 away from the substrate 101, and a plurality of contact holes 1091 are opened in the dielectric layer 109, and the contact holes 1091 penetrate the dielectric layer 109, exposing a plurality of first doped regions 107 and a plurality of second doped regions 108; the contact hole 1091 is filled with a metal material (not shown in the figure), and the metal material and the exposed plurality of the The first doped region 107 is in contact with the plurality of the second doped regions 108 to form a metal interconnection structure of the plurality of the first doped regions 107 and the plurality of the second doped regions 108 .

7 shows a schematic diagram of the circuit connection structure of the bidirectional TVS device of the first embodiment of the present invention; referring to FIG. 5 and FIG. 7, the anode of the first diode D1 (the first doped region in the first region 1031 107) and the cathode of the second diode D2 (the second doped region 108 in the second region 1032) are connected to the first channel I/O1; the cathode of the first diode D1 (the second doped region 108 in the first region 1031), the cathode of the third diode D3 (the second doped region 108 in the third region 1033), and the collector of the NPN transistor ( The second doped region 108) forming the collector of the NPN transistor in the fifth region 1035 is connected together and connected to the power supply terminal VCC. The anode of the second diode D2 (the first doped region 107 in the second region 1032), the anode of the fourth diode D4 (the first doped region 107 in the fourth region 1034) region 107), the base of the NPN transistor (the first doped region 107 short-circuited with the emitter of the NPN transistor in the fifth region 1035) and the emitter (the emitter of the NPN transistor is formed in the fifth region 1035 The second doped regions 108) are connected together and grounded to GND. The anode of the third diode D3 (the first doped region 107 in the third region 1033) and the cathode of the fourth diode D4 (the second doped region 108 in the fourth region 1034 ) is connected to the second channel I/O2. Wherein, the collector of the NPN triode serves as the first potential of the triode, and the emitter of the NPN triode serves as the second potential of the triode.

In this embodiment, the lateral NPN transistor whose base and emitter are short-circuited constitutes the regulator part of the bidirectional TVS device. Compared with the bidirectional TVS device in the prior art, the bidirectional TVS device of this embodiment has a Snapback characteristic , wherein, by adjusting the spacing between the second doped regions 108 in the fifth region 1035 (the distance between the collector and the emitter of the NPN transistor, that is, the base width of the NPN transistor) and the second doped regions 108 and The implant dose of the well region 106 can adjust the size of the breakdown voltage and negative resistance (that is, the retrace amplitude, the difference between BVCB and BVCE), and finally make the sustain voltage (VH) of the bidirectional TVS device greater than the operating voltage, so that both It will not cause latch-up problems, and it can also make it have a lower clamping voltage under high current conditions, and the power consumption will be smaller.

Further, in this embodiment, since the first diode D1 is identical to the third diode D3, the second diode D2 is identical to the diode D4, and shares an NPN transistor, the forward and reverse breakdown voltages Equal, good consistency of forward and reverse breakdown voltage.

The consistency of the forward and reverse breakdown voltages of the bidirectional TVS device of this embodiment will be described below in conjunction with the working process of the present embodiment. Specifically, FIG. 8 shows that in the bidirectional TVS device of the first embodiment of the present invention, the first channel I A schematic diagram of the current flow when /O1 is applied to a high potential and the second channel I/O2 is applied to a low potential; wherein, Figure 8a is a cross-sectional view of the bidirectional TVS device of the first embodiment of the present invention, and Figure 8b is a cross-sectional view of the first embodiment of the present invention In the bidirectional TVS device, the top view of the arrangement of the well region, the first doped region and the second doped region, FIG. 8c is a schematic diagram of the circuit connection structure of the bidirectional TVS device according to the first embodiment of the present invention.

Specifically, when the first channel I/O1 has a high potential and the second channel I/O2 has a low potential, the current flow is as shown in FIG. 8a. Current flows from the anode of the first diode D1 (the first doped region 107 in the first region 1031 ) into the cathode of the first diode D1 (the second doped region 108 in the first region 1031 ), Further flow into the collector of the NPN transistor (the second doped region 108 forming the collector in the fifth region 1035), at this time the base and emitter of the NPN transistor are short-circuited, and the doping concentration of the collector region and the base region is relatively high , the depletion region between the collector region and the base region begins to widen and an avalanche breakdown occurs, and impact ionization occurs in the avalanche breakdown to generate electron-hole pairs, and the electrons are sucked into the collector region (the fifth region 1035 constitutes the second part of the collector electrode doped region 108), holes are injected into the base region (the well region 106 in the fifth region 1035), and the current flows from the base and the emitter (the first doped region 107 and the second doped region in the fifth region 1035 108) flow out; when the inflow current increases, when the voltage drop on the base reaches the turn-on voltage of the PN junction formed by the base region (well region 106) and the emitter region (second doped region 108), the NPN transistor will be turned on When it enters the amplification region, the breakdown voltage drops rapidly to the conduction voltage of the NPN transistor, a negative resistance retrace phenomenon occurs, and the current flows out from the second doped region 108 constituting the emitter, and flows into the second channel through the fourth diode D4 I/O2. In this way, under a certain current condition, the clamping voltage can be greatly reduced, as shown by curve B in Fig. 1 .

In this embodiment, the lateral breakdown voltage of the second diode D2 is relatively high (usually 50V-100V), and the breakdown voltage of the vertical PN junction formed by the substrate 101 and the epitaxial layer 103 is greater than 100V. At the same time, in order to make the bidirectional TVS The voltage of the device is suitable, and the breakdown voltage of the collector-emitter (CE) is lower by adjusting the concentration of the emitter region, the concentration and the width of the base region of the NPN triode, generally only a few volts, relative to the second diode D2, so The breakdown voltage of the NPN transistor mentioned above is much lower. When the first channel I/O1 has a high potential and the second channel I/O2 has a low potential, a positive voltage is applied to the anode of the first diode D1, and the first diode D1 is turned on. The NPN triode has The lower breakdown voltage is the first to break down, and the current flows from the first diode D1 into the NPN transistor; then the current flows from the emitter of the NPN transistor into the fourth diode D4, and the fourth diode D4 is forward-conducting Current flows out of the second channel I/O2. Therefore, the reverse breakdown voltage of the first channel I/O1 to the second channel I/O2 can be expressed as:

V _BR1 =V _f1 +V _NPN +V _f4

Wherein, V _f1 is the forward voltage drop of the first diode D1, V _NPN is the collector-emitter (CE) breakdown voltage of the NPN transistor, V _f4 is the forward voltage drop of the fourth diode D4, When the current flowing through the first diode D1 and the fourth diode D4 is 10mA, V _f1 and V _f4 are about 0.9V, and V _NPN can be 4V~7V when used as ESD protection, so the bidirectional TVS device Suitable for protecting 3.3V and 5V circuits.

In the same way, when the second channel I/O2 has a high potential and the first channel I/O1 has a low potential, the current flows into the NPN transistor from the forward direction of the third diode D3, and then flows from the second diode D2 to the NPN triode. One channel I/O1 flows out, and the reverse breakdown voltage of the second channel I/O2 to the first channel I/O1 can be expressed as:

V _BR2 =V _f3 +V _NPN +V _f2

Wherein, V _f3 is the forward voltage drop of the third diode D3, V _NPN is the collector-emitter (CE) breakdown voltage of the NPN transistor, and V _f2 is the forward voltage drop of the second diode D2.

Since the first diode D1 is exactly the same as the third diode D3, and the second diode D2 is exactly the same as the diode and D4, sharing the NPN triode, so V _BR1 = V _BR2 , good consistency of forward and reverse breakdown voltages .

Furthermore, in this embodiment, the diode and the voltage-stabilizing NPN transistor are integrated into a bidirectional TVS device, which can significantly reduce the capacitance of the device. Among them, although the single triode structure has better current discharge capability, but because the larger the area of the triode, the higher the I _PP , the better the ESD resistance, and the single triode structure has better current discharge capability. The parasitic capacitance is also very large, generally in the range of tens of pF to tens of pF. In this embodiment, four low-capacitance diodes and one NPN transistor are integrated to form a bidirectional TVS device, which can take into account the advantages of diodes and NPN transistors, and has the characteristics of small capacitance, low residual voltage, and appropriate voltage.

Specifically, the first doped regions 107 and the second doped regions 108 are alternately arranged in the epitaxial layer 103, and the alternately arranged first doped regions 107 and the second doped regions 108 and the epitaxial layer 103 form the first two Diode D1 to fourth diode D4. Due to the low doping concentration of the epitaxial layer 103 , the areas of the first diode D1 to the fourth diode D4 are small, and the capacitance of the diodes is generally 0.1 pF˜1 pF. Integrate low-capacity diodes and general-capacity triodes into one circuit. The triode is equivalent to a wire. The circuit can be equivalent to the first diode D1 and the second diode D2 in parallel, and the third diode D3 and the fourth diode. The diode D4 is connected in parallel, and then the two are connected in series, assuming that the capacitance C _D1 of the first diode D1 is equal to the capacitance C _D3 of the third diode D3, and C _D1 =C _D3 =0.4pF, the second diode The capacitance C _D2 of D2 is equal to the capacitance C _D4 of the fourth diode D4, and C _D2 = C _D4 =0.3pF, then the capacitance C _T of the first channel I/O1 to the second channel I/O2 can be expressed as:

It can be seen from the above formula that by integrating the first diode D1 to the fourth diode D4 and the NPN transistor into one circuit, the capacitance of the bidirectional TVS device is greatly reduced, and further, by adjusting the first diode The area of the transistor D1 to the fourth diode D4 and the NPN transistor is used to adjust the capacitance and clamping voltage of the bidirectional TVS device.

Figures 9a to 9i show cross-sectional views of various stages in the preparation process of the bidirectional TVS device according to the first embodiment of the present invention, and the preparation method of the bidirectional TVS device according to the first embodiment of the present invention will be described below with reference to Figures 9a to 9i .

As shown in Figure 9a, a substrate 101 is provided. Wherein, the substrate 101 is a semiconductor layer of the first doping type. In this embodiment, the substrate 101 is, for example, a P-type silicon substrate, and the resistivity of the substrate 101 is 50Ω·cm≤ρ ≤200Ω·cm. The parasitic capacitance is reduced by setting the resistivity of the substrate 101 .

As shown in FIG. 9b, an isolation layer 102 and an epitaxial layer 103 are sequentially formed on the substrate 101. Wherein, the isolation layer 102 is located on the substrate 101 , and the epitaxial layer 103 is located on the isolation layer 102 .

Wherein, the isolation layer 102 is an intrinsic semiconductor layer, and the epitaxial layer 103 is a semiconductor layer of the second doping type. In this embodiment, the epitaxial layer 103 is, for example, an N-type epitaxial layer. In this embodiment, an isolation layer 102 is provided between the substrate 101 and the epitaxial layer 103 , so that the substrate 101 , the isolation layer 102 and the epitaxial layer 103 form a vertical PIN junction. Compared with the PN junction without the isolation layer 102 , this embodiment can significantly reduce the carrier concentration, thereby reducing the parasitic capacitance. And in the subsequent triode region, the substrate 101 is a P-type substrate, and there is an isolation layer 102 between the substrate 101 and the triode region, and the vertical capacitance is very low.

As shown in FIG. 9 c , a first oxide layer 1041 having an opening 1041 a is formed on the epitaxial layer 103 .

In this step, the first oxide layer 1041 is formed on the epitaxial layer 103 by, for example, a deposition process. Further, an opening 1041a is formed in the first oxide layer 1041 by photolithography and etching. Wherein, the first oxide layer 1041 is, for example, a silicon oxide (SiO ₂ ) layer.

As shown in FIG. 9d, an isolation structure 105 is formed.

In this step, the epitaxial layer 103 , the isolation layer 102 and the substrate 101 are etched through the opening 1041 a to form a plurality of isolation trenches. Wherein, each isolation trench penetrates the epitaxial layer 103 and the isolation layer 102 , and extends to the inside of the substrate 101 .

Further, a gate oxide layer is formed on the sidewall and bottom of the isolation trench by using gate oxide growth, and then the isolation trench is filled by a polysilicon filling process to form an isolation structure 105 . The isolation structure 105 divides the semiconductor structure into different regions. In this embodiment, the semiconductor structure is at least isolated to form a first region 1031 , a second region 1032 , a third region 1033 , a fourth region 1034 and a fifth region 1035 . Then, the first oxide layer 1041 is removed.

As shown in FIG. 9e, the second oxide layer 1042 is grown thermally.

In this embodiment, the second oxide layer 1042 is, for example, a silicon oxide (SiO ₂ ) layer, the thickness of the second oxide layer 1042 is smaller than the thickness of the first oxide layer 1041, and the second oxide layer 1042 serves as Masking layer for subsequent ion implantation.

As shown in FIG. 9f , the first ion implantation is performed to form a plurality of well regions 106 .

In this step, using the second oxide layer 1042 as a mask layer, a photolithography process is used to selectively implant impurities of the first doping type, and push junctions are performed to form a plurality of well regions 106 . The well region 106 extends from the surface of the epitaxial layer 103 toward the interior of the epitaxial layer 103 . A plurality of the well regions 106 are respectively located in the epitaxial layer 103 in the first region 1031, the second region 1032, the third region 1033, the fourth region 1034 and the fifth region 1035. Wherein, in the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034, the plan view shape of the well region 106 is strip-shaped, and in the fifth region 1035, the The top view shape of the well region 106 is rectangular.

As shown in FIG. 9 g , a second ion implantation is performed to form a first doped region 107 .

In this step, using the second oxide layer 1042 as a mask layer, a photolithography process is used to selectively implant high-concentration impurities of the first doping type, and annealing is performed to form the first doped region 107. 107 is the injection area. The first doped region 107 extends from the surface of the well region 106 to the inside of the well region 106 . In the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034, the top view of the first doped region 107 is strip-shaped, and a plurality of the first doped regions 107 located in the corresponding well region 106 .

As shown in FIG. 9 h , a third ion implantation is performed to form a second doped region 108 .

In this step, using the second oxide layer 1042 as a mask layer, a high-concentration impurity of the second doping type is selectively implanted by a photolithography process, and annealing is performed to form the second doped region 108, and the second doped region 108 is formed. Region 108 is the implanted region. The second doped region 108 extends from the surface of the epitaxial layer 103 toward the interior of the epitaxial layer 103 . A plan view of the plurality of second doped regions 108 is strip-shaped. In the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034, the second doped region 108 is located in the epitaxial layer 103, and is connected with the first doped region 107 Alternate distribution. In the fifth region 1035 , a plurality of second doped regions 108 are arranged in parallel inside the well region 106 .

In the first region 1031, the first doped region 107 in the well region 106, the second doped region 108 outside the well region 106 and the epitaxial layer 103 form a first diode D1; in the second region In 1032, the first doped region 107 in the well region 106, the second doped region 108 outside the well region 106 and the epitaxial layer 103 constitute the second diode D2; in the third region 1033, the well region 106 The first doped region 107 in the well region 106, the second doped region 108 outside the well region 106, and the epitaxial layer 103 constitute the third diode D3; in the fourth region 1034, the first doped region 108 in the well region 106 The region 107, the second doped region 108 outside the well region 106 and the epitaxial layer 103 form a fourth diode D4. The third diode D3 has the same area and structure as the second diode D2; the fourth diode D4 has the same area and structure as the first diode D1.

In the fifth region 1035 , the well region 106 and the second doped region 108 in the well region 106 form an NPN transistor. Specifically, two adjacent second doped regions 108 and the well region between the two second doped regions 108 form the collector, emitter and base of the NPN transistor respectively. The first doped region 107 is arranged inside and at the edge of the well region 106 .

In a specific embodiment, in the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034, the width of the first doped region 107 and the second doped region 108 is 1.5um～10um, length 30um～200um, junction depth 0.3um～2um. In the fifth region 1035, the first doped region 107 and the second doped region 108 have a width of 1.5um-10um, a length of 100um-300um, and a junction depth of 0.3um-2um; The distance between the first doped regions 107 and between the adjacent first doped regions 107 and the second doped regions 108 is 0.5um˜5um.

As shown in FIG. 9 i , a dielectric layer 109 is formed on the surface of the epitaxial layer 103 , and a contact hole 1091 is formed in the dielectric layer 109 .

In this step, for example, the dielectric layer 109 is formed on the surface of the epitaxial layer 103 by using a deposition process. The dielectric layer 109 is, for example, a silicon oxide (SiO ₂ ) layer. Further, a plurality of contact holes 1091 are formed in the dielectric layer 109 by using a photolithography process and an etching process. The contact holes 1091 penetrate through the dielectric layer 109 , exposing the plurality of first doped regions 107 and the plurality of second doped regions 108 .

Further, a metal interconnection structure is formed.

In this step, metal is deposited in the contact hole 1091 and on the surface of the dielectric layer 109, and the metal is photolithographically and etched to form a metal interconnection structure.

The metal interconnect structure is electrically connected to the exposed first doped regions 107 and the second doped regions 108 to form the first doped regions 107 and the second doped regions. The metal interconnection structure of the impurity region 108 is specifically shown in FIG. 5 . Optionally, a double-layer metal interconnection structure can be formed as required.

Specifically, the anode of the first diode D1 (the first doped region 107 in the fifth region 1035) and the cathode of the second diode D2 (the second doped region in the first region 1031 The impurity region 108) is connected to the first channel I/O1; the cathode of the first diode D1 (the second doped region 108 in the first region 1031), the third diode D3 The cathode of the NPN transistor (the second doped region 108 in the third region 1033 ) and the collector of the NPN transistor are connected together and connected to the power supply terminal VCC. The anode of the second diode D2 (the first doped region 107 in the second region 1032), the anode of the fourth diode D4 (the first doped region 107 in the fifth region 1053) Region 107), the base and the emitter of the NPN transistor are connected together and grounded to GND. The anode of the third diode D3 (the first doped region 107 in the third region 1033) and the cathode of the fourth diode D4 (the second doped region 108 in the fourth region 1034 ) is connected to the second channel I/O2.

Further, a passivation layer is deposited on the metal interconnection structure, and the passivation layer is photolithographically and etched to form pressure points; the substrate is thinned to an appropriate thickness to adapt to different packaging forms. The above steps are conventional techniques in the art, and will not be repeated here.

Fig. 10 shows the sectional view of the bidirectional TVS device of the second embodiment of the present invention, as shown in Fig. 10, described bidirectional TVS device comprises substrate 101, isolation layer 102a, epitaxial layer 103, isolation structure 105, a plurality of wells region 106, a plurality of first doped regions 107, a plurality of second doped regions 108, a dielectric layer 109, and a metal interconnection structure.

In this embodiment, the substrate 101, the epitaxial layer 103, the isolation structure 105, the plurality of well regions 106, the plurality of first doped regions 107, the plurality of second doped regions 108, the dielectric layer 109, the metal interconnection structure and The first embodiment is the same and will not be repeated here. Different from the first embodiment, in this embodiment, the isolation layer 102a is an insulating layer, such as a silicon oxide layer, so that the bidirectional TVS device forms a silicon-on-insulator (SOI, Silicon on Insulator) structure, so that The complete isolation between the substrate and the epitaxial layer further makes devices (such as diodes or triodes) in different regions separated by an isolation layer 102a with good insulation performance, which can prevent the first doped region and the second doped region in different regions from There is a first doped region (P+), an epitaxial layer (N-), a substrate (P-), an epitaxial layer (N-), and a first doped region (P+) between the doped region and the substrate to form a parasitic The PNPNP structure (SCR structure) prevents the risk of false triggering in the circuit, reduces the parasitic capacitance and leakage current between the substrate 101 and the epitaxial layer 103, and has the advantages of high integration and good radiation resistance.

The manufacturing method of the bidirectional TVS device of this embodiment is the same as that of the first embodiment, and will not be repeated here.

Fig. 11 shows the sectional view of the bidirectional TVS device of the third embodiment of the present invention, as shown in Fig. 11, described bidirectional TVS device comprises substrate 101, isolation layer 102, epitaxial layer 103, isolation structure 105, a plurality of wells region 106, a plurality of first doped regions 107, a plurality of second doped regions 108, a dielectric layer 109, and a metal interconnection structure.

Different from the first embodiment, in this embodiment, the first doped region 107 is only located in the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034, and the fifth region 1035 has only the second doped region 108 in the well region 106 .

In this embodiment, the base and the emitter of the NPN transistor are not short-circuited, and the NPN transistor is an open-circuit transistor at this time. When the applied voltage makes the collector and base of the NPN triode undergo avalanche breakdown, impact ionization generates electron-hole pairs, and electrons are sucked into the collector (the second doped region 108 in the fifth region 1035), and the holes The hole is injected into the base (well region 106), and when the PN junction formed by the base (well region 106) and the emitter (the second doped region 108 in the fifth region 1035) reaches the forward turn-on voltage, the NPN triode It will be turned on and enter the amplification area, and the breakdown voltage will drop rapidly to the conduction voltage of the NPN transistor, and the Snapback (negative resistance retrace) phenomenon will occur.

In the first embodiment, the base of the NPN transistor is short-circuited to the emitter, and holes can flow out through the base. The current of the PN junction formed by the emitter region of the NPN transistor (that is, the N region) is relatively large, generally at the mA level; in this embodiment, the base of the NPN transistor is open, and holes cannot flow out through the base. The current of the PN junction formed by 106 (the base region of the NPN transistor, ie the P region) and the second doped region 108 (the emitter region of the NPN transistor, ie the N region) is small when it is turned on, generally at the μA level.

The manufacturing method of the bidirectional TVS device of this embodiment is the same as that of the first embodiment, and will not be repeated here.

Fig. 12 shows the sectional view of the bidirectional TVS device of the fourth embodiment of the present invention, as shown in Fig. 12, described bidirectional TVS device comprises substrate 101, isolation layer 102, epitaxial layer 103, isolation structure 105, a plurality of wells Region 106, multiple first doped regions 107, multiple second doped regions 108, multiple first doped regions 107a, multiple second doped regions 108a, dielectric layer 109, metal interconnection structure.

Different from the first embodiment, in this embodiment, a plurality of first doped regions 107a and a plurality of second doped regions 108a are formed in the fifth region 1035; the first doped regions 107a and the The second doped region 108a is a deep trench structure filled with doped semiconductor material.

Specifically, the well region 106 of the fifth region 1035 has a first deep groove and a second deep groove, and the first deep groove is filled with a semiconductor material of a first doping type (such as a P-type semiconductor material), so as to A first doped region 107a is formed; the second deep trench is filled with a semiconductor material of a second doping type (for example, an N-type semiconductor material) to form a second doped region 108a. In this embodiment, the first deep groove is filled with, for example, boron-doped polysilicon; the doping concentration is 1E17˜1E20 cm −3 . For example, phosphorus-doped polysilicon is filled in the second deep groove; the doping concentration is 1E17˜1E20 cm −3 .

Further, the dimensions of the first deep groove and the second deep groove are the same, and the groove bottoms of the first deep groove and the second deep groove have smooth curves, so that the electric field between the first deep groove and the second deep groove The groove bottom of the second deep groove is evenly distributed, which improves the stability of the product.

In a specific embodiment, the width of the top of the first deep groove and the top of the second deep groove is, for example, 1um˜3um, and the depth is, for example, 2um˜6um. The side walls of the first deep groove and the second deep groove are inclined, and the inclination angle is 89.0°±0.5°.

In this embodiment, the area of the NPN transistor is increased by increasing the depths of the first doped region and the second doped region forming the NPN transistor, and the current discharge capability of the NPN transistor is further improved; at the same time, the electric field is introduced from the surface of the device into the epitaxy Inside the layer, the current discharge capability is improved, a lower clamping voltage is obtained, and the stability of the device is better.

13a to 13k show cross-sectional views of various stages in the fabrication process of the bidirectional TVS device according to the fourth embodiment of the present invention.

Wherein, the steps shown in FIG. 13a and FIG. 13b are the same as the steps shown in FIG. 9a and FIG. 9b in the first embodiment, and will not be repeated here in this embodiment.

As shown in FIG. 13 c , a second oxide layer 1042 is formed on the epitaxial layer 103 .

In this step, the second oxide layer 1042 is formed on the epitaxial layer 103 by, for example, a deposition process. Wherein, the second oxide layer 1042 is, for example, a silicon oxide (SiO ₂ ) layer, and the thickness of the second oxide layer 1042 is, for example,

As shown in FIG. 13 d , the first ion implantation is performed to form multiple well regions 106 .

In this step, using the second oxide layer 1042 as a mask layer, a photolithography process is used to selectively implant impurities of the first doping type, and push junctions are performed to form a plurality of well regions 106 . The well region 106 extends from the surface of the epitaxial layer 103 toward the interior of the epitaxial layer 103 .

As shown in FIG. 13 e , a second ion implantation is performed to form a first doped region 107 .

In this step, using the second oxide layer 1042 as a mask layer, a photolithography process is used to selectively implant high-concentration impurities of the first doping type, and annealing is performed to form the first doping region 107 . The first doped region 107 extends from the surface of the well region 106 to the inside of the well region 106 . The first doped region 107 is located in part of the well region 106 .

As shown in FIG. 13f , a third ion implantation is performed to form a second doped region 108 .

In this step, using the second oxide layer 1042 as a mask layer, a photolithography process is used to selectively implant high-concentration impurities of the second doping type, and annealing is performed to form the second doping region 108 . The second doped region 108 extends from the surface of the epitaxial layer 103 toward the interior of the epitaxial layer 103 . A plurality of the second doped regions 108 are located in the epitaxial layer 103 and distributed alternately with the first doped regions 107 . Then the second oxide layer 1042 is removed.

As shown in FIG. 13 g , a first oxide layer 1041 having an opening 1041 a is formed on the epitaxial layer 103 .

In this step, for example, a first oxide layer 1041 is formed on the epitaxial layer 103 by a film growth process, and then an opening 1041a is formed in the first oxide layer 1041 by photolithography and etching. The first oxide layer 1041 is, for example, a silicon oxide (SiO ₂ ) layer with a thickness of, for example, 1.2um.

As shown in FIG. 13h, an isolation structure 105 is formed.

In this step, the epitaxial layer 103 , the isolation layer 102 and the substrate 101 are etched through the opening 1041 a to form a plurality of isolation trenches. Wherein, each isolation trench penetrates the epitaxial layer 103 and the isolation layer 102 , and extends to the inside of the substrate 101 .

Further, gate oxide growth and polysilicon filling processes are used to fill the isolation trenches, and polysilicon etching or CMP processes are used to remove the polysilicon on the surface of the first oxide layer 1041, leaving only the polysilicon inside the isolation trenches to form isolation structure 105 . The isolation structure 105 divides the semiconductor structure into different regions. In this embodiment, the semiconductor structure is at least isolated to form a first region 1031 , a second region 1032 , a third region 1033 , a fourth region 1034 and a fifth region 1035 .

Wherein, the first doped region 107 , the second doped region 108 and part of the well region 106 are located in the first region 1031 , the second region 1032 , the third region 1033 and the fourth region 1034 . The well region 106 in which the first doped region 107 is not formed is located in the fifth region 1035 .

As shown in FIG. 13i, a first doped region 107a is formed.

In this step, photolithography and etching are performed on the epitaxial layer 103 in the fifth region 1035 to form a first deep groove. Specifically, a photoresist is formed on the first oxide layer 1041, and then the photoresist is exposed and developed to form a photoresist mask, and the first photoresist is etched through the photoresist mask. The oxide layer 1041 forms an opening 1041b, and then the photoresist is removed. Further using the first oxide layer 1041 as a hard mask, the epitaxial layer 103 in the fifth region 1035 is etched to form a first deep groove.

Further, a boron-doped polysilicon filling process is used to fill the first deep trench with boron-doped polysilicon to form the first doped region 107a. Specifically, a certain proportion of BCl ₃ and SiH ₄ is fed into the reaction furnace tube, the temperature is 510°C-600°C, and the sheet resistance is 4ohm-20ohm, so that the boron-doped polysilicon can fill the first deep groove, and then The boron-doped polysilicon on the surface of the first oxide layer 1041 is removed by polysilicon etching or CMP process, and only the boron-doped polysilicon in the first deep trench remains, so as to form the first doped region 107a.

In this embodiment, the width of the top of the first deep groove is, for example, 1um-3um, and the depth is, for example, 2um-6um. The side wall of the first deep groove is inclined, and the inclination angle is 89.0°±0.5°. The curve of the groove bottom of the first deep groove is smooth, so that the electric field is evenly distributed on the groove bottom of the first deep groove, and the stability of the product is improved.

As shown in Fig. 13j, a second doped region 108a is formed.

In this step, photolithography and etching are performed on the epitaxial layer 103 in the fifth region 1035 to form a second deep groove. Specifically, a photoresist is formed on the first oxide layer 1041, and then the photoresist is exposed and developed to form a photoresist mask, and the first photoresist is etched through the photoresist mask. An oxide layer 1041 forms an opening 1041c, and then the photoresist is removed. Further using the first oxide layer 1041 as a hard mask, the epitaxial layer 103 in the fifth region 1035 is etched to form a second deep groove.

Further, the phosphorus-doped polysilicon filling process is used to fill the second deep groove with phosphorus-doped polysilicon to form the second doped region 108a. Specifically, a certain proportion of PH ₃ and SiH ₄ is passed into the reaction furnace tube, the temperature is 510°C-600°C, and the sheet resistance is 4ohm-20ohm, so that the phosphorus-doped polysilicon can fill the second deep groove, and then The boron-doped polysilicon on the surface of the first oxide layer 1041 is removed by polysilicon etching or CMP process, and only the boron-doped polysilicon in the second deep trench remains, so as to form the second doped region 108a.

In this embodiment, the width of the top of the second deep groove is, for example, 1um-3um, and the depth is, for example, 2um-6um. The side wall of the second deep groove is inclined, and the inclination angle is 89.0°±0.5°. The curve of the groove bottom of the second deep groove is smooth, so that the electric field is evenly distributed on the groove bottom of the second deep groove, and the stability of the product is improved.

Further, the annealing process is used to push the junction, so that the junction depth and diffusion width meet the target requirements. In the fifth region 1035 , the well region 106 , the first doped region 107 a in the well region 106 and the second doped region 108 a in the well region 106 form an NPN transistor. Specifically, two adjacent second doped regions 108a and the well region 106 between the two second doped regions 108a respectively constitute the collector, emitter and base of the NPN transistor. The first doped region 107a is arranged inside and at the edge of the well region 106.

In this embodiment, the stress release of the isolation structure 105 can be performed together with the annealing of the first doped region 107 a and the second doped region 108 a, saving steps.

This embodiment adopts the deep groove filling process to form the NPN transistor. Compared with the first embodiment, the NPN transistor of this embodiment introduces the electric field from the surface of the device to the bottom of the silicon, which improves the stability and anti-surge capability of the device. .

Furthermore, compared with the NPN transistor of the first embodiment, the NPN transistor of the deep groove structure of this embodiment has a larger effective area, which can significantly improve the anti-surge capability and reduce the clamping voltage.

Further, compared with the NPN transistor of the first embodiment, the deep groove structure of the NPN transistor of this embodiment has a small lateral diffusion, and under the same area, more minimum repeating units can be made, which improves the current density per unit area , so that the anti-surge and anti-ESD capabilities of the device are further improved.

Furthermore, in the first embodiment, the ion implantation process is limited by the capability of the implanter, and the ion implantation dose can only be up to 1.0E16 cm ^-2 , while the doped polysilicon process of this embodiment can make the doping of N+ and P+ The higher impurity concentration can improve the emission efficiency of the triode and reduce the contact resistance, thereby improving the _IPP capability and reducing the clamping voltage.

As shown in FIG. 13k , a dielectric layer 109 is formed on the epitaxial layer 103 , and a contact hole 1091 is formed in the dielectric layer 109 .

This step is the same as the step shown in FIG. 9i in the first embodiment, and will not be repeated here.

Further, a metal interconnection structure is formed to form the structure shown in FIG. 12 .

This step is the same as that of the first embodiment, and will not be repeated here.

Fig. 14 shows the sectional view of the bidirectional TVS device of the fifth embodiment of the present invention, as shown in Fig. 14, described bidirectional TVS device comprises substrate 101, isolation layer 102, epitaxial layer 103, isolation structure 105, a plurality of wells region 106, a plurality of first doped regions 107a, a plurality of second doped regions 108a, a dielectric layer 109 and a metal interconnection structure.

Different from the fourth embodiment, in this embodiment, in the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034, a plurality of first doped regions 107a are used instead of the fourth embodiment In the multiple first doped regions 107 in the example, the multiple second doped regions 108 in the fourth embodiment are replaced by multiple second doped regions 108a.

Specifically, there are first deep grooves in the well regions 106 of the first region 1031, the second region 1032, the third region 1033, and the fourth region 1034, and the first deep grooves are filled with semiconductors of the first doping type. material (such as P-type semiconductor material) to form the first doped region 107a; the epitaxial layer 103 of the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034 has a second deep groove, The second deep groove is filled with a semiconductor material of a second doping type (for example, an N-type semiconductor material) to form a second doping region 108a. In this embodiment, the first deep groove is filled with, for example, boron-doped polysilicon; the doping concentration is 1E17˜1E20 cm −3 . For example, phosphorus-doped polysilicon is filled in the second deep groove; the doping concentration is 1E17˜1E20 cm −3 .

Further, the dimensions of the first deep groove and the second deep groove are the same, and the groove bottoms of the first deep groove and the second deep groove have smooth curves, so that the electric field between the first deep groove and the second deep groove The groove bottom of the second deep groove is evenly distributed, which improves the stability of the product.

In a specific embodiment, the width of the top of the first deep groove and the top of the second deep groove is, for example, 1um˜3um, and the depth is, for example, 2um˜6um. The side walls of the first deep groove and the second deep groove are inclined, and the inclination angle is 89.0°±0.5°.

15a to 15h show cross-sectional views of various stages in the fabrication process of the bidirectional TVS device according to the fifth embodiment of the present invention.

The steps shown in FIG. 15a to FIG. 15d are the same as the steps shown in FIG. 13a to FIG. 13d in the fourth embodiment, and will not be repeated here in this embodiment.

Further, as shown in FIG. 15 e , a first oxide layer 1041 having an opening 1041 a is formed on the epitaxial layer 103 .

In this step, for example, a first oxide layer 1041 is formed on the epitaxial layer 103 by a film growth process, and then an opening 1041a is formed in the first oxide layer 1041 by photolithography and etching. The first oxide layer 1041 is, for example, a silicon oxide (SiO ₂ ) layer with a thickness of, for example, 1.2um.

As shown in FIG. 15f, an isolation structure 105 is formed.

In the step, the epitaxial layer 103, the isolation layer 102 and the substrate 101 are etched through the opening 1041a to form a plurality of isolation trenches. Wherein, each isolation trench penetrates the epitaxial layer 103 and the isolation layer 102 , and extends to the inside of the substrate 101 .

Further, gate oxide growth and polysilicon filling processes are used to fill the isolation trenches, and polysilicon etching or CMP processes are used to remove the polysilicon on the surface of the first oxide layer 1041, leaving only the polysilicon inside the isolation trenches to form isolation structure 105 . The isolation structure 105 divides the semiconductor structure into different regions. In this embodiment, the semiconductor structure is at least isolated to form a first region 1031 , a second region 1032 , a third region 1033 , a fourth region 1034 and a fifth region 1035 .

As shown in FIG. 15g, a first doped region 107a is formed.

In this step, photolithography and etching are performed on the epitaxial layer 103 in the first region 1031 to the fifth region 1035 to form a first deep groove. Specifically, a photoresist is formed on the first oxide layer 1041, and then the photoresist is exposed and developed to form a photoresist mask, and the first oxide layer is etched through the photoresist mask. Layer 1041 forms opening 1041b, and then the photoresist is removed. Further using the first oxide layer 1041 as a hard mask, the epitaxial layer 103 in the first region 1031 to the fifth region 1035 is etched to form a first deep groove. Wherein, in the first region 1031 to the fifth region 1035 , the first deep trench is located in the well region 106 .

Further, a boron-doped polysilicon filling process is used to fill the first deep trench with boron-doped polysilicon to form the first doped region 107a. Specifically, a certain proportion of BCl ₃ and SiH ₄ is fed into the reaction furnace tube, the temperature is 510°C-600°C, and the sheet resistance is 4ohm-20ohm, so that the boron-doped polysilicon can fill the first deep groove, and then The boron-doped polysilicon on the surface of the first oxide layer 1041 is removed by polysilicon etching or CMP process, and only the boron-doped polysilicon in the first deep trench remains, so as to form the first doped region 107a.

In this embodiment, the width of the top of the first deep groove is, for example, 1um-3um, and the depth is, for example, 2um-6um. The side wall of the first deep groove is inclined, and the inclination angle is 89.0°±0.5°. The curve of the groove bottom of the first deep groove is smooth, so that the electric field is evenly distributed on the groove bottom of the first deep groove, and the stability of the product is improved.

Further, as shown in FIG. 15h, a second doped region 108a is formed.

In this step, photolithography and etching are performed on the epitaxial layer 103 in the first region 1031 to the fifth region 1035 to form a second deep groove. Specifically, a photoresist is formed on the first oxide layer 1041, and then the photoresist is exposed and developed to form a photoresist mask, and the first photoresist is etched through the photoresist mask. The oxide layer 1041 forms an opening 1041c, and then the photoresist is removed. Further using the first oxide layer 1041 as a hard mask, the epitaxial layer 103 in the first region 1031 to the fifth region 1035 is etched to form a second deep groove. Wherein, in the first region 1031 to the fourth region 1034, the second deep grooves are located in the epitaxial layer 103 and distributed alternately with the first deep grooves; in the fifth region 1035, the second deep grooves Deep trenches are located in the well region 106 and between the first deep trenches.

Further, the phosphorus-doped polysilicon filling process is used to fill the second deep trench with phosphorus-doped polysilicon to form the second doped region 108a. Specifically, a certain proportion of PH ₃ and SiH ₄ is passed into the reaction furnace tube, the temperature is 510°C-600°C, and the sheet resistance is 4ohm-20ohm, so that the phosphorus-doped polysilicon can fill the second deep groove, and then The phosphorus-doped polysilicon on the surface of the first oxide layer 1041 is removed by polysilicon etching or CMP process, and only the phosphorus-doped polysilicon in the second deep trench remains, so as to form the second doped region 108a.

In this embodiment, the width of the top of the second deep groove is, for example, 1um-3um, and the depth is, for example, 2um-6um. The side wall of the second deep groove is inclined, and the inclination angle is 89.0°±0.5°. The curve of the groove bottom of the second deep groove is smooth, so that the electric field is evenly distributed on the groove bottom of the second deep groove, and the stability of the product is improved.

Further, the annealing process is used to push the junction, so that the junction depth and diffusion width meet the target requirements.

Further, a dielectric layer 109 is formed on the epitaxial layer 103, and a contact hole 1091 is formed in the dielectric layer 109, and a metal interconnection structure is formed.

Fig. 16 shows the sectional view of the bidirectional TVS device of the sixth embodiment of the present invention, as shown in Fig. 16, described bidirectional TVS device comprises substrate 101, isolation layer 102, epitaxial layer 103, isolation structure 105, a plurality of wells region 106, a plurality of first doped regions 107, a plurality of first doped regions 107a, a plurality of second doped regions 108, a plurality of second doped regions 108a, a dielectric layer 109 and a metal interconnection structure.

Different from the first embodiment, in this embodiment, a first doped region 107a is formed under each first doped region 107, and a second doped region is formed under each second doped region 108 108a.

In the fourth embodiment and the fifth embodiment, the contact hole 1091 needs to be inside the first doped region 107a and the second doped region 108a. Since the width of the first deep groove and the second deep groove is small, the The process requirements of the contact hole are relatively high, and generally require 0.35um CMOS process. In this embodiment, the first doped region 107 and the second doped region 108 are respectively increased above the first doped region 107a and the second doped region 108a, and the top widths of the first doped region 107 and the second doped region 108 The width greater than the top of the first doped region 107a and the second doped region 108a reduces the requirements on the process of the contact hole, and at the same time can reduce the contact resistance of the contact hole.

Fig. 17 shows the top view of the bidirectional TVS device of the seventh embodiment of the present invention, as shown in Fig. 17, different from the first embodiment, in this embodiment, in the fifth region, the first doped region 107 The plan views of the doped region and the second doped region 108 are arranged in a rectangle, the side length of the rectangle is 2um-20um, the pitch is 0.5um-5um, and the junction depth is 0.3um-2um.

Fig. 18 shows the top view of the bidirectional TVS device of the eighth embodiment of the present invention, as shown in Fig. 18, different from the first embodiment, in this embodiment, in the fifth region, the first doped region 107 and the second doped region 108 are arranged in a "back shape". Miscellaneous region 108 constitutes the collector, the base and the emitter of NPN triode respectively; In the NPN triode in the present embodiment, electric current can flow into the emitter of outer ring around the collector of inner circle, has increased perimeter area ratio, has improved The emission efficiency and anti-surge ability of NPN triode current. Among them, the side length of the second doped region 108 in the inner circle of the "back shape" is 2um-10um, and the width of the first doped region 107 and the second doped region 108 in the outer circle of the "back shape" is 4um-10um. 12um, the distance between the second doped region 108 of the inner circle and the first doped region 107 or the second doped region 108 of the outer circle is 0.5um-5um. In this embodiment, the number and size of the first doped region and the second doped region are selected according to actual needs.

In addition, the outer circle of part of the "back shape" is the first doped region 107, and the number and area of the first doped region 107 can control the magnitude of the trigger current. The first doped region 107 is connected to the emitter through a metal interconnection structure, so as to short-circuit the base and emitter of the triode.

FIG. 19 shows a top view of a bidirectional TVS device according to the ninth embodiment of the present invention. As shown in FIG. 19, different from the first embodiment, in this embodiment, in the fifth region, the first doped region 107 and the second doped region 108 are arranged in a "ring-shaped" arrangement. In this embodiment, the second doped region of the "ring-shaped" inner circle, the well region, and the second doped The regions constitute the collector, base and emitter of the NPN triode respectively; in the NPN triode in this embodiment, the current can flow into the emitter of the outer ring through the collector of the inner ring, which increases the perimeter area ratio and improves the NPN triode. The current emission efficiency and anti-surge ability are improved, and the electric field distribution is smoother at the same time. Among them, the outer diameter of the first doped region and the second doped region of the "ring-shaped" inner ring is 2um-10um, and the outer diameter of the first doped region and the second doped region of the "ring-shaped" outer ring The diameter is 4um-12um, and the distance between the first doped region and the second doped region of the inner circle and the first doped region and the second doped region of the outer circle is 0.5um-5um. In other embodiments, the number and size of the first doped region and the second doped region are selected according to actual needs.

In addition, the outer circle of a part of the "annular shape" is the first doped region 107, and the number and area of the first doped region 107 can control the magnitude of the trigger current. The first doped region 107 is connected to the emitter through a metal interconnection structure, so as to short-circuit the base and emitter of the triode.

Fig. 20 shows a schematic diagram of the current flow when the first channel I/O1 is applied with a high potential and the second channel I/O2 is applied with a low potential in the bidirectional TVS device of the tenth embodiment of the present invention; wherein, Fig. 20a shows this The cross-sectional view of the bidirectional TVS device according to the tenth embodiment of the invention, Fig. 20b is a top view of the arrangement of the well region, the first doped region and the second doped region in the bidirectional TVS device according to the tenth embodiment of the present invention, Fig. 20c is the A schematic diagram of the circuit connection structure of the bidirectional TVS device according to the tenth embodiment of the invention. Different from the first embodiment, in this embodiment, the first doping type is an N-type doping type, and correspondingly, the second doping type is a P-type doping type.

Specifically, in this embodiment, the substrate 101 is, for example, an N-substrate, and the epitaxial layer 103 is, for example, a P- epitaxial layer; the first doped region 107 is an N+ doped region, and the second The doped region is a P+ doped region. In the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034, the well region 106 is an N well, and the first doped region 107 is located in the well region 106; in the first In the region 1031, the second region 1032, the third region 1933 and the fourth region 1034, a first diode D1, a second diode D2, a third diode D3 and a fourth diode D4 are respectively formed; In the fifth region 1035 , the well region 106 is an N well, and the first doped region 107 and the second doped region 108 are located in the well region 106 ; a PNP transistor is formed in the fifth region 1035 .

The anode of the first diode D1 (the second doped region 108 in the first region 1031) and the cathode of the second diode D2 (the first doped region 107 in the second region 1032 ) connected to the first channel I/O1; the cathode of the first diode D1 (the first doped region 107 in the first region 1031), the cathode of the third diode D3 ( The first doped region 107 in the third region 1033) and the emitter of the PNP transistor (the second doped region 108 forming the emitter of the PNP transistor in the fifth region 1035) are connected together and connected to the power supply Terminal VCC. The anode of the second diode D2 (the second doped region 108 in the second region 1032), the anode of the fourth diode D4 (the second doped region 108 in the fourth region 1034) region 108), the base of the PNP transistor (the first doped region 107 short-circuited with the collector of the PNP transistor in the fifth region 1035) and the collector (the emitter of the PNP transistor is formed in the fifth region 1035 The second doped regions 108) are connected together and grounded to GND. The anode of the third diode D3 (the second doped region 108 in the third region 1033) and the cathode of the fourth diode D4 (the first doped region 107 in the fourth region 1034 ) is connected to the second channel I/O2. Wherein, the emitter of the PNP triode serves as the first potential of the triode, and the collector of the PNP triode serves as the second potential of the triode.

The bidirectional TVS device and the preparation method thereof provided by the present invention adopt a diode and a voltage stabilizing transistor to be integrated into a bidirectional TVS device, and integrate the advantages of the small capacitance of the diode and the Snapback effect of the short circuit between the base and the emitter of the triode, which can Taking into account the advantages of diodes and triodes, it has the characteristics of small capacitance, low residual voltage and appropriate voltage.

In a preferred embodiment, the triode whose base and emitter are short-circuited constitutes the regulator part of the bidirectional TVS device, which has a Snapback characteristic compared with the bidirectional TVS device in the prior art.

Optionally, the triode constitutes the voltage regulator part of the bidirectional TVS device, the base of the triode is open, holes cannot flow out through the base, and the PN junction formed by the base and emitter of the triode has a small opening When the current, generally uA level.

Further, by adjusting the spacing between the second doped regions in the fifth region (the distance between the collector and the emitter of the triode, that is, the width of the base region of the triode) and the implantation dose of the second doped region and the well region That is to say, the breakdown voltage and negative resistance can be adjusted, so that the sustaining voltage of the bidirectional TVS device is greater than the operating voltage, so that it will not cause latch-up problems, and it can also lower the clamping voltage under high current conditions. Power consumption will be less.

Further, since the first diode is exactly the same as the third diode, the second diode is exactly the same as the diode and share the triode, the forward and reverse breakdown voltages of the bidirectional TVS device are equal, and the forward and reverse breakdown voltages are equal. Good voltage consistency.

In a preferred embodiment, the isolation layer is an intrinsic semiconductor layer, and an intrinsic semiconductor layer is provided between the substrate and the epitaxial layer, so that the substrate, the isolation layer, and the The epitaxial layer forms a vertical PIN junction. Compared with the PN junction, the PIN junction can significantly reduce the carrier concentration, thereby reducing the capacitance.

In a preferred embodiment, the isolation layer is an insulating layer, so that the TVS device forms a silicon-on-insulator (SOI, Silicon on Insulator) structure, and devices in different regions are separated by an isolation layer with good insulating properties. The separation can eliminate the opening of bulk silicon parasitic devices, reduce the parasitic capacitance and leakage current between the substrate and the epitaxial layer, and have the advantages of high integration and good radiation resistance.

In a preferred embodiment, the first doped region and/or the second doped region in the triode and/or diode are formed by using a deep trench filling process, and an electric field is introduced from the surface of the device to the inside of the epitaxial layer, improving the device stability and surge immunity.

Furthermore, the first doped region and/or the second doped region of the deep groove structure enables the triode and/or diode to have a larger effective area, which can significantly improve the anti-surge capability and reduce the clamping voltage.

Furthermore, the lateral diffusion of the deep groove structure in the triode and/or diode is small, and under the same area, more minimum repeating units can be made, which improves the current density per unit area and further improves the anti-surge and anti-ESD capabilities of the device. promote.

Furthermore, the ion implantation process is limited by the capability of the implanter, and the ion implantation dose can only be up to 1.0E16 cm ^-2 , and the deep trench filling process is used to form the first doped region and/or The second doping region can make the doping concentration of the first doping region and the second doping region higher, which can improve the emission efficiency of the triode and reduce the contact resistance, thereby improving the _IPP capability and reducing the clamping voltage.

In a preferred embodiment, in the fifth region, the first doped region and the second doped region are arranged in a "back shape", and the second doped region arranged in a "back shape" forms a triode, and current can pass through the inner The collector electrode of the ring flows into the emitter electrode of the outer ring, which increases the perimeter area ratio and improves the emission efficiency and anti-surge capability of the triode current.

In a preferred embodiment, in the fifth region, the first doped region and the second doped region are arranged in a "ring shape", and the second doped region arranged in a "ring shape" forms a triode, and current can pass through The collector electrode of the inner ring flows into the emitter electrode of the outer ring, which increases the perimeter area ratio, improves the emission efficiency and surge resistance of the triode current, and makes the electric field distribution more smooth.

Embodiments according to the present invention are described above, and these embodiments do not describe all details in detail, nor do they limit the invention to only the specific embodiments described. Obviously many modifications and variations are possible in light of the above description. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modification on the basis of the present invention. The invention is to be limited only by the claims, along with their full scope and equivalents.

Claims (31)

1. A bidirectional TVS device, comprising:

a substrate of a first doping type;

an epitaxial layer of a second doping type on the substrate, wherein the second doping type is opposite to the first doping type;

the isolation structure extends from the surface of the epitaxial layer into the substrate, and a first region, a second region, a third region, a fourth region and a fifth region which are isolated from each other are defined in the epitaxial layer; a first diode, a second diode, a third diode and a fourth diode are respectively formed in the first area, the second area, the third area and the fourth area, and a triode is formed in the fifth area; and

and the metal interconnection structure is used for connecting the cathodes of the first diode and the third diode to the first potential of the triode and connecting the anodes of the second diode and the fourth diode to the second potential of the triode.

2. The bidirectional TVS device of claim 1, wherein an anode of said first diode and a cathode of said second diode are connected to a first channel; the cathode of the first diode, the cathode of the third diode and the collector of the triode are connected to a power supply end; the anode of the second diode, the emitter of the triode and the anode of the fourth diode are grounded; an anode of the third diode and a cathode of the fourth diode are connected to a second channel.

3. The bidirectional TVS device of claim 1 or 2, further comprising:

the well region is positioned in the epitaxial layer of the fifth region and has a first doping type;

the first doping area of the first doping type is positioned in the epitaxial layers of the first area, the second area, the third area and the fourth area; and

the second doping area of the second doping type is positioned in the epitaxial layers of the first area, the second area, the third area and the fourth area and in the well area of the fifth area;

in the first region, the second region, the third region and the fourth region, the first doped region, the second doped region and the epitaxial layer respectively form a first diode, a second diode, a third diode and a fourth diode; in the fifth region, the second doped region and the well region form a triode.

4. The bidirectional TVS device of claim 3, wherein the first doped region of the first doping type is further located in the well region of the fifth region, the first doped region in the fifth region being shorted to the second doped region forming an emitter of the transistor to form a transistor with a base shorted to the emitter in the fifth region.

5. The bidirectional TVS device of claim 3, further comprising a well region within said epitaxial layer within said first, second, third, and fourth regions, said first doped region being within said well region, said second doped region being outside said well region.

6. The bidirectional TVS device of claim 1, comprising an isolation layer between said substrate and said epitaxial layer, said isolation structure extending from a surface of said epitaxial layer through said epitaxial layer and said isolation layer and into said substrate.

7. The bidirectional TVS device of claim 6, wherein said isolation layer is an intrinsic semiconductor layer or an insulating layer.

8. The bidirectional TVS device of claim 3, wherein said first doped region comprises:

an implanted region of a first doping type; and/or

A deep trench filled with a semiconductor material of a first doping type;

the second doped region includes:

an implanted region of a second doping type; and/or

A deep trench filled with a semiconductor material of a second doping type.

9. The bidirectional TVS device of claim 8, wherein said first doped region and said second doped region have a width of 1.5um to 20um and a junction depth of 0.3um to 2um.

10. The bidirectional TVS device of claim 8, wherein a top of said first doped region and said second doped region has a width of 1um to 3um; the depth is 2 um-6 um.

11. The bidirectional TVS device of claim 3, wherein the first doped regions alternate with the second doped regions within the first region, the second region, the third region, and the fourth region.

12. The bidirectional TVS device of claim 3, wherein in the fifth region, the first and second doped regions have a shape of one of a stripe, a rectangle, a square, a circular ring, or a combination thereof in a top view.

13. The bidirectional TVS device of claim 1, wherein said first, second, third and fourth regions are arranged in a matrix, and said fifth region is located in a central region of said matrix.

14. The bidirectional TVS device of claim 1, wherein said third diode and said second diode are identical in area and structure, and said fourth diode is identical in area and structure to said second diode.

15. A preparation method of a bidirectional TVS device comprises the following steps:

forming an epitaxial layer of a second doping type on the substrate of the first doping type, wherein the second doping type is opposite to the first doping type;

forming an isolation structure extending from a surface of the epitaxial layer into the substrate, defining a first region, a second region, a third region, a fourth region and a fifth region in the epitaxial layer, wherein the first region, the second region, the third region, the fourth region and the fifth region are isolated from each other; a first diode, a second diode, a third diode and a fourth diode are respectively formed in the first area, the second area, the third area and the fourth area, and a triode is formed in the fifth area; and

forming a metal interconnect structure connecting cathodes of the first diode and the third diode to a first potential of the triode and anodes of the second diode and the fourth diode to a second potential of the triode.

16. The method of claim 15, wherein an anode of the first diode and a cathode of the second diode are connected to a first channel; the cathode of the first diode, the cathode of the third diode and the collector of the triode are connected to a power supply end; the anode of the second diode, the emitter of the triode and the anode of the fourth diode are grounded; an anode of the third diode and a cathode of the fourth diode are connected to a second channel.

17. The method of fabricating a bidirectional TVS device according to claim 15 or 16, further comprising, before or after forming the isolation structure:

forming a well region in the epitaxial layer of the fifth region, wherein the well region has a first doping type;

forming a first doping area of a first doping type in the epitaxial layers of the first area, the second area, the third area and the fourth area; and

forming a second doping area of the second doping type in the epitaxial layers of the first area, the second area, the third area and the fourth area and in the well area of the fifth area;

in the first region, the second region, the third region and the fourth region, the first doped region, the second doped region and the epitaxial layer respectively form a first diode, a second diode, a third diode and a fourth diode; in the fifth region, the second doped region and the well region form a triode.

18. The method of fabricating a bidirectional TVS device of claim 17, further comprising, either before or after forming said isolation structure: and forming a first doping area of the first doping type in the fifth area, wherein the first doping area in the fifth area is in short circuit with a second doping area for forming an emitter of the triode so as to form the triode with a base electrode in short circuit with the emitter in the fifth area.

19. The method of fabricating a bidirectional TVS device of claim 17, further comprising, before or after forming said isolation structure: and forming a well region in the epitaxial layer in the first region, the second region, the third region and the fourth region, wherein the first doped region is positioned in the well region, and the second doped region is positioned outside the well region.

20. The method of fabricating a bidirectional TVS device of claim 15, wherein before forming said epitaxial layer, further comprising: and forming an isolation layer on the substrate, wherein the isolation structure penetrates through the epitaxial layer and the isolation layer from the surface of the epitaxial layer and extends into the substrate.

21. The method of fabricating a bidirectional TVS device of claim 20, wherein said isolation layer is an intrinsic semiconductor layer or an insulating layer.

22. The method of making a bidirectional TVS device of claim 17, wherein said first doped region comprises:

an implanted region of a first doping type; and/or

A deep trench filled with a semiconductor material of a first doping type;

the second doped region includes:

an implanted region of a second doping type; and/or

A deep trench filled with a semiconductor material of a second doping type.

23. The method of claim 22, wherein the first doping type implant region or the second doping type implant region is formed by ion implantation.

24. The method of fabricating a bidirectional TVS device of claim 22, wherein the method of forming the deep trench filled with the semiconductor material of the first doping type or the semiconductor material of the second doping type comprises:

forming a deep trench extending from a surface of the epitaxial layer to an interior of the epitaxial layer; and

and filling the deep groove with a semiconductor material of a first doping type or a semiconductor material of a second doping type to form a first doping region or a second doping region.

25. The method of claim 24, wherein the semiconductor material of the first doping type is polysilicon doped with boron; the doping concentration is 1E 17-1E 20cm-3; the semiconductor material of the second doping type is polysilicon doped with phosphorus, and the doping concentration is 1E 17-1E 20cm-3.

26. The method of claim 22, wherein the first doped region and the second doped region have a width of 1.5um to 20um and a junction depth of 0.3um to 2um.

27. The method of claim 22, wherein the width of the top of the first doped region and the second doped region is between 1um and 3um; the depth is 2 um-6 um.

28. The method of claim 17, wherein the first doped regions alternate with the second doped regions in the first region, the second region, the third region and the fourth region.

29. The method of claim 17, wherein in the fifth region, the first doped region and the second doped region have one or a combination of a stripe shape, a rectangular shape, a zigzag shape and a circular shape in a plan view.

30. The method of fabricating a bidirectional TVS device as set forth in claim 15, wherein said first, second, third and fourth regions are arranged in a matrix, and said fifth region is located in a central region of said matrix.

31. The method of claim 15, wherein the area and structure of said third diode and said second diode are identical, and the area and structure of said fourth diode and said second diode are identical.

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