CN115497824A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, which are applied in the technical field of semiconductors. Specifically, in the manufacturing method provided by the present invention, the depth of the field oxygen isolation structure LOCOS in the semiconductor substrate is deepened by increasing the etching time of the active region, so it is used to form the LOCOS structure When the groove is formed, a certain siliconloss of the semiconductor substrate will be formed. Therefore, the depth of the LOCOS structure obtained in this way can be deepened, and the depth of the formed LOCOS is required to be greater than the junction depth of the N+ and P+ of the NPN. At the same time, the NPN device structure The impact of the manufacturing process is small, that is, while the production cost can not be increased, the problem of unstable beta parameters of the NPN device structure caused by the fluctuation of the metal plug etching is avoided.

Description

Semiconductor structure and manufacturing method thereof

technical field

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.

Background technique

The BCD process is a monolithic integration process technology, which was successfully developed by STMicroelectronics (ST) in 1986. This technology can make bipolar transistor (Bipolar Junction Transistor), CMOS and DMOS devices on the same chip. The BCD process not only combines the advantages of high transconductance, strong load driving capability of bipolar devices, high integration and low power consumption of CMOS, but also integrates DMOS power devices with fast switching speed. Since DMOS has the characteristics of high speed and high current capability at the same time, the withstand voltage is usually high, so the power management chip manufactured by BCD process can work under high frequency, high voltage and high current, which is an ideal process for manufacturing high performance power chip . The monolithic integrated chip manufactured by the BCD process can also improve system performance, save circuit packaging costs, and have better reliability. The main application fields of BCD technology are power management (power supply and battery control), display drive, automotive electronics, industrial control and other fields. Due to the continuous expansion of the application field of the BCD process, the requirements for the BCD process are getting higher and higher. Recently, the BCD process is mainly differentiated and developed in the direction of high voltage, high power, and high density.

FIG. 1 is a schematic structural diagram of an NPN device structure (bipolar transistor) in the current BCD process. It can be seen from FIG. 1 that beta=Ic/Ib of the NPN device structure, and the Ib current path is mainly the A path and the D path in FIG. 1 . In the actual process, the CT etching depth will have normal fluctuations or in-plane distribution. When the CT etching depth is shallower, most of the Ib current is the A path current. When the CT etching depth is deeper, the CT is closer to At the bottom of the Emmiter (emitter) junction, most of the Ib current is the D path current, because the PW concentration flowing through D is lighter than the PW concentration flowing through A, so the beta dominated by the D path is larger than the beta dominated by the A path, which in turn leads to The beta instability problem of the NPN device structure.

Contents of the invention

The object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, so as to solve the problem of unstable beta of the NPN device structure caused by CT etching depth fluctuations in the NPN device structure in the prior art.

In the first aspect, in order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor structure, which at least includes the following steps:

A semiconductor substrate is provided, a first deep well is formed in the semiconductor substrate, and an oxide layer, a nitride layer and a hard mask layer are sequentially stacked on the surface of the semiconductor substrate;

Using the hard mask layer as a mask, etching the nitride layer, the oxide layer and the partial thickness of the semiconductor substrate to form a plurality of discrete layers composed of the etched nitride layer and oxide layer While stacking structures, forming a plurality of trenches in the semiconductor substrate between adjacent stack structures;

Forming a field oxygen isolation structure in each of the trenches, and performing ion implantation on the semiconductor substrate between two adjacent field oxygen isolation structures to form a collector, a base, and an emitter of an NPN structure;

forming metal plugs for electrically externally connecting the collector, base, and emitter of the NPN structure, wherein the metal plugs are inserted into the semiconductor substrate corresponding to the collector, base, and emitter The depth is smaller than the depth of the field oxygen isolation structure in the semiconductor substrate.

Further, the oxide layer may be silicon dioxide, and the nitride layer may be silicon nitride.

Further, the depth range of the groove can be

Further, the depth range of the field oxygen isolation structure along the direction perpendicular to the semiconductor substrate may be

Further, after forming the field oxygen isolation structure and before forming the collector, base and emitter of the NPN structure, the method may further include:

forming a sacrificial oxide layer, the sacrificial oxide layer covering part of the top surface of the semiconductor substrate corresponding to the first deep well;

Using the sacrificial oxide layer as a mask, an ion implantation process is performed on the semiconductor substrate not covered by the sacrificial oxide layer to form a second deep well in the first deep well.

Further, the first deep well may be an N-type well, and the second deep well may be a P-type well.

Further, after forming the second deep well, the method may further include: performing rapid thermal annealing on the semiconductor substrate, and removing the sacrificial oxide layer by using a wet etching process.

Further, the thickness range of the sacrificial oxide layer can be

Further, the step of forming the collector, base and emitter of the NPN structure may include:

Performing N-type ion implantation on the surface of the part of the semiconductor substrate corresponding to the second deep well to form an emitter of an NPN structure in the part of the semiconductor substrate corresponding to the second deep well;

Performing P-type ion implantation on the surface of the remaining semiconductor substrate corresponding to the second deep well again, so as to form NPN structures located on both sides of the emitter in the remaining semiconductor substrate corresponding to the second deep well the base of ; and,

N-type ion implantation is further performed on the semiconductor substrate of the first deep well except the second deep well, so as to form a collection of the NPN structure in the semiconductor substrate corresponding to the first deep well. electrode.

Further, the junction depth of the ion implantation region correspondingly formed in the semiconductor substrate where the emitter and the base of the NPN structure are located needs to be smaller than the depth of the field oxygen isolation structure along a direction perpendicular to the semiconductor substrate.

In the second aspect, based on the same inventive concept, the present invention also provides an NPN device structure, which can be specifically prepared by using the above-mentioned semiconductor structure manufacturing method.

Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

In the manufacturing method of the semiconductor structure provided by the present invention, the emitter of the NPN structure is separated from the lead-out end of the metal plug at the base end by the field oxygen isolation structure LOCOS, and the field oxygen isolation structure LOCOS is required to be in the semiconductor substrate The depth of the NPN structure is deeper than that of the lead-out end of the metal plug at the emitter and base terminals of the NPN structure in the semiconductor substrate, so that the current path of the A path can be eliminated, that is, a larger beta can be obtained, and the metal plug can be avoided. The beta parameter of the NPN structure is changed due to the change of the plug etching depth, that is, the beta parameter of the NPN structure is stabilized.

Further, in the manufacturing method provided by the present invention, the depth of the field oxygen isolation structure LOCOS in the semiconductor substrate is deepened by increasing the etching time of the active region, so it is used to form the LOCOS structure When the groove is formed, a certain siliconloss of the semiconductor substrate will be formed. Therefore, the depth of the LOCOS structure obtained in this way can be deepened, and the depth of the formed LOCOS is required to be greater than the junction depth of the N+ and P+ of the NPN. At the same time, the NPN device structure The impact of the manufacturing process is small, that is, while the production cost can not be increased, the problem of unstable beta parameters of the NPN device structure caused by the fluctuation of the etching of the metal plug is avoided.

Description of drawings

Fig. 1 is the structural representation of the NPN device structure (bipolar transistor) in the current BCD technology;

2 is a flowchart of a method for manufacturing a semiconductor structure in an embodiment of the present invention;

3a to 3d are structural schematic diagrams of a semiconductor structure provided in an embodiment of the present invention during the manufacturing process;

Wherein, the reference signs are as follows:

100-semiconductor substrate; 110-oxide layer;

120-nitride layer; 130-hard mask layer;

140 - metal plug; NDW - first deep well;

Pwell - the second deep well.

detailed description

As mentioned in the background technology, at present, in the actual process, the CT etching depth will have normal fluctuations or in-plane distribution. When the CT etching depth is shallower, most of the Ib current is the A path current. When the CT etching depth When the depth is deeper, CT is closer to the bottom of the Emmiter (emitter) junction, and most of the Ib current is the current of the D path, because the concentration of PW flowing through D is lighter than that of PW flowing through A, so the beta dominated by the D path is stronger than that of the A path The dominant beta is large, which in turn leads to the instability of the beta of the NPN device structure.

Based on this, the present invention provides a semiconductor structure and its manufacturing method to solve the problem of unstable beta of the NPN device structure caused by CT etching depth fluctuations in the NPN device structure in the prior art.

For example, referring to FIG. 2, the method for manufacturing a semiconductor structure provided by the present invention at least includes the following steps:

Step S100, providing a semiconductor substrate, in which a first deep well is formed, and an oxide layer, a nitride layer and a hard mask layer are sequentially stacked on the surface of the semiconductor substrate;

Step S200, using the hard mask layer as a mask to etch the nitride layer, oxide layer and a part of the thickness of the semiconductor substrate, so as to form the nitride layer and oxide layer after etching While multiple discrete stack structures are formed, multiple trenches are formed in the semiconductor substrate between adjacent stack structures;

Step S300, forming a field oxygen isolation structure in each of the trenches, and performing ion implantation on the semiconductor substrate between two adjacent field oxygen isolation structures, so as to form a collector, a base and an NPN structure. emitter;

Step S400, respectively forming metal plugs for electrically externally connecting the collector, base, and emitter of the NPN structure, wherein the metal plugs are inserted into the semiconductor substrate corresponding to the collector, base, and emitter The depth in the bottom is smaller than the depth of the field oxygen isolation structure in the semiconductor substrate.

That is, in the manufacturing method of the semiconductor structure provided by the present invention, the emitter of the NPN structure and the lead-out end of the metal plug at the base end are separated by the field oxygen isolation structure LOCOS, and the field oxygen isolation structure LOCOS is required to be formed on the semiconductor substrate. The depth inside the bottom is deeper than the depth of the lead-out end of the metal plug of the emitter and base terminals of the NPN structure in the semiconductor substrate, so that the current path of the A path can be eliminated, that is, a larger beta can be obtained, and a larger beta can be obtained. The change of the beta parameter of the NPN structure caused by the change of the etching depth of the metal plug is avoided, that is, the beta parameter of the NPN structure is stabilized. Further, in the manufacturing method provided by the present invention, the depth of the field oxygen isolation structure LOCOS in the semiconductor substrate is deepened by increasing the etching time of the active region, so it is used to form the LOCOS structure When the groove is formed, a certain silicon loss of the semiconductor substrate will be formed. Therefore, the depth of the LOCOS structure obtained in this way can be deepened, and the depth of the formed LOCOS is required to be greater than the junction depth of the N+ and P+ of the NPN. At the same time, the NPN device The influence of the manufacturing process of the structure is small, that is, while the production cost can not be increased, the problem of unstable beta parameters of the NPN device structure caused by metal plug etching fluctuations is avoided.

The semiconductor structure and its manufacturing method proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention. In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways than those described here, so the present invention is not limited by the specific embodiments disclosed below.

As indicated in this application and claims, the terms "a", "an", "an" and/or "the" do not refer to the singular and may include the plural unless the context clearly indicates an exception. Generally speaking, the terms "comprising" and "comprising" only suggest the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and the method or device may also contain other steps or elements. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

3a to 3d are structural schematic diagrams of a method for manufacturing a semiconductor structure in an embodiment of the present invention.

In step S100, specifically referring to FIG. 3a, a semiconductor substrate 100 is provided, in which a first deep well DNW is formed, and on the surface of the semiconductor substrate 100, sequentially stacked wells are formed. oxide layer 110 , nitride layer 120 and hard mask layer 130 . Wherein, the semiconductor substrate 100 may be a silicon-on-insulator substrate (SOI), which has a bottom semiconductor layer (not shown), an insulating buried layer (not shown) and a top semiconductor layer (not shown) stacked sequentially from bottom to top. shown), the material of the bottom semiconductor layer and the top semiconductor layer can be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors, the material of the buried insulating layer may include silicon dioxide. Exemplarily, in the embodiment of the present invention, the semiconductor substrate 100 is a conductive silicon substrate. The oxide layer 110 may be silicon dioxide, the nitride layer 120 may be silicon nitride, and the hard mask layer 130 may be a photoresist layer.

In this embodiment, a semiconductor substrate 100 whose substrate material is a silicon substrate can be provided first, and P-type ion implantation is performed on it to form a P-type doped silicon substrate 100; A photoresist layer (not shown) is formed on both sides of the bottom 100 (or called the semiconductor substrate 100) to expose the surface of the middle portion of the silicon P-type doped silicon substrate 100, and then using ion implantation process, N-type ion implantation is performed on the middle part of the P-type doped silicon substrate 100, and then the N-high-resistance region is formed after high-temperature push-well, that is, the first deep well DNW as shown in FIG. 3a.

In step S200, specifically referring to FIG. 3b, using the hard mask layer 130 as a mask, etch the nitride layer 110, the oxide layer 120 and the semiconductor substrate 100 with a partial thickness, so as to form While forming a plurality of discrete stack structures 251 composed of the nitride layer 110 and the oxide layer 120 after etching, a plurality of trenches 101 are formed in the semiconductor substrate 100 between adjacent stack structures 251 .

具体可以为

和

In this embodiment, after the above step S100 is performed, a silicon dioxide layer, a silicon nitride layer and a photoresist layer may be sequentially deposited and formed on the surface of the semiconductor substrate 100, and then the photoresist layer is used as The mask is vertically etched downward along the direction perpendicular to the surface of the semiconductor substrate 100, for example, it is a wet etching process, so as to form the stacked structure 251 as shown in FIG. A groove 101 with a certain depth is formed inside the bottom 100 . Wherein, the depth range of the groove 101 can be exemplarily

Specifically, it can be

with

It should be noted that, in the present invention, the process of etching the hard mask layer 130 to form a plurality of discrete stack structures 251 composed of the etched nitride layer 110 and oxide layer 120 is defined as The active region of the NPN device structure is formed, and the region between two adjacent discrete stack structures 251 is the region for forming the LOCOS field oxygen isolation structure. Moreover, in this process, it deepens the depth of the field oxygen isolation structure LOCOS in the semiconductor substrate (ie, the process of forming the stack structure 251 in step S200) by increasing the etching time of the active region (ie, the process of forming the stack structure 251 in step S200). is the groove 101), so when forming the groove for forming the LOCOS structure, it will form a certain situation of silicon loss of the semiconductor substrate, therefore, the depth of the LOCOS structure obtained in this way can be deepened, and at the same time, the NPN device structure The manufacturing process is less affected. Moreover, at the same time, the junction depth of the corresponding ion implantation region formed in the semiconductor substrate 100 where the emitter and the base of the NPN structure formed in the subsequent steps needs to be smaller than that of the field oxygen isolation structure LOCOS along the vertical direction of the semiconductor substrate. 100 for the depth of direction.

In step S300, specifically referring to FIG. 3c, a field oxygen isolation structure LOCOS is formed in each of the trenches 101, and the semiconductor substrate 100 between two adjacent field oxygen isolation structures LOCOS is ionized. Implanted to form the collector C, base B and emitter E of the NPN structure.

再执行步骤S302，以所述牺牲氧化层为掩膜，对未被所述牺牲氧化层覆盖的半导体衬底100进行离子注入工艺，以在所述第一深阱中形成第二深阱Pwell。之后，在执行步骤S303，对所述半导体衬底100进行快速热退火处理，并利用湿法刻蚀工艺去除所述牺牲氧化层。最后，在利用多步离子注入工艺，分别形成NPN结构的集电极C、基极B和发射极E。In this embodiment, the field oxygen isolation structure LOCOS in FIG. 3c can be formed by using the existing formation process of the field oxygen isolation structure, and then, in step S301, a sacrificial oxide layer (not shown) is formed, so The sacrificial oxide layer covers part of the top surface of the semiconductor substrate 100 corresponding to the first deep well DNM; wherein, the thickness range of the sacrificial oxide layer is

Step S302 is then performed, using the sacrificial oxide layer as a mask to perform an ion implantation process on the semiconductor substrate 100 not covered by the sacrificial oxide layer, so as to form a second deep well Pwell in the first deep well. Afterwards, in step S303 , rapid thermal annealing is performed on the semiconductor substrate 100 , and the sacrificial oxide layer is removed by using a wet etching process. Finally, using a multi-step ion implantation process, the collector C, the base B and the emitter E of the NPN structure are respectively formed.

Exemplarily, in the embodiment of the present invention, it provides a specific step of forming the collector C, base B and emitter E of the NPN structure, including:

Performing N-type ion implantation on the surface of the part of the semiconductor substrate 100 corresponding to the second deep well Pwell to form an emitter E of an NPN structure in the part of the semiconductor substrate 100 corresponding to the second deep well Pwell;

Perform P-type ion implantation on the surface of the remaining semiconductor substrate 100 corresponding to the second deep well Pwell again, so as to form a the base B of the NPN structure on both sides; and,

N-type ion implantation is further performed on the semiconductor substrate 100 of the first deep well DNW except the second deep well Pwell, so as to form the semiconductor substrate 100 corresponding to the first deep well DNW. The collector C of the NPN structure.

示例性的其具体可以为：

和

It should be noted that, in the embodiment of the present invention, the depth range of the field oxygen isolation structure LOCOS along the direction perpendicular to the semiconductor substrate 100 may be

Exemplary details can be:

with

In step S400, specifically referring to FIG. 3d, metal plugs 140 for electrically externally connecting the collector C, base B, and emitter E of the NPN structure are respectively formed, wherein the metal plugs 140 are inserted into the The depth in the semiconductor substrate 100 corresponding to the collector C, the base B and the emitter E is smaller than the depth of the field oxygen isolation structure LOCOS in the semiconductor substrate 100 .

In this embodiment, a BPSG (interlayer insulating film) can be deposited on the surface of the semiconductor substrate 100 first, and then the film layer is smoothed by using a chemical mechanical polishing process CMP, and then an etching process is used to form a layer for electrical external connection. The metal plugs of the collector C, base B, and emitter E of the NPN structure, that is, define the CT region by CT lithography, etch, fill W, deposit metal, and define the metal plug by metal lithography The wiring area is etched to complete the connection of each terminal of the BJT.

In summary, in the manufacturing method of the semiconductor structure provided by the present invention, the emitter of the NPN structure and the lead-out end of the metal plug at the base end are separated by the field oxygen isolation structure LOCOS, and the field oxygen isolation structure LOCOS is required The depth in the semiconductor substrate is deeper than that of the lead-out end of the metal plug of the emitter and base terminals of the NPN structure in the semiconductor substrate, so that the current path of the A path can be eliminated, that is, a larger beta can be obtained , and can avoid the change of the beta parameter of the NPN structure caused by the change of the etching depth of the metal plug, that is, the beta parameter of the NPN structure is stabilized.

Further, in the manufacturing method provided by the present invention, the depth of the field oxygen isolation structure LOCOS in the semiconductor substrate is deepened by increasing the etching time of the active region, so it is used to form the LOCOS structure When the groove is formed, a certain silicon loss of the semiconductor substrate will be formed. Therefore, the depth of the LOCOS structure obtained in this way can be deepened, and the depth of the formed LOCOS is required to be greater than the junction depth of the N+ and P+ of the NPN. At the same time, the NPN device The influence of the manufacturing process of the structure is small, that is, while the production cost can not be increased, the problem of unstable beta parameters of the NPN device structure caused by metal plug etching fluctuations is avoided.

After that, the present invention also provides an NPN device structure based on the same concept as the above-mentioned inventive concept of the manufacturing method of the semiconductor structure. Specifically, the depth of the field oxygen isolation structure LOCOS of the NPN device structure provided in the embodiment of the present invention in the semiconductor substrate is deeper than that of the field oxygen isolation structure LOCOS of other NPN device structures in the prior art.

It should be noted that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or be modified to be equivalent to equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the content of the technical solution of the present invention, still belong to the scope of protection of the technical solution of the present invention.

It should also be understood that, unless otherwise specified or pointed out, the terms “first”, “second”, “third” and other descriptions in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than It is used to express the logical relationship or sequence relationship between various components, elements, and steps.

In addition, it should be understood that the terminology described herein is used to describe particular embodiments only and is not intended to limit the scope of the invention. It must be noted that as used herein and in the appended claims, the singular forms "a" and "an" include plural referents unless the context clearly dictates otherwise. For example, a reference to "a step" or "a means" means a reference to one or more steps or means, and may include sub-steps as well as sub-means. All conjunctions used should be understood in their broadest sense. And, the word "or" should be understood as having the definition of logical "or" rather than logical "exclusive or", unless the context clearly expresses the contrary meaning. Additionally, implementation of the method and/or apparatus in embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims (11)

1. A method of fabricating a semiconductor structure, comprising:

providing a semiconductor substrate, wherein a first deep well is formed in the semiconductor substrate, and an oxide layer, a nitride layer and a hard mask layer which are sequentially stacked are formed on the surface of the semiconductor substrate;

etching the nitride layer, the oxide layer and the semiconductor substrate with partial thickness by taking the hard mask layer as a mask so as to form a plurality of discrete stacked structures consisting of the etched nitride layer and the etched oxide layer and a plurality of grooves in the semiconductor substrate between the adjacent stacked structures;

forming a field oxygen isolation structure in each groove, and performing ion implantation on the semiconductor substrate between two adjacent field oxygen isolation structures to form a collector, a base and an emitter of an NPN structure;

and respectively forming metal plugs for electrically connecting the collector, the base and the emitter of the NPN structure externally, wherein the depth of the metal plugs inserted into the semiconductor substrate corresponding to the collector, the base and the emitter is less than the depth of the field oxygen isolation structure in the semiconductor substrate.

2. The method of fabricating a semiconductor structure according to claim 1, wherein the oxide layer is silicon dioxide and the nitride layer is silicon nitride.

3. The method of claim 1, wherein the trench has a depth in a range of about

4. The method of claim 1, wherein the field oxide isolation structures have a depth in a direction perpendicular to the semiconductor substrate in a range of

5. The method of fabricating a semiconductor structure of claim 1, wherein after forming the field oxygen isolation structure and before forming a collector, a base, and an emitter of the NPN structure, the method further comprises:

forming a sacrificial oxide layer, wherein the sacrificial oxide layer covers a part of the top surface of the semiconductor substrate corresponding to the first deep well;

and carrying out an ion implantation process on the semiconductor substrate which is not covered by the sacrificial oxide layer by taking the sacrificial oxide layer as a mask so as to form a second deep well in the first deep well.

6. The method of fabricating a semiconductor structure of claim 5, wherein the first deep well is an N-type well and the second deep well is a P-type well.

7. The method of fabricating a semiconductor structure of claim 6, wherein after forming the second deep well, the method further comprises: and carrying out rapid thermal annealing treatment on the semiconductor substrate, and removing the sacrificial oxide layer by utilizing a wet etching process.

8. The method of fabricating a semiconductor structure according to claim 7, wherein the sacrificial oxide layer has a thickness in a range of

9. The method of fabricating a semiconductor structure according to claim 8, wherein the step of forming a collector, a base, and an emitter of the NPN structure comprises:

carrying out N-type ion implantation on the surface of the part of the semiconductor substrate corresponding to the second deep well so as to form an emitter of an NPN structure in the part of the semiconductor substrate corresponding to the second deep well;

performing P-type ion implantation on the surface of the remaining semiconductor substrate corresponding to the second deep well again to form base electrodes of the NPN structure located at two sides of the emitter in the remaining semiconductor substrate corresponding to the second deep well; and the number of the first and second groups,

and further carrying out N-type ion implantation on the semiconductor substrate of the first deep well except the second deep well so as to form a collector of the NPN structure in the semiconductor substrate corresponding to the first deep well.

10. The method according to claim 9, wherein a junction depth of the ion implantation regions formed in the semiconductor substrate corresponding to the emitter and the base of the NPN structure is smaller than a depth of the field oxygen isolation structure in a direction perpendicular to the semiconductor substrate.

11. An NPN device structure produced by the method for manufacturing a semiconductor structure according to any one of claims 1 to 10.

Images