CN115474914A - Pulse diagnosis instrument - Google Patents

Abstract

The application relates to a pulse diagnosis instrument, which comprises a host, at least two first measuring assemblies and at least two second measuring assemblies. The first measuring component is used for acquiring a first sound signal under the pressure of a first target area of a human body, and the first target area comprises an area of a part to be diagnosed and is larger than the area of the part to be diagnosed; the second measurement assembly is used for acquiring a second sound signal of a second target area of the human body; and the host is used for obtaining a first measurement result according to the first sound signal and obtaining a second measurement result according to the second sound signal. The pulse diagnosis instrument has high accuracy and stability of measurement results and rich diversity of the measurement results.

Description

Pulse diagnosis instrument

technical field

The present application relates to the technical field of medical devices, in particular to a pulse diagnosis instrument.

Background technique

The pulse diagnosis instrument is a kind of instrument that can obtain the pulse or blood pressure changes in the arms and heart. The pulse diagnosis instrument in the prior art is to compress the arteries of the measured parts of the human body through gas, and use the pressure sensor to detect the light, medium and heavy states. The weak changes in the pulse are converted into electrical signals, and then the signal waveform is obtained through signal processing.

However, the pulse diagnosis instrument in the prior art has an error in the measured site for each measurement, which leads to very unstable tests and inaccurate test results.

Contents of the invention

Based on this, it is necessary to provide a pulse diagnosis instrument with accurate test results, high stability and rich diversity in view of the above technical problems.

In a first aspect, the present application provides a pulse diagnosis instrument, which includes a host, at least two first measurement components and at least two second measurement components;

The first measurement component is used to collect the first sound signal under the pressure of the first target area of the human body, the first target area includes the area of the site to be diagnosed and is larger than the area of the site to be diagnosed;

The second measurement component is configured to collect a second sound signal of a second target area of the human body;

The host is configured to obtain a first measurement result according to the first sound signal, and obtain a second measurement result according to the second sound signal.

In one of the embodiments, the host includes a processor, a conversion module, a voltage management module, and an air pressure adjustment module, and the conversion module, the voltage management module, and the air pressure adjustment module are all connected to the processor;

The voltage management module is used to control the voltage rise and fall of the processor;

The air pressure adjustment module is used to control the first measurement component to pressurize and release the first target area;

The converting module is configured to convert the first sound signal into a first digital signal, and convert the second sound signal into a second digital signal;

The processor is configured to obtain the first measurement result according to the first digital signal, and obtain the second measurement result according to the second digital signal.

In one of the embodiments, the voltage management module includes a switch module, a step-down control module, a first step-down module, a second step-down module and a first power supply module;

The switch module, the step-down control module, the first step-down module, the second step-down module and the first power supply module are all connected to the processor.

In one of the embodiments, the sphygmomanometer includes two first measurement components, both of which are connected to the air pressure adjustment module.

In one of the embodiments, the air pressure adjustment module includes a second power supply module, a first air pressure adjustment sub-module and a second air pressure adjustment sub-module, and the first air pressure adjustment sub-module is connected with two of the first measurement components The second air pressure adjustment sub-module is connected to the other measurement component of the two first measurement components.

In one of the embodiments, the first air pressure adjustment sub-module includes a first air pressure detection module, a first drive module, a first air pump module, a first air release valve module, and a first air release valve fine-tuning module;

The second air pressure regulation sub-module includes a second air pressure detection module, a second drive module, a second air pump module, a second air release valve module, and a second air release valve trimming module.

In one of the embodiments, the host computer further includes a power supply detection module and a voltage acquisition module, both of which are connected to the processor.

In one of the embodiments, the power supply detection module includes a first detection submodule, a second detection submodule, a third detection submodule, a fourth detection submodule, a fifth detection submodule, a sixth detection submodule and a sixth detection submodule. Seven detection sub-modules.

In one of the embodiments, the host also includes a USB-TYPE module, an external switch module, a battery interface module, an extension indicator module, a status indicator module, a debugging button module, a display module, a storage module, and a Bluetooth module. - TYPE module, the external switch module, the battery interface module, the expansion indicator module, the status indicator module, the debugging button module, the display module, the storage module and the Bluetooth module connected to said processor;

The second measurement component is connected with the USB-TYPE module.

In one of the embodiments, the first measurement component includes a pressure belt, and the length of the pressure belt is 3cm-15cm;

The second measurement assembly includes a stethoscope.

The above pulse diagnosis instrument includes a host, at least two first measuring components and at least two second measuring components. The first measurement component is used to collect the first sound signal under the pressure of the first target area of the human body, the first target area includes the area of the part to be diagnosed and is larger than the area of the part to be diagnosed; the second measurement component is used to for collecting a second sound signal of the second target area of the human body; the host is used for obtaining a first measurement result according to the first sound signal, and obtaining a second measurement result according to the second sound signal. The first target area includes the area of the site to be diagnosed and is larger than the area of the site to be diagnosed, and the first measurement component can collect the first sound signal under the pressure of a larger range, which can improve the accuracy and accuracy of the measurement results of the pulse diagnosis instrument. stability. In addition, using the second measurement component to collect the second sound signal of the second target area of the human body can enrich the diversity of measurement results.

Description of drawings

Fig. 1 is the structural representation of the pulse diagnosis instrument provided by the embodiment of the present application;

FIG. 2 is one of the structural block diagrams of the host in an embodiment of the present application;

Fig. 3 is a circuit diagram of a processor in an embodiment of the present application;

Fig. 4 is the circuit diagram of conversion module in one embodiment of the present application;

Fig. 5 is a structural block diagram of a voltage management module in an embodiment of the present application;

Fig. 6 is the circuit diagram of switch machine module in one embodiment of the present application;

FIG. 7 is a circuit diagram of a buck-boost control module in an embodiment of the present application;

FIG. 8 is a circuit diagram of a first step-down module in an embodiment of the present application;

FIG. 9 is a circuit diagram of a second step-down module in an embodiment of the present application;

Fig. 10 is a circuit diagram of a first power supply module in an embodiment of the present application;

Fig. 11 is a structural block diagram of an air pressure regulating module in an embodiment of the present application;

Fig. 12 is a circuit diagram of a second power supply module in an embodiment of the present application;

Fig. 13 is a circuit diagram of the first air pressure detection module in an embodiment of the present application;

Fig. 14 is a circuit diagram of a first driving module in an embodiment of the present application;

Fig. 15 is a circuit diagram of the first air pump module in one embodiment of the present application;

Fig. 16 is a circuit diagram of the first air release valve module in one embodiment of the present application;

Fig. 17 is a circuit diagram of the first leak valve fine-tuning module in an embodiment of the present application;

Fig. 18 is a circuit diagram of the second air pressure detection module in one embodiment of the present application;

Fig. 19 is a circuit diagram of a second driving module in an embodiment of the present application;

Fig. 20 is a circuit diagram of a second air pump module in an embodiment of the present application;

Fig. 21 is a circuit diagram of the second air release valve module in one embodiment of the present application;

Fig. 22 is a circuit diagram of the second air leakage valve trimming module in an embodiment of the present application;

Fig. 23 is a frame diagram of a power supply detection module in an embodiment of the present application;

Fig. 24 is a circuit diagram of the first detection sub-module in an embodiment of the present application;

Fig. 25 is a circuit diagram of the second detection sub-module in an embodiment of the present application;

Fig. 26 is a circuit diagram of a third detection sub-module in an embodiment of the present application;

Fig. 27 is a circuit diagram of the fourth detection sub-module in an embodiment of the present application;

Fig. 28 is a circuit diagram of the fifth detection sub-module in an embodiment of the present application;

Fig. 29 is a circuit diagram of the sixth detection sub-module in an embodiment of the present application;

Fig. 30 is a circuit diagram of the seventh detection sub-module in an embodiment of the present application;

Fig. 31 is a circuit diagram of a voltage acquisition module in an embodiment of the present application;

Figure 32 is one of the structural block diagrams of the host in an embodiment of the present application;

Fig. 33 is a circuit diagram of the Bluetooth module in one embodiment of the present application;

Fig. 34 is a circuit diagram of a USB-TYPE module in an embodiment of the present application;

Fig. 35 is a circuit diagram of an external switch module in an embodiment of the present application;

Fig. 36 is a circuit diagram of a battery interface module in an embodiment of the present application;

Fig. 37 is a circuit diagram of an extended indication module in an embodiment of the present application;

Fig. 38 is a circuit diagram of a status indication module in an embodiment of the present application;

Fig. 39 is a circuit diagram of the debugging button module in one embodiment of the present application;

Fig. 40 is a circuit diagram of a display module in an embodiment of the present application;

Figure 41 is a circuit diagram of an external storage sub-module in an embodiment of the present application;

Fig. 42 is a circuit diagram of an internal storage sub-module in an embodiment of the present application.

detailed description

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

In one embodiment, as shown in FIG. 1 , FIG. 1 is a schematic structural diagram of a pulse diagnosis instrument provided in an embodiment of the present application. The sphygmomanometer includes a host 100 , at least two first measuring components 200 and at least two second measuring components 300 .

Wherein, the first measurement component 200 is used to collect the first sound signal under the pressure of the first target area of the human body, the first target area includes the area of the site to be diagnosed and is larger than the area of the site to be diagnosed. The second measurement component 300 is configured to collect a second sound signal of a second target area of the human body. It should be noted that the first target area can be but not limited to a segment of an arm or leg, the second target area can be but not limited to a heart, chest or a certain point in the abdomen, and the site to be diagnosed can be an arm or leg that can A point where the pulse is measured. Use the first measurement component 200 to collect the sound signal of the first target area. If the area of the first target area is large, the first measurement component 200 can collect signals with a wide range of positions to be measured, which can enhance the accuracy of the measurement results of the pulse diagnosis instrument. In addition to collecting the sound signal of the first target area, the pulse diagnosis instrument of this embodiment also uses the second measurement component 300 to collect the sound signal of the second target area, which can enrich the diversity of sampled data of the pulse diagnosis instrument.

Wherein, the host 100 is configured to obtain a first measurement result according to the first sound signal, and obtain a second measurement result according to the second sound signal. The host 100 of this embodiment can also analyze and display the first measurement result and the second measurement result, specifically, use the data monitoring and health management software contained in the host 100 to process the sound signal, perform signal data analysis, and present the analysis Results and health management recommendations are given.

In one of the embodiments, as shown in FIG. 2 , FIG. 2 is one of the structural block diagrams of a host 100 in an embodiment of the present application, and the host 100 includes a processor 400 , a conversion module 500 , a voltage management module 600 and an air pressure adjustment module 700 , the conversion module 500 , the voltage management module 600 and the air pressure regulation module 700 are all connected to the processor 400 .

Among them, the voltage management module 600 is used to control the voltage rise and fall of the processor 400; the air pressure adjustment module 700 is used to control the first measurement component 200 to pressurize and release the first target area; the conversion module 500 is used to convert the first sound The signal is converted into a first digital signal, and the second sound signal is converted into a second digital signal; the processor 400 is configured to obtain a first measurement result according to the first digital signal, and obtain a second measurement result according to the second digital signal.

In one of the embodiments, as shown in FIG. 3, FIG. 3 is a circuit diagram of a processor 400 in one embodiment of the present application. The processor 400 is provided with chips U10A and U10B whose model is STM32F429VIT6, and an interface CN10, a capacitor C58, and a capacitor C59, capacitor C60, capacitor C61, capacitor C62, capacitor C63, capacitor C64, capacitor C65, capacitor C66, capacitor C67, capacitor C68, capacitor C69, capacitor C70, capacitor C71, capacitor C72, capacitor C94, capacitor C95, capacitor BAT1, Resistor R73, resistor R74, chip resistor LR7, crystal oscillator X1, crystal oscillator X2, Zener diode D4, Zener diode D7 and reset switch SW4.

Specifically, one end of capacitor C71 is connected to pin 73 of chip U10A, the other end of capacitor C71 is grounded, one end of capacitor C72 is connected to pin 49 of chip U10A, the other end of capacitor C71 is grounded, and one end of resistor R73 is connected to pin 70 of chip U10A. One end of resistor R74 is connected to pin 71 of chip U10A, one end of capacitor C94 is connected to one end of crystal oscillator X2, the other end of capacitor C94 is grounded, one end of capacitor C95 is connected to the other end of crystal oscillator X2, and the other end of capacitor C95 Grounding, one end of crystal oscillator X2 is connected to pin 8 of chip U10A, the other end of crystal oscillator X2 is connected to pin 9 of chip U10A, one end of capacitor C58 is connected to one end of crystal oscillator X1, the other end of capacitor C58 is grounded, and one end of capacitor C59 is connected to The other end of crystal oscillator X1 is connected, the other end of capacitor C59 is grounded, one end of crystal oscillator X1 is connected to pin 12 of chip U10A, the other end of crystal oscillator X1 is connected to pin 13 of chip U10A, pin 1 of interface CN10 is connected to 3V power supply, and interface CN10 Pin 2 of the interface CN10 is connected to pin 72 of the chip U10A, pin 3 of the interface CN10 is connected to pin 76 of the chip U10A, pin 3 of the interface CN10 is connected to pin 94 of the chip U10A, pins 5 and 6 of the interface CN10 are grounded, capacitor C67 One end of Zener diode D4 is connected to the negative pole, the other end of capacitor C67 is grounded, the other end of Zener diode D4 is connected to the positive pole of capacitor BAT1, the negative pole of capacitor BAT1 is grounded, the negative pole of Zener diode D7 is connected to the negative pole of Zener diode D4 Negative connection, the positive pole of the Zener diode D7 is connected to the 3V power supply, one end of the capacitor C60 is connected to the positive pole of the Zener diode D7, the other end of the capacitor C60 is grounded, one end of the capacitor C61 is connected to the positive pole of the Zener diode D7, and the other end of the capacitor C61 One end of the capacitor C62 is connected to the positive pole of the Zener diode D7, the other end of the capacitor C62 is grounded, one end of the capacitor C63 is connected to the positive pole of the Zener diode D7, the other end of the capacitor C63 is grounded, and one end of the capacitor C64 is connected to the voltage regulator The positive pole of the diode D7 is connected, the other end of the capacitor C64 is connected to the ground, one end of the capacitor C65 is connected to the positive pole of the Zener diode D7, the other end of the capacitor C65 is grounded, one end of the capacitor C66 is connected to the positive pole of the Zener diode D7, and the other end of the capacitor C66 One end is grounded, pin 6 of the chip U10B is connected to the negative pole of the Zener diode D4, one end of capacitor C69, capacitor C68 and chip resistor LR7 is connected to pin 22 of the chip U10B, the other end of the capacitor C69 and capacitor C68 are grounded, The other end of the chip resistor LR7 is connected to the 3V power supply, the 11 pins, 19 pins, 28 pins, 50 pins, 75 pins and 100 pins of the chip U10B are connected to the 3V power supply, and the 10 pins, 27 pins, 74 pins, 99 pins and 20 pins of the chip U10B are connected to the 3V power supply. Both pins are grounded, one end of capacitor C70 is connected to pin 14 of chip U10A, the other end of capacitor C70 is grounded, the second position of reset switch SW4 is connected to pin 14 of chip U10A, and reset is turned on. The 1st, 3rd, 4th and 5th positions of SW4 are all grounded.

Please refer to Fig. 4, Fig. 4 is the circuit diagram of conversion module 500 in an embodiment of the present application, conversion module 500 is provided with chip U1, electric capacity C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11 , C12, C12, C13, C14, C15, C16, C17, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, chip resistor LR1, chip resistor LR2, chip resistor Chip resistor LR3, variable resistor MIC_R1, variable resistor MIC_R2, test interface JP1, test interface T1, test interface T2, test interface T3, test interface T4, test interface T5 and test interface T6.

Specifically, one end of the capacitor C1, one end of the capacitor C2 and one end of the chip resistor LR1 are all connected to pin 26 of the chip U1, the other end of the capacitor C1 and the other end of the capacitor C2 are grounded, one end of the capacitor C3, and the other end of the capacitor C4 One end and one end of the chip resistor LR2 are connected to pin 31 of the chip U1, the other end of the capacitor C3 and the other end of the capacitor C4 are grounded, the other end of the chip resistor LR2 is connected to the other end of the chip resistor LR1, and the capacitor C8 One end of capacitor C9 and one end of chip resistor LR3 are all connected to pin 14 of chip U1, the other end of capacitor C8 and the other end of capacitor C9 are grounded, pin 13 of chip U1 is connected to pin 14 of chip U1, The 12 pins, 24 pins, 33 pins and 28 pins of the chip are all grounded, the 7 pins of the chip U1 are connected with the 3 pins of the chip U10A, the 8 pins of the chip U1 are connected with the 4 pins of the chip U10A, the 9 pins of the chip U1 are connected with the chip U10A The 2 pins of the chip U1 are connected to the 5 pins of the chip U10A, the 11 pins of the chip U1 are connected to the 1 pin of the chip U10A, the 16 pins of the chip U1 are connected to the 92 pins of the chip U10A, and the 17 pins of the chip U1 are connected to the Connect pin 93 of chip U10A, one end of resistor R5 is connected to pin 16 of chip U1, one end of resistor R6 is connected to pin 17 of chip U1, one end of resistor R7 is connected to pin 18 of chip U1, and the other end of resistor R7 is grounded. One end of resistor R2 is connected to pin 3 of chip U1, the other end of resistor R2 is grounded, one end of resistor R3 is connected to pin 6 of chip U1, the other end of resistor R3 is grounded, and one end of capacitor C5 is connected to pin 1 of chip U1. One end of the resistor R1 and the second position of the variable resistor MIC_R1 are connected to the other end of the capacitor C5, the other end of the resistor R1 is connected to the first position of the variable resistor MIC_R1, and one end of the capacitor C6 is connected to the pin 2 of the chip U1. The other end of the capacitor C6 is connected to the third position of the variable resistor MIC_R1, one end of the capacitor C7 is connected to the pin 4 of the chip U1, one end of the resistor R4 and the second position of the variable resistor MIC_R2 are connected to the other end of the capacitor C7, The other end of the resistor R4 is connected to the first position of the variable resistor MIC_R2, one end of the capacitor C10 is connected to the pin 5 of the chip U1, the other end of the capacitor C10 is connected to the third position of the variable resistor MIC_R2, one end of the capacitor C11 is connected to the chip Connect to pin 19 of U1, one end of capacitor C12 is connected to pin 20 of chip U1, the other end of capacitor C11, the other end of capacitor C12, one end of resistor R12 and pin 2 of test interface JPA are all connected to one end of capacitor C17, the resistor The other end of R12 is connected to pin 29 of chip U10A, the other end of capacitor C17 is grounded, one end of capacitor C15 is connected to pin 32 of chip U1, one end of capacitor C14 is connected to pin 27 of chip U1, the other end of capacitor C15 is connected to the capacitor The other end of C14 is grounded, one end of resistor R8 and one end of resistor R10 are connected to pin 32 of chip U1, resistor R One end of 9 and one end of capacitor C13 are connected to the other end of resistor R8 and test interface T1, the other end of resistor R9 and the other end of capacitor C13 are connected to pin 1 of test interface JP1, and one end of resistor R11 is connected to the terminal of capacitor C16. One end is connected to the other end of the resistor R10 and the test interface T2, the other end of the resistor R11 and the other end of the capacitor C16 are connected to the 1 pin of the test interface JP1, the 3 pin of the test interface JP1 is connected to the 1 pin of the test interface JP1, The test interface T3 is connected to the 32-pin of the chip U1, the test interface T4 is connected to the 26-pin of the chip U1, the test interface T5 is connected to the 31-pin of the chip U1, and the test interface T6 is connected to the 14-pin of the chip U1.

In one embodiment, as shown in FIG. 5, FIG. 5 is a structural block diagram of a voltage management module 600 in an embodiment of the present application. The voltage management module 600 includes a switch module 610, a buck-boost control module 620, a first buck voltage module 630 , second voltage reduction module 640 and first power supply module 650 . Specifically, the switch module 610 , the buck-boost control module 620 , the first buck module 630 , the second buck module 640 and the first power supply module 650 are all connected to the processor 400 . Among them, the power switch module 610 is used to control the power on or off of the host computer 100, the buck-boost control module 620 is used to control the voltage rise and fall of the processor 400, and the first buck module 630 and the second buck module 640 are used to control the voltage of the processor 400. 400 step down, and the first power supply module 650 is used to supply power to the processor 400 .

As shown in Figure 6, Figure 6 is a circuit diagram of the switch module 610 in an embodiment of the present application, the switch module 610 is provided with a chip U6, a resistor R26, a resistor R30, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a resistor R35, resistor R37, resistor R38, resistor R39, resistor R40, capacitor C23, capacitor C24, capacitor C34, capacitor C36, capacitor C37, capacitor C38, capacitor C39, capacitor C40, Zener diode D3, light emitting diode LED3, inductor L4, The test interface T7, the test interface T9, the test interface T10, the test interface T13, the triode Q3 and the reset switch SW3.

Specifically, pin 1 of chip U6 is connected to pin 24 of chip U6, pin 24 of chip U6 and one end of capacitor C36 are connected to 5V voltage, the other end of capacitor C36 and one end of resistor R31 are both grounded, and the other end of resistor R31 is connected to Connect the pin 10 of the chip U6, one end of the resistor R26 is connected to the pin 4 of the chip U6, the negative pole of the test interface T10 and the light-emitting diode LED3 are connected to the other end of the resistor R26, the positive pole of the light-emitting diode LED3 is connected to the system power supply, and one end of the resistor R32 Connect to pin 2 of chip U6, the other end of resistor R32 is connected to pin 3 of chip U6, pin 8 of chip U6 is grounded, pin 5 of chip U6 is connected to pin 47 of chip U10A, pin 6 of chip U6 is connected to pin 47 of chip U10A 48-pin connection, the 7-pin of the chip U6 is connected with the 51-pin of the chip U10A, the 9-pin of the chip U6 is connected with the 52-pin of the chip U10A, one end of the resistor R37 is connected with the 5-pin of the chip U6, one end of the resistor R38 is connected with the chip U6 6-pin connection, one end of the resistor R39 is connected to the 7-pin of the chip U6, the other end of the resistor R37, the other end of the resistor R38, and the other end of the resistor R39 are connected to 3V voltage, one end of the capacitor C23, one end of the capacitor C24 and the test Interface T7 is connected to pin 23 of chip U6, the other end of capacitor C23 and the other end of capacitor C24 are grounded, one end of capacitor C34 is connected to pin 21 of chip U6, the other end of capacitor C34, pin 20 of chip U6 and chip Pin 19 of U6 is connected to one end of inductor L4, the other end of inductor L4, pin 16 of chip U6, pin 15 of chip U6, test interface T9, one end of capacitor C37 and one end of capacitor C38 are connected to the system voltage. The other end of C37, the other end of capacitor C38, one end of capacitor C39, and one end of resistor R35 are all grounded, the other end of resistor R35, pin 22 of chip U6, and one end of resistor R40 are all connected to the test interface T3, and the other end of resistor R40 One end, pin 18 of chip U6, pin 17 of chip U6 and pin 25 of chip U6 are all grounded, the first position of the reset switch is connected to pin 12 of chip U6, the second position of the reset switch is connected to pin 13 of chip U6, Pin 14 of chip U6 is connected to pin 13 of chip U6, one end of Zener diode D3 is connected to pin 12 of chip U6, one end of resistor R33 and capacitor C40 are connected to the other end of Zener diode D3, one end of resistor R34 and The B end of the transistor Q is connected to the other end of the resistor R33, the other end of the capacitor C40, the other end of the resistor R34, and the E end of the transistor Q are all grounded, and the C end of the transistor Q and one end of the resistor R30 are connected to the 77 The pin is connected, and the other end of the resistor R30 is connected to a 3V voltage.

As shown in FIG. 7, FIG. 7 is a circuit diagram of a buck-boost control module 620 in an embodiment of the present application. The buck-boost control module 620 is provided with a chip U4, a chip U5, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C28, Capacitor C29, capacitor C30, capacitor C31, capacitor C32, capacitor C33, capacitor C35, resistor R24, resistor R25, resistor R27, resistor R28, resistor R29, inductor L1, inductor L2, inductor L3, Zener diode D1, Zener diode D2.

Specifically, one end of the capacitor C26, one end of the capacitor C27, one end of the Zener diode D2, one end of the inductor L3 and pin 3 of the chip U5 are connected to the system voltage, the other end of the capacitor C26, the other end of the capacitor C27, the Zener diode The other end of D2, one end of resistor R29, pin 1 of chip U5, pin 5 of chip U5, pin 9 of chip U5, one end of resistor R27, one end of capacitor C29, one end of capacitor C30, one end of capacitor C28, and capacitor C31 One end of the photo U4 pin 2, one end of the capacitor C35, one end of the capacitor C32, one end of the capacitor C33 and one end of the resistor R28 are all grounded, the other end of the resistor R29 is connected to the 2 pin of the chip U5, and the 4 pin of the chip U5 is connected to the The pin 85 of the chip U10A is connected, the pin 8 of the chip U5 and one end of the Zener diode D1 are connected to the other end of the inductor L3, the other end of the Zener diode D1, one end of the resistor R24, the other end of the capacitor C29, and the other end of the capacitor C30 The other end, the other end of capacitor C28, the other end of capacitor C31, pin 4 of chip U4, pin 1 of chip U4 and test interface T8 are all connected to 5V voltage, the other end of resistor R24 and the other end of resistor R27 are connected to chip U5 One end of the inductor L1 is connected to the 3-pin of the chip U4, the other end of the capacitor C36 and one end of the inductor L2 are connected to the other end of the inductor L1, the other end of the inductor L2, the other end of the capacitor C32, and the capacitor C33 The other end, one end of the resistor R25 and one end of the capacitor C25 are all connected to 3V voltage, and the other end of the resistor R25, the other end of the resistor R28 and the other end of the capacitor C25 are connected to pin 5 of the chip U4.

As shown in Figure 8, Figure 8 is a circuit diagram of the first step-down module 630 in an embodiment of the present application, the first step-down module 630 is provided with a chip IC1, a capacitor C42, a capacitor C43, a capacitor C44, a capacitor C46 and a test interface T11 , one end of capacitor C44 and pin 1 of chip IC1 are connected to 5V voltage, pin 3 of chip IC1 is connected to pin 95 of chip U10A, pin 5 of photo IC1, test interface T11, one end of capacitor C43 and one end of capacitor C42 are all connected 3V voltage, the other end of capacitor C44, pin 2 of chip IC1, one end of capacitor C46, the other end of capacitor C43 and the other end of capacitor C42 are all grounded, and the other end of capacitor C46 is connected to pin 4 of chip IC1.

As shown in Figure 9, Figure 9 is a circuit diagram of the second step-down module 640 in an embodiment of the present application, the second step-down module 640 is provided with a chip U7, a resistor R36, a resistor R41, a capacitor C45, a capacitor C41, and a capacitor C47 And chip resistor LR4, one end of chip resistor LR4 is connected to 5V voltage, the other end of chip resistor LR4 and one end of capacitor C45 are connected to pin 8 of chip U7, the other end of capacitor C45, pin 4 of chip U7, chip U7 Pin 9 of the capacitor, one end of the capacitor C48, one end of the resistor R41 and one end of the capacitor C47 are grounded, the other end of the capacitor C48 is connected to the pin 6 of the chip U7, the pin 5 of the chip U7 is connected to the pin 95 of the chip U10A, and the pin of the resistor R36 One end, the other end of resistor R41 and one end of capacitor C41 are all connected to pin 2 of chip U7, and pin 1 of chip U7, the other end of resistor R36, the other end of capacitor C41, test interface T12 and the other end of capacitor C47 are all connected 3V voltage.

As shown in Figure 10, Figure 10 is a circuit diagram of the first power supply module 650 in an embodiment of the present application, the first power supply module 650 is provided with a chip U8, a chip U9, a capacitor C49, a capacitor C50, a capacitor C51, a capacitor C52, and a capacitor C53 , Capacitor C54, Capacitor C55, Capacitor C56, Capacitor C57, Resistor R42, Resistor R43, Resistor R44, Chip Resistor LR5 and grounding test point TP1, one end of Chip Resistor LR5 is connected to 5V voltage, the other end of Chip Resistor LR5, One end of capacitor C51 and one end of capacitor C52 are connected to pin 2 of chip U9, the other end of capacitor C51, the other end of capacitor C52, pin 4 of chip U9, one end of capacitor C56, one end of capacitor C49, and one end of capacitor C50 , one end of capacitor C57, one end of capacitor C54, one end of capacitor C53, one end of capacitor C55, and one end of resistor R44. Pin 4 of chip U8 is grounded, the other end of capacitor C56 is connected to pin 5 of chip U9, pin 6 of chip U9 Pin, the other end of capacitor C49, the other end of capacitor C50 and one end of resistor R43 are all connected to pin 21 of chip U10B, the other end of resistor R43, the other end of resistor R44 and the other end of capacitor C57 are all connected to 3 pins of chip U8 Pin connection, pin 2 of chip U8, pin 6 of chip U8, the other end of capacitor C53 and one end of resistor R42 are connected to pin 27 of chip U1, pin 7 of chip U8 and the other end of capacitor C54 are connected to 5V voltage, The other end of the resistor R42 and the other end of the capacitor C55 are both connected to pin 17 of the chip U10A, and the grounding test point TP1 is grounded.

In one of the embodiments, the sphygmomanometer includes two first measuring components 200 , and the two first measuring components 200 are both connected to the air pressure regulating module 700 .

As shown in Fig. 11, Fig. 11 is a structural block diagram of an air pressure adjustment module 700 in an embodiment of the present application, the air pressure adjustment module 700 includes a second power supply module 710, a first air pressure adjustment sub-module 720 and a second air pressure adjustment sub-module 730, The first air pressure adjustment sub-module 720 is connected to one of the two first measurement assemblies 200 , and the second air pressure adjustment sub-module 730 is connected to the other of the two first measurement assemblies 200 .

Specifically, the second power supply module 710 is used to supply power to the first air pressure adjustment sub-module 720 and the second air pressure adjustment sub-module 730, and the first air pressure adjustment sub-module 720 and the second air pressure adjustment sub-module 730 are used to adjust the corresponding first The air pressure of assembly 200 is measured.

In one of the embodiments, the first air pressure adjustment sub-module 720 includes a first air pressure detection module 721, a first drive module 722, a first air pump module 723, a first air release valve module 724, and a first air release valve fine-tuning module 725; The second air pressure regulation sub-module 730 includes a second air pressure detection module 731 , a second drive module 732 , a second air pump module 733 , a second air release valve module 734 and a second air release valve fine-tuning module 735 . The first air pressure detection module 721 and the second air pressure detection module 731 are used to detect the air pressure of the corresponding first measurement assembly 200, and the first drive module 722 and the second drive module 732 are used to drive the corresponding air pump module, air release valve module and air release valve. The valve fine-tuning module correspondingly controls the first measuring component 200 to carry out air filling, deflation and deflation fine-tuning.

As shown in Figure 12, Figure 12 is a circuit diagram of the second power supply module 710 in an embodiment of the present application, the second power supply module 710 is provided with a chip U12, an interface Q7, a capacitor C84, a capacitor C85, a capacitor C86, a capacitor C87, and a capacitor C88 , capacitor C89, resistor C68, resistor C69, resistor C70, resistor C71, Zener diode D5, Zener diode D6, triode Q8, test interface T23 and test interface T24, one end of capacitor C88, one end of capacitor C89, and interface Q7 Pin 8, pin 7 of interface Q7, pin 6 of interface Q7, pin 5 of interface Q7 and one end of resistor R69 are all connected to 5V voltage, the other end of capacitor C88, the other end of capacitor C89, E end of triode, Zener diode The positive pole of D5, one end of capacitor C85, one end of capacitor C86, one end of capacitor C87, pin 9 of chip U12, pin 3 of chip U12, positive pole of Zener diode D6, one end of resistor R70 and one end of capacitor C84 are all grounded. The other end of the resistor R69 and the C end of the triode are connected to the pin 4 of the interface Q7, one end of the resistor R71 is connected to the pin 98 of the chip U10A, the other end of the resistor R71 is connected to the B end of the triode Q8, and the negative pole of the Zener diode , pin 1 of interface Q7, pin 2 of interface Q7, pin 3 of interface Q7, the other end of capacitor C85, the other end of capacitor C86, the other end of capacitor C87 and pin 8 of chip U12 are all connected to the test interface T23, test Interface T23 is connected to 5V voltage, pin 5 of chip U12 is connected to pin 97 of chip U10A, pin 2 of chip U12 and the other end of resistor R70 are connected to one end of resistor R68, pin 1 of chip U12 is connected to the negative pole of Zener diode D6 1. The other end of the resistor R68 and the other end of the capacitor C84 are both connected to the test interface T24, and the test interface T24 is connected to 3V voltage.

As shown in Figure 13, Figure 13 is a circuit diagram of the first air pressure detection module 721 in an embodiment of the present application, the first air pressure detection module 721 is provided with a chip U13, a capacitor C90 and a capacitor C91, the 3 pins of the chip U13 are grounded, and the chip U13 Pin 2 of the chip U13 is connected to the test interface T12, pin 4 of the chip U13 is connected to 3V voltage with one end of the capacitor C90, pin 6 of the chip U13, the other end of the capacitor C90 and one end of the capacitor C91 are all grounded, and the other end of the capacitor C91 is connected to the chip U13 The 5-pin connection.

As shown in Figure 14, Figure 14 is a circuit diagram of the first drive module 722 in an embodiment of the present application, the first drive module 722 is provided with an interface Q9, and pins 1, 2 and 3 of the interface Q9 are all connected to 67 pins of the chip U10A. Pin connection, pin 4 and pin 5 of interface Q9 are connected to pin 43 of chip U10A, pin 6 and pin 7 of interface Q9 are connected to pin 44 of chip U10A, pin 8 of interface Q9 is grounded, pin 9 of interface Q9 is connected to pin 44 of chip U10A Test interface T23 connection.

As shown in Figure 15, Figure 15 is a circuit diagram of the first air pump module 723 in an embodiment of the present application, the first air pump module 723 is provided with an interface CN3, the 3 pins and 4 pins of the interface CN3 are grounded, and the 14 pins and 15 pins of the interface Q9 are grounded. Both pin and pin 16 are connected to pin 1 of the interface CN3, and pin 2 of the interface CN3 is connected to the test interface T24.

As shown in Figure 16, Figure 16 is a circuit diagram of the first air release valve module 724 in an embodiment of the present application, the first air release valve module 724 is provided with an interface CN4, pins 3 and 4 of the interface CN4 are grounded, and pin 12 of the interface Q9 Both pins 1 and 13 are connected to pin 1 of the interface CN4, and pin 2 of the interface CN4 is connected to the test interface T23.

As shown in Figure 17, Figure 17 is a circuit diagram of the first air release valve fine-tuning module 725 in an embodiment of the present application, the first air release valve fine-tuning module 725 is provided with an interface CN5, the 3 pins and 4 pins of the interface CN5 are grounded, and the interface Q9 Both pins 10 and 11 are connected to pin 1 of the interface CN5, and pin 2 of the interface CN5 is connected to the test interface T23.

As shown in Figure 18, Figure 18 is a circuit diagram of the second air pressure detection module 731 in an embodiment of the present application, the second air pressure detection module 731 is provided with a chip U14, a capacitor C92 and a capacitor C93, the pin 3 of the chip U14 is grounded, and the chip U14 Pin 2 of the chip U14 is connected to the test interface T12, pin 4 of the chip U14 and one end of the capacitor C92 are connected to 3V voltage, pin 6 of the chip U14, the other end of the capacitor C92 and one end of the capacitor C93 are all grounded, and the other end of the capacitor C93 is connected to the chip U14 The 5-pin connection.

As shown in Figure 19, Figure 19 is a circuit diagram of the second drive module 732 in one embodiment of the present application, the second drive module 732 is provided with an interface Q10, and pins 1, 2 and 3 of the interface Q10 are all connected to 66 pins of the chip U10A. Pin connection, pin 4 and pin 5 of interface Q10 are connected to pin 45 of chip U10A, pin 6 and pin 7 of interface Q10 are connected to pin 46 of chip U10A, pin 8 of interface Q10 is grounded, pin 9 of interface Q10 is connected to pin 46 of chip U10A Test interface T23 connection.

As shown in Figure 20, Figure 20 is a circuit diagram of the second air pump module 733 in an embodiment of the present application, the second air pump module 733 is provided with an interface CN6, the 3 pins and 4 pins of the interface CN6 are grounded, and the 14 pins and 15 pins of the interface Q10 are grounded. Both pin and pin 16 are connected to pin 1 of the interface CN6, and pin 2 of the interface CN6 is connected to the test interface T24.

As shown in Figure 21, Figure 21 is a circuit diagram of the second air release valve module 734 in an embodiment of the present application, the second air release valve module 734 is provided with an interface CN7, pins 3 and 4 of the interface CN7 are grounded, and pin 12 of the interface Q10 Both pins 1 and 13 are connected to pin 1 of the interface CN7, and pin 2 of the interface CN7 is connected to the test interface T23.

As shown in Figure 22, Figure 22 is a circuit diagram of the second air release valve fine-tuning module 735 in an embodiment of the present application, the second air release valve fine-tuning module 735 is provided with an interface CN8, the pin 3 and pin 4 of the interface CN8 are grounded, and the pin 4 of the interface Q10 is grounded. Both pins 10 and 11 are connected to pin 1 of the interface CN8, and pin 2 of the interface CN8 is connected to the test interface T23.

In one of the embodiments, the host 100 further includes a power supply detection module 800 and a voltage acquisition module 900 , both of which are connected to the processor 400 . Specifically, the power supply detection module 800 is used to detect the power supply of the entire host 100 , and the voltage collection module 900 is used to collect the voltages of the modules included in the entire host 100 .

As shown in Figure 23, Figure 23 is a frame diagram of a power supply detection module 800 in an embodiment of the present application, the power supply detection module 800 includes a first detection sub-module 810, a second detection sub-module 820, a third detection sub-module 830, a Four detection sub-module 840 , fifth detection sub-module 850 , sixth detection sub-module 860 and seventh detection sub-module 870 .

As shown in Figure 24, Figure 24 is a circuit diagram of the first detection sub-module 810 in an embodiment of the present application, the first detection sub-module 810 is provided with a resistor R48, a resistor R51, a capacitor C76 and a test interface T15, a test interface T15, a capacitor One end of C76, one end of resistor R48 and one end of resistor R51 are all connected to pin 35 of chip U10A, the other end of capacitor C76 and the other end of resistor R51 are all grounded, and the other end of resistor R48 is connected to the anode of light-emitting diode LED3.

As shown in Figure 25, Figure 25 is a circuit diagram of the second detection sub-module 820 in one embodiment of the present application, the second detection sub-module 820 is provided with a resistor R49, a resistor R52, a capacitor C77 and a test interface T16, the test interface T16, a capacitor One end of C77, one end of resistor R49 and one end of resistor R52 are all connected to pin 30 of chip U10A, the other end of capacitor C77 and the other end of resistor R52 are grounded, and the other end of resistor R49 is connected to test interface T12.

As shown in Figure 26, Figure 26 is a circuit diagram of the third detection sub-module 830 in an embodiment of the present application, the third detection sub-module 830 is provided with a resistor R59, a resistor R63, a capacitor C79 and a test interface T18, a test interface T18, a capacitor One end of C79, one end of resistor R63 and one end of resistor R59 are all connected to pin 33 of chip U10A, and the other end of capacitor C79 and the other end of resistor R63 are grounded.

As shown in Figure 27, Figure 27 is a circuit diagram of the fourth detection sub-module 840 in an embodiment of the present application, the fourth detection sub-module 840 is provided with a resistor R60, a resistor R64, a capacitor C80 and a test interface T19, a test interface T19, a capacitor One end of C80, one end of resistor R60 and one end of resistor R64 are all connected to pin 32 of chip U10A, the other end of capacitor C80 and the other end of resistor R64 are grounded, and the other end of resistor R60 is connected to the ungrounded end of capacitor C33.

As shown in Figure 28, Figure 28 is a circuit diagram of the fifth detection sub-module 850 in an embodiment of the present application, the fifth detection sub-module 850 is provided with a resistor R58, a resistor R67, a capacitor C81 and a test interface T20, a test interface T20, a capacitor One end of C81, one end of resistor R58 and one end of resistor R67 are all connected to pin 34 of chip U10A, the other end of capacitor C81 and the other end of resistor R67 are grounded, and the other end of resistor R58 is connected to test interface T8.

As shown in Figure 29, Figure 29 is a circuit diagram of the sixth detection sub-module 860 in one embodiment of the present application, the sixth detection sub-module 860 is provided with a resistor R61, a resistor R65, a capacitor C82 and a test interface T21, a test interface T21, a capacitor One end of C82, one end of resistor R61 and one end of resistor R65 are all connected to pin 31 of chip U10A, the other end of capacitor C82 and the other end of resistor R65 are grounded, and the other end of resistor R61 is connected to test interface T11.

As shown in Figure 30, Figure 30 is a circuit diagram of the seventh detection sub-module 870 in an embodiment of the present application, the seventh detection sub-module 870 is provided with a resistor R62, a resistor R66, a capacitor C83 and a test interface T22, a test interface T22, a capacitor One end of C83, one end of resistor R62 and one end of resistor R66 are all connected to pin 36 of chip U10A, the other end of capacitor C83 and the other end of resistor R66 are grounded, and the other end of resistor R62 is connected to test interface T24.

As shown in Figure 31, Figure 31 is a circuit diagram of the voltage acquisition module 900 in an embodiment of the present application. The voltage acquisition module 900 is provided with a resistor R50, a resistor R53, a resistor R54, a resistor R55, a resistor R56, a resistor R57, a capacitor C78, and a transistor Q5, transistor Q6 and test interface T17, one end of capacitor C78, one end of resistor R54, one end of resistor R57 and test interface T17 are all connected to pin 18 of chip U10A, the other end of capacitor C78, the other end of resistor R57, transistor Q6 The E end of the resistor R56 and one end of the resistor R56 are both grounded, the other end of the resistor R54 is connected to the C end of the transistor Q5, one end of the resistor R50 and one end of the resistor R53 are connected to the B end of the transistor Q5, and the other end of the resistor R53 is connected to the transistor Q6 The other end of the resistor R56 and one end of the resistor R55 are connected to the B end of the transistor Q6, the other end of the resistor R55 is connected to the 86 pin of the chip U10A, the E end of the transistor Q5 and the other end of the resistor are connected to the chip The 13-pin connection of U6.

In one embodiment, as shown in FIG. 32 , which is one of the structural block diagrams of the host 100 in an embodiment of the present application, the host 100 also includes a USB-TYPE module 1000 , an external switch module 1100 , and a battery interface module 1400 , extension indicator module 1300, status indicator module 1500, debugging button module 1600, display module 1200, storage module 1800 and Bluetooth module 1700, USB-TYPE module 1000, external switch module 1100, battery interface module 1400, extension indicator module 1300, The status indication module 1500 , the debugging button module 1600 , the display module 1200 , the storage module 1800 and the Bluetooth module 1700 are all connected to the processor 400 , and the second measurement component 300 is connected to the USB-TYPE module 1000 .

Specifically, the Bluetooth module 1700 is used for information transmission between the host 100 and external devices. The USB-TYPE module 1000 uses the USB2.0 protocol for data transmission, charging and connection with the second measurement component 300, an external switch module 1100, a battery interface module 1400, an expansion indicator module 1300, a status indicator module 1500, and a debugging button Module 1600, display module 1200, and storage module 1800 have the same functions as their names, and will not be repeated here.

As shown in Figure 33, Figure 33 is a circuit diagram of the Bluetooth module 1700 in an embodiment of the present application, the Bluetooth module 1700 is provided with a chip U11, a resistor R45, a resistor R46, a resistor R47, a capacitor C73, a capacitor C74, a capacitor C75, a transistor Q4, Test interface T14, interface JP2 and light-emitting diode LED4.

Specifically, one end of the capacitor C73, one end of the resistor R46, and the E end of the triode are all connected to a voltage of 3V, the other end of the resistor R46 and one end of the resistor R47 are connected to the B end of the transistor Q4, and the other end of the resistor R47 is connected to the chip U10A The C terminal of the transistor Q4, one end of the capacitor C74, one end of the capacitor C75 and the test interface T14 are all connected to the 12 pin of the chip U11, the other end of the capacitor C73, the other end of the capacitor C74 and the other end of the capacitor C75 Both are grounded, pin 2 of interface JP2 is connected to pin 36 of chip U11, pin 3, pin 1 and pin 13 of interface JO2 are connected to pin 35 of chip U11, one end of resistor R45 is connected to pin 32 of chip U11, resistor R45 The other end of the LED is connected to the positive pole of the light-emitting diode LED4, the negative pole of the light-emitting diode LED4 is grounded, the 21 pins and 22 pins of the chip U11 are both grounded, the 1 pin of the chip U11 is connected to the 26 pin of the chip U10A, the 1 pin of the chip U11 is connected to the chip U10A The 26-pin connection of the chip U11 is connected with the 25-pin of the chip U10A, the 3-pin of the chip U11 is connected with the 24-pin of the chip U10A, the 4-pin of the chip U11 is connected with the 23-pin of the chip U10A, and the 9-pin of the chip U11 is connected with the Pin 84 of the chip U10A is connected, pin 10 of the chip U11 is connected to pin 83 of the chip U10A, pin 11 of the chip U11 is connected to pin 82 of the chip U10A.

As shown in Figure 34, Figure 34 is a circuit diagram of the USB-TYPE module 1000 in an embodiment of the present application, the USB-TYPE module 1000 is provided with an interface USB1, a resistor R15 and a resistor R16, and one end of the resistor R15 is connected to the A5 pin of the interface USB1 , one end of the resistor R16 is connected to the B5 pin of the interface USB1, the other end of the resistor R16, the other end of the resistor R16, the B1A12 pin of the interface USB1, the 1 pin of the interface USB1, the 2 pin of the interface USB1, the 3 pin of the interface USB1 and the interface USB1 The 4 pins of the interface USB1 are connected to the ground, the A4B9 pin of the interface USB1 and the B 4A9 pin of the interface USB1 are connected to the other end of the resistor R59, the A6 pin of the interface USB1 is connected to the 71 pin of the chip U10A, the A7 pin of the interface USB1 is connected to the 70 pin of the chip U10A Pin connection, the B6 pin of the interface USB1 is connected with the 71 pin of the chip U10A, and the B7 pin of the interface USB1 is connected with the 71 pin of the chip U10A.

As shown in Figure 35, Figure 35 is a circuit diagram of an external switch module 1100 in an embodiment of the present application. The external switch module 1100 is provided with an interface CN1, pin 1 of the interface CN1 is connected to pin 13 of the chip U6, and pin 2 of the interface CN1 The pin is connected to the 12 pin of the chip U6, and the 3 pin of the interface CN1 and the 4 pin of the interface CN1 are both grounded.

As shown in Figure 36, Figure 36 is a circuit diagram of the battery interface module 1400 in an embodiment of the present application. The battery interface module 1400 is provided with an interface CN2, pin 1 of the interface CN2 is connected to pin 13 of the chip U6, pin 2 of the interface CN2 is connected to the The 11-pin of the chip U6 is connected, and the 3-pin of the interface CN2 is grounded.

As shown in Figure 37, Figure 37 is a circuit diagram of the extended indicator module 1300 in an embodiment of the present application. The extended indicator module 1300 is provided with an interface FPC1, and pins 1, 7, and 8 of the interface FPC1 are all grounded, and pin 2 of the interface FPC1 is grounded. Connect with pin 64 of chip U10A, pin 3 of interface FPC1 connect with pin 63 of chip U10A, pin 4 of interface FPC1 connect with pin 69 of chip U10A, pin 5 of interface FPC1 connect with pin 68 of chip U10A.

As shown in FIG. 38, FIG. 38 is a circuit diagram of a status indicating module 1500 in an embodiment of the present application. The status indicating module 1500 is provided with a resistor R13, a resistor R14, a resistor R72, a light emitting diode B, a light emitting diode G and a light emitting diode R, and the resistor One end of R13 is connected to the negative pole of LED B, the other end of resistor R13 is connected to pin 65 of chip U10A, one end of resistor R14 is connected to the negative pole of light emitting diode G, and the other end of resistor R14 is connected to pin 68 of chip U10A. One end of R72 is connected to the negative pole of the LED R, the other end of the resistor R13 is connected to the pin 69 of the chip U10A, the positive poles of the LED B, the positive poles of the LED G and the positive poles of the LED R are all connected to the pin 6 of the interface FPC1.

As shown in Figure 39, Figure 39 is a circuit diagram of the debug button module 1600 in an embodiment of the present application, the debug button module 1600 is provided with a debug button SW1 and a debug button SW2, and the second position of the debug button SW1 is connected to pin 63 of the chip U10A , the first position, the third position, the fourth position and the fifth position of the debugging button SW1 are all grounded, the second position of the debugging button SW2 is connected to the 64 pin of the chip U10A, the first position, the third position, Both 4th and 5th positions are grounded.

As shown in Figure 40, Figure 40 is a circuit diagram of a display module 1200 in an embodiment of the present application. The display module 1200 is provided with an interface Q1, an interface CN9 whose model is HY2.0-8P, a resistor R17, a resistor R18, a capacitor C18, and a capacitor C19, capacitor C20 and transistor Q2, one end of capacitor C19, one end of capacitor C20, one end of resistor R17, pin 5 of interface QI, pin 6 of interface QI, pin 7 of interface QI and pin 8 of interface QI are all connected to the test interface T8 connection, the other end of the capacitor C19, the other end of the capacitor C20, the E end of the transistor Q2, one end of the capacitor C18, the 7 pin of the interface CN9 and the 8 pin of the interface CN9 are all grounded, the 4 pin of the interface Q1 and the other end of the resistor R17 One end is connected to the C terminal of the transistor Q2, one end of the resistor R18 is connected to the B terminal of the transistor Q2, the 1 pin of the interface Q1, the 2 pin of the interface Q1, the 3 pin of the interface Q1, the 1 pin of the interface CN9 and the 2 pin of the interface CN9 Both pins are connected to the other end of the capacitor C18, pin 4 of the interface CN9 is connected to pin 56 of the chip U10A, pins 5 and 6 of the interface CN9 are connected to pin 57 of the chip U10A.

Specifically, the storage module 1800 is provided with an external storage sub-module and an internal storage sub-module, and both the external storage sub-module and the internal storage sub-module are connected to the processor 400 . Both the external storage sub-module and the internal storage sub-module are used for storing data information.

As shown in Figure 41, Figure 41 is a circuit diagram of an external storage sub-module in an embodiment of the present application, the external storage sub-module is provided with a chip U3, a resistor R19, a resistor R20, a resistor R21, a resistor R22 and a resistor R23, and one end of the resistor R19 , one end of resistor R20, one end of resistor R21, one end of resistor R22, one end of resistor R23 and pin 8 of chip U3 are all connected to VDD 3V3, the other end of resistor R19 is connected to pin 1 of chip U3, and the other end of resistor R20 is connected to pin 1 of chip U3. The other end of resistor R21 is connected to pin 7 of chip U3, the other end of resistor R22 is connected to pin 6 of chip U3, the other end of resistor R23 is connected to pin 5 of chip U3, and the other end of resistor R23 is connected to pin 5 of chip U3. Pin 1 is connected to pin 89 of chip U10A, pin 2 of chip U3 is connected to pin 90 of chip U10A, pin 7 of chip U3 is connected to pin 54 of chip U10A, pin 6 of chip U3 is connected to pin 54 of chip U10A The 53 pins of the chip U3 are connected to the 53 pins of the chip U3 and the 82 pins of the chip U10A.

As shown in Figure 42, Figure 42 is a circuit diagram of the internal storage sub-module in an embodiment of the present application, the internal storage sub-module is provided with a chip U2 and a capacitor C21, one end of the capacitor C21 and 8 pins of the chip U2 are connected to VDD 3V3, and the capacitor The other end of C21 and pin 4 of chip U2 are grounded, pin 1 of chip U2 is connected to pin 79 of chip U10A, pin 2 of chip U2 is connected to pin 39 of chip U10A, pin 3 of chip U2 is connected to pin 40 of chip U10A Connection, the 5 pins of the chip U2 are connected with the 38 pins of the chip U10A, the 6 pins of the chip U2 are connected with the 37 pins of the chip U10A, and the 7 pins of the chip U2 are connected with the 41 pins of the chip U10A.

In this application, the parameters of the processor 400 included in the host computer 100 and the electronic components contained in the circuits of all modules are marked in the drawings, which are the corresponding parameters in the drawings, and the parameters of the unmarked electronic components can be determined by those skilled in the art. Set it according to the actual situation. It should also be noted that those skilled in the art can specifically adjust the parameters of the marked electronic components in the drawings according to the actual situation, and the parameters of the electronic components in this application are not limited to the parameters shown in the drawings.

In one embodiment, the first measuring component 200 is a pressure band with a length of 3 cm to 15 cm, and the second measuring component 300 is a stethoscope. Using a pressure band with a length of 3cm to 15cm to measure the sound signal of the first target area can improve the detection stability and accuracy. Using a stethoscope to collect the sound signal of a certain point in the heart or chest, that is, the second target area can enrich the detection results. diversity.

The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered to be within the range described in this specification.

The above-mentioned embodiments only express several implementation modes of the present application, and the description thereof is relatively specific and detailed, but should not be construed as limiting the patent scope of the present application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be determined by the appended claims.

Claims (10)

1. A pulse diagnosis instrument, characterized in that, the pulse diagnosis instrument comprises a host, at least two first measurement assemblies and at least two second measurement assemblies; The first measurement component is used to collect the first sound signal under the pressure of the first target area of the human body, the first target area includes the area of the site to be diagnosed and is larger than the area of the site to be diagnosed; The second measurement component is configured to collect a second sound signal of a second target area of the human body; The host is configured to obtain a first measurement result according to the first sound signal, and obtain a second measurement result according to the second sound signal. 2. The pulse diagnosis instrument according to claim 1, characterized in that: the host computer includes a processor, a conversion module, a voltage management module and an air pressure adjustment module, and the conversion module, the voltage management module and the air pressure adjustment module The modules are all connected to the processor; The voltage management module is used to control the voltage rise and fall of the processor; The air pressure adjustment module is used to control the first measurement component to pressurize and release the first target area; The converting module is configured to convert the first sound signal into a first digital signal, and convert the second sound signal into a second digital signal; The processor is configured to obtain the first measurement result according to the first digital signal, and obtain the second measurement result according to the second digital signal. 3. The pulse diagnosis instrument according to claim 2, wherein the voltage management module comprises a switch module, a step-down control module, a first step-down module, a second step-down module and a first power supply module; The switch module, the step-down control module, the first step-down module, the second step-down module and the first power supply module are all connected to the processor. 4. The pulse diagnosis instrument according to claim 3, characterized in that, the pulse diagnosis instrument comprises two first measuring assemblies, both of which are connected to the air pressure regulating module. 5. The pulse diagnosis instrument according to claim 4, wherein the air pressure adjustment module comprises a second power supply module, a first air pressure adjustment sub-module and a second air pressure adjustment sub-module, and the first air pressure adjustment sub-module It is connected with one of the two first measurement components, and the second air pressure adjustment sub-module is connected with the other of the two first measurement components. 6. The pulse diagnosis instrument according to claim 5, wherein the first air pressure regulation sub-module includes a first air pressure detection module, a first drive module, a first air pump module, a first air release valve module and a first air pressure module. Leakage valve fine-tuning module; The second air pressure regulation sub-module includes a second air pressure detection module, a second drive module, a second air pump module, a second air release valve module, and a second air release valve trimming module. 7. The pulse diagnosis instrument according to claim 6, wherein the host computer further comprises a power supply detection module and a voltage acquisition module, both of which are connected to the processor. 8. The pulse diagnosis instrument according to claim 7, wherein the power supply detection module comprises a first detection sub-module, a second detection sub-module, a third detection sub-module, a fourth detection sub-module, a fifth detection sub-module submodule, the sixth detection submodule and the seventh detection submodule. 9. The pulse diagnosis instrument according to claim 8, wherein the host computer also includes a USB-TYPE module, an external switch module, a battery interface module, an expansion indicator module, a status indicator module, a debugging button module, and a display module , a storage module and a Bluetooth module, the USB-TYPE module, the external switch module, the battery interface module, the expansion indicator module, the status indicator module, the debugging button module, the display module, Both the storage module and the Bluetooth module are connected to the processor; The second measurement component is connected with the USB-TYPE module. 10. The pulse diagnosis instrument according to any one of claims 1-9, characterized in that, the first measuring component comprises a pressure belt, and the length of the pressure belt is 3cm-15cm; The second measurement assembly includes a stethoscope.

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