CN115472698A - LDMOS device structure - Google Patents

Abstract

The present invention provides an LDMOS device structure, including a semiconductor layer, a source region, a drain region, a gate dielectric layer, a gate layer, a silicide barrier layer and a split contact field plate, wherein the gate dielectric layer is located on the semiconductor layer and It is arranged between the source and drain regions; the gate layer is located on the gate dielectric layer and extends to the upper surface of the gate dielectric layer in the direction towards the drain region; the split contact field plate is located on the silicide barrier layer and extends in the horizontal direction The upper layer is disposed between the gate layer and the drain region, and includes at least two field plate strips arranged at intervals along the channel direction. The invention splits the large-sized bulk contact field plate into multiple small-sized contact field plates along the length direction of the channel, which not only can realize the electrical performance basically the same as that of conventional devices, but also can achieve a considerable withstand voltage performance. A straighter shape is achieved in the etching process, and the critical dimension is easy to achieve the target value, and the metal filling is easier without affecting the lithographic alignment of the first layer of metal in the subsequent process.

Description

A LDMOS device structure

technical field

The invention belongs to the technical field of semiconductor power devices and relates to an LDMOS device structure.

Background technique

Contact Field Plate (CFP) technology is a very competitive field plate technology, widely used in the electric field optimization of Lateral Diffused Metal Oxide Semiconductor (LDMOS) devices, by increasing the contact field plate, and connect the contact field plate to the source terminal, so that the voltage difference between the drain terminal and the contact field plate will make the electric field under the contact field plate evenly distributed, and reduce the specific on-resistance of the device without changing the The peak electric field on the surface of the device improves the withstand voltage (BV) performance of the device. At the same time, contacting the field plate can improve the hot carrier injection effect (HCI) of the device and simplify the fabrication process.

LDMOS with different voltages often require contact field plates of different sizes. To a certain extent, as the withstand voltage increases, the size of the contact field plate becomes larger. The production process of large-size contact field plates is very difficult, such as etching load effects, The critical dimensions at the bottom are not easy to achieve, the critical dimensions at the top are too large, and a thicker metal filling thickness is required, which leads to problems such as inability to align the first layer of metal lithography in the subsequent process.

Therefore, how to improve the large-sized contact field plate to meet the requirements of the manufacturing process has become an important technical problem to be solved urgently by those skilled in the art.

It should be noted that the above introduction to the technical background is only for the convenience of a clear and complete description of the technical solution of the present application, and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are known to those skilled in the art just because these solutions are described in the background technology section of this application.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an LDMOS device structure, which is used to solve the problem that the contact field plate process of the existing LDMOS device is easy to cause etching morphology defects, excessive metal filling, and influence on subsequent processes. One-layer metal alignment and other issues.

In order to achieve the above purpose and other related purposes, the present invention provides an LDMOS device structure, including:

semiconductor layer;

a source region and a drain region, located in the semiconductor layer and arranged at intervals in the horizontal direction;

a gate dielectric layer located on the semiconductor layer and disposed between the source region and the drain region;

a gate layer located on the gate dielectric layer, the distance between the gate layer and the source region is smaller than the distance between the gate layer and the drain region;

a silicide barrier layer covering a part of the upper surface of the gate layer and extending to the upper surface of the gate dielectric layer in a direction toward the drain region;

a split contact field plate located on the silicide barrier layer and arranged between the gate layer and the drain region in the horizontal direction, the split contact field plate comprising: of at least two field slats.

Optionally, the semiconductor layer includes a substrate layer of the first conductivity type and a doped layer of the second conductivity type arranged in sequence from bottom to top, and includes a body of the first conductivity type located in the doped layer of the second conductivity type. region, the source region is located in the body region and is spaced a predetermined distance from the sidewall of the body region, and at least a part of the gate layer is located above the body region.

Optionally, the second conductivity type doped layer includes a first concentration doped layer and a second concentration doped layer sequentially arranged from bottom to top, and the doping concentration of the first concentration doped layer is lower than the The doping concentration of the doping layer of the second concentration, the body region penetrates the doping layer of the second concentration and extends downward into the doping layer of the first concentration.

Optionally, the width of the field plate strips ranges from 0.1 micron to 0.5 micron.

Optionally, the plurality of field slabs have the same width.

Optionally, at least two of said field slabs have different widths.

Optionally, the split contact field plate includes at least three field plate strips arranged at intervals along the channel direction, and the distance between any two adjacent field plate strips is the same.

Optionally, the split contact field plate includes at least three field plate strips arranged at intervals along the channel direction, and the distance between at least one pair of adjacent two field plate strips is the same as that of another pair of adjacent two field plate strips. The distance between the field slats varies.

Optionally, the LDMOS device structure further includes a source contact portion and a drain contact portion, the bottom end of the source contact portion is in contact with the source region, and the bottom end of the drain contact portion is in contact with the In contact with the drain region, at least one of the field plate strips has the same width as the source contact portion, or at least one of the field plate strips has the same width as the drain contact portion.

Optionally, the slope of the sidewall of the field slab is less than 5°.

As mentioned above, the LDMOS device structure of the present invention splits the large-sized bulk contact field plate into multiple small-sized contact field plates along the length direction of the device channel, and the multiple small-sized contact field plates form a split contact field plate, compared with the LDMOS device based on the large-size bulk contact field plate, the LDMOS device based on the split contact field plate structure of the present invention can not only achieve basically the same electrical performance, achieve a considerable withstand voltage performance, but also can be used in etching A straighter shape is achieved in the process, and the critical dimensions are easy to achieve the target value. At the same time, metal filling is easier and does not affect the photolithographic alignment of the first layer of metal in the subsequent process.

Description of drawings

FIG. 1 shows a schematic cross-sectional structure of an LDMOS device structure based on a bulk contact field plate.

FIG. 2 shows a partial layout diagram of the structure shown in FIG. 1 .

FIG. 3 is a schematic cross-sectional structure diagram of the LDMOS device structure of the present invention.

FIG. 4 shows a layout diagram of the LDMOS device structure of the present invention.

FIG. 5 shows the current density distribution diagram of the LDMOS device structure based on the large-scale bulk contact field plate shown in FIG. 1 and FIG. 2 under withstand voltage.

FIG. 6 is a graph showing the current density distribution of the LDMOS device structure based on the split contact field plate structure under withstand voltage according to the present invention.

FIG. 7 shows the withstand voltage curves of the LDMOS device structure based on the split contact field plate structure of the present invention and the conventional LDMOS device structure based on the large-sized bulk contact field plate.

Component designation description

101 P-type substrate layer

102 deep N well layer

103 N-type drift layer

104 P-type body region

105 source region

106 Drain region

107 gate dielectric layer

108 gate layer

109 side wall

110 silicide barrier layer

111 block contact field plate

112 contact part

201 semiconductor layer

201a First conductive type substrate layer

201b first concentration doped layer

201c second concentration doped layer

202 source region

203 Drain area

204 gate dielectric layer

205 gate layer

206 Silicide barrier layer

207 split contact field plate

207a First slats

207b second field slats

207c Third Field Slats

208 body area

209 Source contact

210 Drain contact

211 side wall

detailed description

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 through 7. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

Please refer to Figure 1 and Figure 2, wherein Figure 1 shows a schematic cross-sectional structure of an LDMOS device structure based on a bulk contact field plate (Bulk CFP), and Figure 2 shows a partial layout of the structure shown in Figure 1, The structure includes a P-type substrate layer 101, a deep N well layer 102, an N-type drift layer 103, a P-type body region 104, a source region 105, a drain region 106, a gate dielectric layer 107, a gate layer 108, and sidewalls 109. , the silicide barrier layer 110, the bulk contact field plate 111 and the contact portion 112. In this structure, due to the large size of the bulk contact field plate 111 (the width is 0.99 microns), a series of problems will be brought: (1 ) produces an etching load effect, resulting in a decrease in the etching rate or uneven distribution; (2) the sidewall slope of the field plate etching hole is large, and the key dimensions at the bottom are not easy to achieve; (3) due to the field plate etching hole The critical dimension of the top is too large. When filling metal (such as tungsten), if you want to fill the field plate etching hole, you need to increase the deposition thickness, but this will also make the first layer of metal (M1) in the back end (BEOL) The alignment mark pattern during photolithography is also filled, which leads to a weak alignment signal of the first layer of metal photolithography, resulting in alignment failure.

In terms of the structural design of the LDMOS device, the present invention splits the large-sized contact field plate into a plurality of long and narrow contact field slabs along the direction of the device channel, and the combination of the plurality of long and narrow contact field slabs can realize the integration with the original contact field plate Consistent electrical properties, and easier hole etching and metal filling during the preparation process, can effectively solve the problems of CFP etching morphology, metal filling thickness and photolithography alignment of M1 metal. The technical solutions of the present invention are illustrated below through specific examples.

Please refer to FIG. 3 and FIG. 4 , wherein FIG. 3 is a schematic cross-sectional structure diagram of the LDMOS device structure of the present invention, and FIG. 4 is a layout diagram of the LDMOS device structure of the present invention.

Specifically, the LDMOS device structure of the present invention includes a semiconductor layer 201, a source region 202, a drain region 203, a gate dielectric layer 204, a gate layer 205, a silicide barrier layer 206, and a split contact field plate 207, wherein the The source region 202 and the drain region 203 are located in the semiconductor layer 201 and arranged at intervals in the horizontal direction, and the gate dielectric layer 204 is located on the semiconductor layer 201 and arranged between the source region 202 and the Between the drain regions 203; the gate layer 205 is located on the gate dielectric layer 204, and the distance between the gate layer 205 and the source region 202 is smaller than that between the gate layer 205 and the gate layer 205. The distance between the drain regions 203; the silicide barrier layer 206 covers a part of the upper surface of the gate layer 205, and extends to the gate dielectric layer 204 along the direction toward the drain region 203 the upper surface of the upper surface; the split contact field plate 207 is located on the silicide barrier layer 206, and is arranged between the gate layer 205 and the drain region 203 in the horizontal direction, and the split contact The field plate 207 includes at least two field plate strips arranged at intervals along the channel direction.

As an example, the semiconductor layer 201 includes a substrate layer 201a of the first conductivity type and a doped layer of the second conductivity type arranged sequentially from bottom to top, and includes a doped layer of the first conductivity type located in the doped layer of the second conductivity type. The body region 208 , the source region 202 is located in the body region 208 and is spaced a predetermined distance from the sidewall of the body region 208 , and at least a part of the gate layer 205 is located above the body region 208 .

As an example, the first conductivity type substrate layer 201a may be a silicon substrate, a silicon germanium substrate, a group III-V element compound substrate or other semiconductor material substrates known to those skilled in the art. The first conductivity type may be P-type or N-type, and correspondingly, the second conductivity type is N-type or P-type. In this embodiment, the first conductivity type substrate layer 201a is preferably a P-type silicon substrate.

As an example, the second conductivity type doped layer includes a first concentration doped layer 201b and a second concentration doped layer 201c arranged in sequence from bottom to top, and the body region 208 runs through the second concentration doped layer 201c and extend downwards into the first concentration doped layer 201b. In this embodiment, the first concentration doped layer 201b is selected from a deep N well (DNW), which is obtained by ion implantation into a preset region of the first conductivity type substrate layer 201a, and is mainly used for device isolation. Prevent the latch-up effect (latch up) caused by parasitic devices in the working process. The second concentration doped layer 201c is also obtained by performing ion implantation on a preset region of the first conductivity type substrate layer 201a, the implantation depth is shallower than that of the first concentration doped layer 201b, and the second concentration The doped layer 201c serves as a drift region in the device and mainly affects the withstand voltage (BV) and on-resistance of the NLDMOS.

As an example, the material of the gate dielectric layer 204 may be silicon dioxide or other suitable dielectric materials, the material of the gate layer 205 may be polysilicon or other suitable conductive materials, and the silicide barrier layer 206 The material may be silicon nitride or other suitable insulating materials, and the material of the split contact field plate 207 may be metal tungsten or other suitable metal materials.

As an example, sidewalls 211 are further provided on both sides of the gate layer 205, and the sidewalls 211 may include one or more of a silicon dioxide layer and a silicon nitride layer.

Specifically, the channel direction refers to a direction from the source region 202 to the drain region 202 horizontally.

As an example, the number of field slabs included in a split contact field plate 207 can be adjusted as required, for example, 2-10. In this embodiment, three field slats are taken as an example, as shown in FIG. 3 and FIG. 4 , which show a first field slab 207 a , a second field slat 207 b and a third field slat 207 c. It can be seen from FIG. 4 that the field slabs are long and narrow.

As an example, the field plate strips have a width ranging from 0.1 micron to 0.5 micron, such as 0.19 micron, 0.22 micron or other suitable widths. Due to the narrow width of the field plate, when the field plate hole is formed by etching, the side wall of the field plate hole is more likely to be vertical, and correspondingly, the side wall of the field plate obtained after filling the metal is also more vertical. Vertically, in this embodiment, the slope of the sidewall of the field slab is less than 5°.

As an example, the LDMOS device structure further includes a source contact portion 209 and a drain contact portion 210, the bottom end of the source contact portion 209 is in contact with the source region 202 and is an ohmic contact, and the drain contact The bottom end of portion 210 is in contact with the drain region 203 and is in ohmic contact.

As an example, the width of at least one field plate is the same as or close to the width of the source contact 209 (the deviation is not greater than 50%), or the width of at least one field plate is the same as that of the drain contact 209 The widths of 210 are the same or close (the deviation is not greater than 50%), which is more conducive to process control.

As an example, the widths of the plurality of field slabs may be the same, or at least two of the field slabs may have different widths, as long as the width of the field slab with the largest width does not cause the above problems.

As an example, the split contact field plate includes at least three field plate strips arranged at intervals along the channel direction, wherein the distance between any two adjacent field plate strips may be the same, or there may be at least one pair The distance between two adjacent field slabs is different from the distance between another pair of adjacent two field slabs.

Please refer to Fig. 5 and Fig. 6, wherein Fig. 5 shows the current density distribution diagram of the LDMOS device structure based on the large-scale bulk contact field plate shown in Fig. 1 and Fig. 2 under withstand voltage, and Fig. 6 shows the current density distribution of the present invention The current density distribution diagram of the LDMOS device structure based on the split contact field plate structure under withstand voltage, it can be seen that the LDMOS device structure based on the split contact field plate structure of the present invention is different from the conventional LDMOS device based on the large-scale bulk contact field plate The current density distribution of the structures is very consistent.

Please refer to FIG. 7, which shows the withstand voltage curves of the LDMOS device structure based on the split contact field plate structure of the present invention and the conventional LDMOS device structure based on the large-scale bulk contact field plate. It can be seen that when the two device structures are applied to 20V There is no difference in the following cases, and the achievable withstand voltage performance is equivalent.

From the above test results, it can be known that the LDMOS device structure based on the split contact field plate structure of the present invention is equivalent to the depletion degree in the drift region of the conventional LDMOS device structure based on the large-scale bulk contact field plate structure, and the realized current density distribution The same, that is, the electrical properties of the two contact field plates are consistent.

In summary, the LDMOS device structure of the present invention splits the large-sized bulk contact field plate into multiple small-sized contact field plates along the length direction of the device channel, and the multiple small-sized contact field plates form a split contact field plate, compared with the LDMOS based on the large-size bulk contact field plate, the LDMOS device based on the split contact field plate structure of the present invention can not only achieve basically the same electrical performance, achieve a considerable withstand voltage performance, but also Straighter morphology can be achieved in the etching process, and the critical dimension is easy to achieve the target value. At the same time, metal filling is easier and does not affect the photolithographic alignment of the first layer of metal in the subsequent process. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (10)

1. An LDMOS device structure, comprising:

a semiconductor layer;

a source region and a drain region in the semiconductor layer and spaced apart in a horizontal direction;

the gate dielectric layer is positioned on the semiconductor layer and is arranged between the source electrode area and the drain electrode area;

the gate layer is positioned on the gate dielectric layer, and the distance between the gate layer and the source electrode area is smaller than the distance between the gate layer and the drain electrode area;

the silicide barrier layer covers one part of the upper surface of the grid electrode layer and extends to the upper surface of the grid dielectric layer along the direction towards the drain electrode area;

and the split contact field plate is positioned on the silicide barrier layer and is arranged between the grid electrode layer and the drain electrode region in the horizontal direction, and the split contact field plate comprises at least two field plates which are arranged at intervals along the channel direction.

2. The LDMOS device structure of claim 1, wherein: the semiconductor layer comprises a first conductive type substrate layer and a second conductive type doping layer which are sequentially arranged from bottom to top, and comprises a first conductive type body region positioned in the second conductive type doping layer, the source region is positioned in the body region and is spaced from the side wall of the body region by a preset distance, and at least one part of the gate layer is positioned above the body region.

3. The LDMOS device structure of claim 2, wherein: the second conductive type doping layer comprises a first concentration doping layer and a second concentration doping layer which are sequentially arranged from bottom to top, the doping concentration of the first concentration doping layer is smaller than that of the second concentration doping layer, and the body region penetrates through the second concentration doping layer and extends downwards into the first concentration doping layer.

4. The LDMOS device structure of claim 1, wherein: the width of the field plate is in the range of 0.1 micron to 0.5 micron.

5. The LDMOS device structure of claim 1, wherein: the width of a plurality of the field slats is the same.

6. The LDMOS device structure of claim 1, wherein: at least two of the field plates have different widths.

7. The LDMOS device structure of claim 1, wherein: the split type contact field plate comprises at least three field strips which are arranged at intervals along the channel direction, and the distance between any two adjacent field strips is the same.

8. The LDMOS device structure of claim 1, wherein: the split contact field plate comprises at least three field strips which are arranged at intervals along the channel direction, and the distance between at least one pair of adjacent two field strips is different from the distance between the other pair of adjacent two field strips.

9. The LDMOS device structure of claim 1, wherein: the LDMOS device structure further comprises a source contact and a drain contact, the bottom end of the source contact is in contact with the source region, the bottom end of the drain contact is in contact with the drain region, the width of at least one field plate is the same as that of the source contact, or the width of at least one field plate is the same as that of the drain contact.

10. The LDMOS device structure of claim 1, wherein: the field slats have a sidewall inclination of less than 5 °.

Images