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CN115472686A - 一种低动态电阻增强型GaN器件 - Google Patents

一种低动态电阻增强型GaN器件 Download PDF

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CN115472686A
CN115472686A CN202110726646.8A CN202110726646A CN115472686A CN 115472686 A CN115472686 A CN 115472686A CN 202110726646 A CN202110726646 A CN 202110726646A CN 115472686 A CN115472686 A CN 115472686A
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CN115472686B (zh
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魏进
吴妍霖
杨俊杰
王茂俊
沈波
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Peking University
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Abstract

本发明公开了一种低动态电阻增强型GaN器件，在传统的增强型HEMT增强型器件制备工艺中，通过选择性刻蚀p‑GaN外延层被引入一个额外的P型掺杂的GaN薄层(即p‑GaN薄层)。这种器件结构中p‑GaN薄层形成的表面陷阱屏蔽效应和空穴注入效应有效地抑制了器件中陷阱的电离，对电流崩塌效应具有极强的抑制作用，因此，改善了GaN器件的电阻退化情况，提高了器件的动态稳定性，优化了器件的导通特性。

Description

一种低动态电阻增强型GaN器件
技术领域
本发明涉及GaN增强型半导体器件结构，特别涉及一种低动态电阻增强型GaN器件，例如增强型GaN HEMT(高电子迁移率晶体管)器件，属于电力电子器件领域。
背景技术
在GaN器件漏极施加高压后会导致器件导通电阻增大，该现象叫做动态电阻退化效应，会影响器件的动态稳定性、退化其导通特性，限制了GaN器件的进一步发展。因此，如何抑制GaN器件中的电流崩塌效应并改善器件的导通特性是GaN器件一个研究热点。
在现有技术中，松下电器有限公司提出通过选择性刻蚀，在漏极区域额外引入了一层与漏极相连的p-GaN结构来抑制电流崩塌效应(参见文献：H.Okita,M.Hikita,A.Nishio,et al.Through Recess and Regrowth Gate Technology for RealizingProcess Stability of GaN-Based Gate Injection Transistors[J].IEEETransactions on Electron Devices,2017,64(3):1026-1031.)，该技术为了实现增强型器件，需要完全刻蚀掉栅极区域的势垒层，完成刻蚀后再外延一层较薄的势垒层来形成栅极区域的二维电子气沟道，这使器件的制备工艺更加复杂且器件的阈值电压难以精确控制。不仅如此，完全刻蚀掉势垒层会使沟道层暴露在刻蚀气体下，在沟道层中会造成更多的损害和缺陷，降低二维电子气的迁移率。
在现有技术中，一种带有长p-GaN栅极的极化超级结(PolarizationSuperjunction)场效应管被日本的POWDEC公司提出(S.Hirata,F.Nakamura and H.Kawai,et al.600V Switching Characteristics of GaN Polarization SuperJunction(PSJ)Transistors on Sapphire substrate.Autumn meeting of the Japanese AppliedPhysics,2014)来提高器件的击穿电压。然而，该器件是一个耗尽型(常开型)器件，常开型器件在电路中提高了电路设计的复杂性，降低了系统的可靠性。
发明内容
针对目前存在的GaN HEMT器件中因电流崩塌效应导致的导通电阻退化问题，本发明首先提供了一种新型增强型GaN HEMT器件结构，以抑制电流崩塌效应并提高沟道中二维电子气浓度，以改善动态电阻退化现象。为了增强对动态电阻退化效应的抑制作用并简化工艺步骤，本发明的器件结构如图1所示，在传统的HEMT增强型器件制备工艺中，一个额外的P型掺杂的GaN薄层(即p-GaN薄层)通过选择性刻蚀p-GaN外延层被引入，该p-GaN薄层覆盖在势垒层表面与p-GaN帽层相连，可以屏蔽势垒层表面的陷阱，且p-GaN薄层会注入空穴至到器件内部，复合器件中电离的陷阱，有效地抑制电流崩塌效应。在制备工艺中无需对势垒层进行额外的刻蚀步骤，实现了对阈值电压的精确控制。
具体的，本发明的技术方案如下：
一种增强型GaN HEMT器件，如图1所示，包括衬底和在衬底上从下往上依次层叠的缓冲层、GaN沟道层和AlGaN势垒层，其特征在于，通过选择性刻蚀AlGaN势垒层上的p-GaN外延层形成p-GaN帽层和p-GaN薄层，该p-GaN薄层覆盖在AlGaN势垒层表面且与p-GaN帽层相连；源极和漏极设于AlGaN势垒层上表面，栅极位于p-GaN帽层上表面，所述栅极和p-GaN薄层位于所述源极和漏极之间。
本发明增强型GaN HEMT器件结构中的p-GaN层可以抬高二维电子气沟道处的导带能级，实现增强型器件技术，如图2所示，展示了无栅极偏压下器件中二维电子气分布情况，该器件中p-GaN层覆盖区域下的二维电子气被完全耗尽，使器件在无外加偏压下表现为关断态。同时，由于p-GaN薄层覆盖在AlGaN势垒层表面，对AlGaN层表面陷阱具有屏蔽作用，能削弱势垒层表面陷阱对电子的俘获作用，抑制了因势垒层表面陷阱俘获电子引起的电流崩塌效应。不仅如此，如图3所示，当器件的栅源极电压差VGS>0V时，p-GaN层会注入空穴至到器件内部，空穴会中和器件缓冲层中的负电中心，降低负电中心对二维电子气的排斥作用，从而有效抑制因缓冲层中深能级负电中心导致的动态导通特性退化。延伸的p-GaN薄层与栅极相连，因此该p-GaN薄层能起到与栅极相同的作用，可以通过栅极外加偏压的方式在势垒层下感应出更多二维电子气，优化器件的导通特性并降低器件的导通损耗。
所述p-GaN薄层可以覆盖整个势垒层表面，也可以仅覆盖在栅极附近，p-GaN薄层可以是均一厚度的，也可以在不同区域的厚度有所变化，从其纵剖面看可以是长条形、阶梯形等。
所述p-GaN薄层的厚度优选为1nm至400nm，更优选为100nm，取决于不同的设计需求和制备工艺。
在本发明的一个实施例中，所述p-GaN薄层通过一金属电极与漏极相连，该金属电极与p-GaN薄层之间形成肖特基接触，在器件关断时该肖特基结会反偏辅助p-GaN耗尽，改善器件的耐压性能。
在本发明的另一个实施例中，在源极和栅极之间额外增加一个p-GaN帽层及其上的第二栅极，通过第二栅极来控制共同器件的开关，实现了cascode结构。
上述p-GaN薄层可以引入到各种半导体器件中，例如GaN LED、MIS结构增强型HEMT器件、肖特基二极管、PN结二极管和其它GaN功率器件，都有益于改善电流崩塌效应。
本发明还提供了一种GaN二极管，包括衬底和在衬底上从下往上依次层叠的缓冲层、GaN沟道层和AlGaN势垒层，其特征在于，通过选择性刻蚀AlGaN势垒层上的p-GaN外延层形成p-GaN帽层和p-GaN薄层，该p-GaN薄层覆盖在AlGaN势垒层表面且与p-GaN帽层相连；阳极和阴极设于AlGaN势垒层上表面，栅极位于p-GaN帽层上表面，所述栅极和p-GaN薄层位于所述源极和漏极之间，阳极与栅极电连接。
上述GaN二极管中，所述p-GaN薄层的形状、厚度、掺杂浓度等参数的变化同所述p-GaN HEMT器件，取决于不同的设计需求和制备工艺，其纵剖面形状可以是长条形、阶梯形等，其厚度优选为1nm至400nm。
本发明的有益效果：
通过本发明所提供的新型器件结构中p-GaN薄层形成的表面陷阱屏蔽效应和空穴注入效应，有效地抑制了器件中陷阱的电离，对电流崩塌效应具有极强的抑制作用，因此，改善了GaN器件的电阻退化情况，提高了器件的动态稳定性，优化了器件的导通特性。
附图说明
图1是本发明提出的增强型GaN HEMT器件二维截面图。
图2展示图1所示器件无外加偏压时的二维电子气分布情况，可以看出p-GaN会耗尽沟道中的二维电子气，从而制备出增强型器件。
图3是图1所示器件中p-GaN薄层激发的空穴注入现象的示意图。
图4是本发明实施例二的器件的二维截面图，p-GaN薄层由长条形变为阶梯状。
图5是本发明实施例三的器件的二维截面图，在p-GaN薄层和漏极之间增加一个新的金属电极，与p-GaN薄层之间形成肖特极接触。
图6是本发明实施例四的器件的二维截面图，该器件为cascode结构，增加一个第二栅极来共同控制器件的开关。
图7是本发明实施例五的器件的二维截面图，是一个GaN二极管，器件中p-GaN层上的栅极与阳极相连。
具体实施方式
实施例一：本发明中的增强型GaN HEMT器件结构
图1是本发明第一种实例涉及的GaN器件的截面图，如图1所示，本器件包含外延所需的衬底1，可以采用硅衬底、蓝宝石衬底和碳化硅衬底；能平衡外延过程中应力、降低器件漏电流、提高击穿电压的缓冲层2；提供导电沟道的GaN沟道层3；通过极化效应产生二维电子气的AlGaN势垒层4；耗尽二维电子气的p-GaN帽层5；用于屏蔽势垒层表面陷阱和通过空穴注入复合缓冲层中负电中心的p-GaN薄层6；栅极7、漏极8、源极9等接触电极，其中源极和漏极采用欧姆接触分别制备在器件两端，栅极制备于p-GaN帽层上；以及传统p-GaN器件中所必需的钝化层、场板等结构，虽然图中未显示，但在本实例及后述的其它实例中，都包含相应的结构。
此外，延伸的p-GaN薄层6的长度、厚度、掺杂浓度等参数的变化都是本发明所涉及的范畴。该p-GaN薄层6可以覆盖整个势垒层表面，也可以仅覆盖在栅极附近，其长度能发生变化。该p-GaN薄层6厚度的变化范围为1nm至400nm，最优值为100nm，取决于不同的设计需求和制备工艺。该p-GaN薄层6的掺杂浓度在合理范围内可以发生变化，这与器件阈值电压设计和掺杂工艺有关。可以理解，在不脱离本发明的范围，可以有其他结构和其他变化的实例。再者，不同的实例、结构和工艺可以相互组合。
参照附图中的这些实例可以用于制作该新型p-GaN HEMT器件，但是，所述结构不仅仅限于这一种应用方式，依照本发明实例可以制备任何合适的半导体器件，例如GaNLED、MIS结构增强型HEMT器件、肖特基二极管、PN结二极管和其它GaN功率器件，都有益于改善电流崩塌效应。
实施例二：本发明中的增强型GaN HEMT器件结构
图4是本发明第二种实例所涉及的GaN器件的截面图，本实例的GaN器件与第一种实例不同，其p-GaN薄层由长条形变为阶梯形。其他结构和效果与第一种实例一致。
实施例三：本发明中的增强型GaN HEMT器件结构
图5是本发明第三种实例所涉及的GaN器件的截面图，本实例的GaN器件与第一和第二种实例不同，其在漏极9和p-GaN薄层6之间额外增加一个与漏极9相连的金属电极10，该金属电极10与p-GaN薄层6之间形成肖特基接触，在关断时该肖特基结会反偏辅助p-GaN耗尽，改善器件的耐压性能。其他结构和效果与第一种实例一致。
实施例四：本发明中的增强型GaN HEMT器件结构
图6是本发明第四种实例所涉及的GaN器件cascode的截面图，本实例的GaN器件在源极8和栅极7之间额外增加一个p-GaN帽层11和第二栅极12，通过第二栅极12和栅极7来共同控制器件的开关，也可以使栅极7外加偏压保持不变来抑制电流崩塌效应，并感应出更多的沟道电子。
实施例五：本发明中的GaN二极管器件结构
图7是本发明第五种实例所涉及的GaN器件的截面图，本实例的GaN器件是一个二极管，将漏极9和源极8替换为二极管的阴极14和阳极13，阳极13可以做欧姆接触或肖特基接触，这与设计有关，其中阳极13通过外接连线15或其他方式与栅极7相连。

Claims (8)

1.一种增强型GaN HEMT器件，包括衬底和在衬底上从下往上依次层叠的缓冲层、GaN沟道层和AlGaN势垒层，其特征在于，通过选择性刻蚀AlGaN势垒层上的p-GaN外延层形成p-GaN帽层和p-GaN薄层，该p-GaN薄层覆盖在AlGaN势垒层表面且与p-GaN帽层相连；源极和漏极设于AlGaN势垒层上表面，栅极位于p-GaN帽层上表面，所述栅极和p-GaN薄层位于所述源极和漏极之间。
2.如权利要求1所述的增强型GaN HEMT器件，其特征在于，所述p-GaN薄层的厚度是均一的或呈阶梯状变化。
3.如权利要求1所述的增强型GaN HEMT器件，其特征在于，所述p-GaN薄层的厚度为1～400nm。
4.如权利要求1所述的增强型GaN HEMT器件，其特征在于，所述p-GaN薄层通过一金属电极与漏极相连，该金属电极与p-GaN薄层之间形成肖特基接触。
5.如权利要求1所述的增强型GaN HEMT器件，其特征在于，在源极和栅极之间设有另一个p-GaN帽层，其上为第二栅极。
6.一种GaN二极管，包括衬底和在衬底上从下往上依次层叠的缓冲层、GaN沟道层和AlGaN势垒层，其特征在于，通过选择性刻蚀AlGaN势垒层上的p-GaN外延层形成p-GaN帽层和p-GaN薄层，该p-GaN薄层覆盖在AlGaN势垒层表面且与p-GaN帽层相连；阳极和阴极设于AlGaN势垒层上表面，栅极位于p-GaN帽层上表面，所述栅极和p-GaN薄层位于所述源极和漏极之间，阳极与栅极电连接。
7.如权利要求7所述的GaN二极管，其特征在于，所述p-GaN薄层的厚度是均一的或呈阶梯状变化。
8.如权利要求7所述的GaN二极管，其特征在于，所述p-GaN薄层的厚度为1～400nm。
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