CN115472499A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The invention discloses a manufacturing method of a semiconductor device, which comprises the following steps: forming a basic functional layer on a substrate; forming a conductive mask layer on the basic functional layer; etching the conductive mask layer to form a window sunken downwards on the conductive mask layer; forming an insulating medium layer on the conductive mask layer and the window; etching the insulating medium layer to form a side wall in the window, wherein the side wall is positioned on the side wall of the conductive mask layer; forming a carrier providing layer between the side walls; etching the conductive mask layer and the basic functional layer at the periphery of the window to form a downward sunken table top; and forming a passivation layer on the mesa, the conductive mask layer, the carrier supply layer and the sidewall. The invention also discloses a semiconductor device obtained by the manufacturing method, wherein the semiconductor device is a bipolar transistor or a pin junction diode.

Description

Semiconductor device and manufacturing method thereof

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

The continuous development of chip technology has pushed into the post-Moore era, which is mainly characterized by the continuous scaling of semiconductor devices to achieve higher device integration densities. The basic scaling technology of semiconductor devices based on diodes and transistors has become a key technology. Taking bipolar transistors as an example, bipolar transistors are very important high-speed solid-state devices in the field of microwave and millimeter waves. They have the characteristics of high power density and gain, low phase noise, and good linearity. They are especially suitable for power switching devices and radio frequency power amplifier. Improving switching speed and frequency performance is an important development trend of bipolar transistors. The external parasitic capacitance resistance introduced by the base contact electrode is the main factor limiting the continuous improvement of device performance. In order to obtain higher performance, the size of the external base area is continuously reduced to reduce the parasitic effect.

Self-alignment technology is an effective method that can reduce the size of the external base region to the extreme, and is widely used in InP and GaAs. However, this often depends on the fact that InP and GaAs materials have high etching lateral and vertical selectivity ratios, and it is necessary to form an inverted mesa-shaped emission region mesa by etching; this technology is difficult to precisely control the etching angle. Device performance is not uniform. The self-alignment technology applied to InGaP/GaAsSb-based heterojunction bipolar transistors is disclosed in the related art. This technology not only involves multiple process steps such as sidewalls and etching openings, but also requires the emitter to pass through The etch width must be smaller than the etch mask. However, it is difficult to achieve this etching morphology in GaN-based, SiC, and SiGe-based materials, so this technology cannot be applied to transistors made of the above materials. In addition, it is also disclosed in the related art that the self-alignment technology relying on the sidewall process is usually applied to semiconductor devices to reduce the size, but this technology uses complex processes such as three sidewalls, etching, ion implantation, etc. , not only the process is difficult, but also the size of the external base cannot be minimized. Moreover, this technology requires an ion implantation process to realize the emitter region and the base region, and is also not suitable for the preparation of GaN-based transistors.

Contents of the invention

In view of this, the present invention provides a method for manufacturing a semiconductor device, using the method to manufacture bipolar transistors, and controlling the distance between the emitter region and the base electrode by controlling the thickness of the sidewall, so as to realize the separation between the base electrode and the emitter region. The minimum size of the spacing is used to reduce the size of the external base region and reduce the external parasitic parameters of the device, thereby effectively improving the performance of the device.

The invention provides a manufacturing method of a semiconductor device, comprising: forming a basic functional layer on a substrate; forming a conductive mask layer on the basic functional layer; etching the conductive mask layer to form a downward facing layer on the conductive mask layer A recessed window; forming an insulating dielectric layer on the conductive mask layer and the window; etching the insulating dielectric layer to form spacers in the window, the sidewalls being located on the sidewalls of the conductive mask layer; forming a current-carrying layer between the sidewalls sub-providing layer; etching the conductive mask layer and the basic functional layer on the periphery of the window to form a downwardly recessed mesa; and forming a passivation layer on the mesa, the conductive mask layer, the carrier supply layer and the side wall.

According to an embodiment of the present invention, the semiconductor device is a bipolar transistor, the window is an emission region window, and the carrier supply layer is an emission region;

Forming the basic functional layer on the substrate includes: sequentially forming an n-type heavily doped sub-collector region, an n-type lightly doped collector region, and a p-type base region on the substrate; etching the conductive mask layer, basically The functional layer to form a downwardly recessed mesa includes: etching a conductive mask layer, a p-type base region, and an n-type lightly doped collector region to form a downwardly recessed mesa.

According to an embodiment of the present invention, the above manufacturing method further includes: forming a dielectric mask layer on the conductive mask layer; etching the conductive mask layer to form a window includes: etching the dielectric mask layer and the conductive mask layer, to form the emission region window; wherein, the sidewalls formed in the emission region window are located on the sidewalls of the conductive mask layer and the dielectric mask layer.

According to an embodiment of the present invention, the above manufacturing method further includes: forming an emitter electrode via hole on the passivation layer located on the emitter region, forming a base via hole on the passivation layer located on the conductive mask layer, A collector through hole is formed on the passivation layer on the n-type heavily doped sub-collector region; an emitter electrode is formed in the emitter electrode through hole, a base electrode is formed in the base through hole, and a collector through hole is formed. A collector electrode is formed inside the hole.

According to another embodiment of the present invention, the semiconductor device is a pin junction diode, and the carrier supply layer is a p-type layer;

Forming the basic functional layer on the substrate includes: sequentially forming an n-type layer and an i-type layer on the substrate, etching the conductive mask layer and the basic functional layer to form a downwardly recessed mesa includes: etching the conductive mask layer , i-type layer, and n-type layer to form a downwardly recessed mesa.

The present invention also provides a semiconductor device obtained by the above manufacturing method, the semiconductor device is a bipolar transistor, comprising: a substrate; an n-type heavily doped sub-collector region formed on the substrate; an n-type light The doped collector region is formed on the n-type heavily doped sub-collector region; the p-type base region is formed on the n-type lightly doped collector region, wherein the n-type lightly doped collector region and the p-type base region form a mesa on the n-type heavily doped sub-collector region; the conductive mask layer is formed on the p-type base region, and an emitter window is formed on the conductive mask layer; the emitter region is formed on the emitter In the region window, and a sidewall is formed between the emission region and the conductive mask layer; and a passivation layer is formed on the n-type heavily doped sub-collector region, the conductive mask layer, the emission region and the sidewall; wherein , The p-type base region is suitable for injecting external current, the emitter region is suitable for generating electron current and forming an amplified current after passing through the p-type base region, and the n-type heavily doped sub-collector region is suitable for outputting amplified current.

The present invention also provides a semiconductor device obtained by the above manufacturing method, the semiconductor device is a pin junction diode, comprising: a substrate; an n-type layer formed on the substrate; an i-type layer formed on the n-type layer, The i-type layer and the n-type layer form a mesa on the substrate; the conductive mask layer is formed on the i-type layer, and a window is formed on the conductive mask layer; the p-type layer is formed in the window, and the p-type layer and the conductive A side wall is formed between the mask layers; a passivation layer is formed on the substrate, a conductive mask layer, a p-type layer and a side wall; a p-type electrode is formed in a p-type electrode through hole, and the p-type electrode through hole formed on the passivation layer on the p-type layer; and an n-type electrode formed in the n-type electrode through hole, and the n-type electrode through hole is formed on the passivation layer on the conductive mask layer.

According to the manufacturing method of the semiconductor device provided by the above-mentioned embodiments of the present invention, the bipolar transistor is manufactured by using the manufacturing method, and the distance between the base electrode and the emitter region can be controlled by controlling the thickness of the sidewall, and the base electrode and the emitter region can be realized. The minimum size of the distance between them, thereby realizing the minimum size of the external base area, can reduce the external parasitic parameters of the device, reduce the resistance of the device, and improve the operating frequency and efficiency of the device.

Description of drawings

Fig. 1 is the flowchart of the manufacturing method of the bipolar transistor according to the embodiment of the present invention;

2(a)-2(i) are cross-sectional schematic diagrams of the manufacturing process of the bipolar transistor according to an embodiment of the present invention;

3 is a flowchart of a method for manufacturing a bipolar transistor according to another embodiment of the present invention;

4(a)-4(i) are cross-sectional schematic diagrams of the fabrication process of a bipolar transistor according to another embodiment of the present invention;

5 is a schematic cross-sectional view of a bipolar transistor according to another embodiment of the present invention;

Fig. 6 is the flowchart of the manufacturing method of the pin junction diode according to the embodiment of the present invention; And

7( a ) to 7 ( i ) are schematic cross-sectional views of the fabrication process of a pin junction diode according to an embodiment of the present invention.

[Description of Reference Signs]

1-substrate; 2-n-type heavily doped sub-collector region;

3-n-type lightly doped collector region; 4-p-type base region;

5-conductive mask layer; 6-photoresist layer;

7- insulating medium layer; 8- emission area;

9-passivation layer; 1001-emitter electrode;

1002-base electrode; 1003-collector;

11-dielectric mask layer; 1004-external electrodes in the emission area;

02-n-type layer; 03-i-type layer;

08-p-type layer; 1005-p-type electrode;

1006-n-type electrode.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. However, this invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and like reference numerals designate like elements throughout.

The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the invention. The terms "comprising", "comprising", etc. used herein indicate the presence of stated features, steps, operations and/or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

In view of this, the present invention proposes a self-alignment technology that is simple in process, high in uniformity and repeatability, and applicable to semiconductor devices of various materials. The present invention proposes a method for making a small-sized semiconductor device using self-alignment technology, using the method to make bipolar transistors, and realizing a smaller distance between the base electrode and the emitter region through the self-alignment process, which can effectively The size of the external base region of the device can be greatly reduced, and the external parasitic parameters of the device can be reduced, thereby improving the performance of the device.

The invention provides a manufacturing method of a semiconductor device, comprising: forming a basic functional layer on a substrate; forming a conductive mask layer on the basic functional layer; etching the conductive mask layer to form a downward facing layer on the conductive mask layer A recessed window; forming an insulating dielectric layer on the conductive mask layer and the window; etching the insulating dielectric layer to form spacers in the window, the sidewalls being located on the sidewalls of the conductive mask layer; forming a current-carrying layer between the sidewalls sub-providing layer; etching the conductive mask layer and the basic functional layer on the periphery of the window to form a downwardly recessed mesa; and forming a passivation layer on the mesa, the conductive mask layer, the carrier supply layer and the side wall.

It should be noted that an npn-type GaN-based bipolar transistor is taken as an example to describe embodiments of the present invention.

FIG. 1 is a flowchart of a method for fabricating a bipolar transistor according to an embodiment of the present invention. 2( a ) to 2 ( i ) are schematic cross-sectional views of the fabrication process of the bipolar transistor according to the embodiment of the present invention.

According to an exemplary embodiment of the present invention, the present invention provides a method for manufacturing a bipolar transistor, as shown in FIG. 1 , including steps S01-S08.

In step S01 , a heavily n-type doped sub-collector region 2 , a lightly n-type doped collector region 3 , and a p-type base region 4 are sequentially formed on a substrate 1 .

According to an embodiment of the present invention, as shown in FIG. 2( a ), the substrate 1 includes one of the following: Si substrate, sapphire substrate, SiC substrate and GaN free-standing substrate.

According to an embodiment of the present invention, the material of the n-type heavily doped sub-collector region 2 may be one or more selected from GaN and AlGaN, or SiGe, or SiC, or one selected from GaAs and InP. One or more; the thickness can be 100nm-20μm. The n-type heavily doped sub-collector region 2 has a higher doping concentration to ensure a lower resistivity. The doping elements include Si, Ge, N, and P, and the doping concentration range can be 1×10 ¹⁹ cm ^-3 -1×10 ²⁰ cm ^-3 .

According to an embodiment of the present invention, the material of the n-type lightly doped collector region 3 may be one or more selected from GaN and AlGaN, or SiGe, or SiC, or one selected from GaAs and InP or more; the thickness is 50nm-20μm. The doping concentration of the n-type lightly doped collector region 3 is relatively low, and the doping elements include Si, Ge, N, and P. The doping concentration can range from 1×10 ¹⁵ cm ^-3 to 5×10 ¹⁷ cm ^{- 3} .

It should be noted that for high-voltage power devices, the lightly n-type doped collector region 3 is required to be thicker, for example, for 1200V high-voltage applications, the thickness range may be 12-15 μm. For radio frequency devices, it is required that the n-type lightly doped collector region 3 has a thinner thickness in order to reduce the electron transit time and improve the frequency performance of the device, and the thickness range can be 100-500nm.

According to an embodiment of the present invention, the material of the p-type base region 4 is selected from GaN, _{AlxGa1 - xN} , _{InxAl1 - xN} , InxAlyGa1 _{- xyN} and _InxGa1- One or more of _x N, or one or more of Si and SiC, or SiGe, or one or more of GaAs and InP, 0≤x≤0.45; p-type group Region 4 is a single component with constant elemental component content or a gradual component with linearly changing elemental component content; for example, the p-type base region 4 can be Al _0.3 Ga _0.7 N, or the p-type base region 4 can be The element composition content changes linearly from x ₁ to x ₂ , Al _x Ga _1-x N, 0≤x ₁ ≤x ₂ ≤0.45; the thickness of the p-type base region 4 is 50nm-500nm; the p-type base The doping elements in region 4 include Si, Ge, B, and Al, and the doping concentration is 2×10 ¹⁷ cm ^-3 -3×10 ²⁰ cm ^-3 . The p-type base region 4 requires the resistivity to be as low as possible, so the material of the p-type base region 4 can be InGaN. In order to improve the frequency performance of the device, the p-type base region 4 can also be made with a graded doping concentration, that is, the p-type base region 4 can be doped with a graded concentration whose concentration changes linearly along the thickness direction.

In step S02 , a conductive mask layer 5 is formed on the p-type base region 4 .

According to an embodiment of the present invention, as shown in FIG. 2( b ), a conductive mask layer 5 is formed on the p-type base region 4 , and the conductive mask layer 5 forms an ohmic contact with the p-type base region 4 . The material of the conductive mask layer 5 is NiO, W, Cr, Mo; the thickness is 20-300nm, for example, 20nm, 50nm, 100nm, 200nm, 300nm.

In step S03, the conductive mask layer 5 is etched to form a window for the emission region.

According to an embodiment of the present invention, as shown in FIG. 2( c ), a photoresist layer 6 is coated on the conductive mask layer 5 , and a patterned mask is formed after exposure. With the photoresist layer 6 as a mask, the conductive mask layer 5 is etched, the conductive mask layer 5 not covered by the photoresist layer 6 is removed, and the conductive mask layer 5 covered by the photoresist layer 6 is retained to form launch window. Wherein, the method of etching the conductive mask layer 5 includes dry etching or wet etching.

In step S04, an insulating dielectric layer 7 is formed on the conductive mask layer 5 and the emission region window.

According to an embodiment of the present invention, referring to FIG. 2( d ), an insulating dielectric layer 7 is formed on the conductive mask layer 5 and the emission region window. The pyrolysis temperature of the insulating dielectric layer 7 is greater than 1000°C; the insulating dielectric layer 7 can be made of SiO ₂ or SiN with a thickness of 10-100nm, for example, 10nm, 20nm, 50nm, 70nm, 100nm.

In step S05, the insulating dielectric layer 7 is etched to form sidewalls in the window of the emission region.

According to an embodiment of the present invention, referring to FIG. 2( e ), the insulating dielectric layer 7 is etched by a dry method so that the insulating dielectric layer 7 forms sidewalls on the sidewalls of the conductive mask layer 5 .

In step S06, the emission area 8 is formed in the emission area window.

According to an embodiment of the present invention, as shown in FIG. 2(f), metal organic compound chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), pulsed laser deposition, hydride vapor phase epitaxy or physical vapor deposition are used in the emission region window An emission region 8 is formed. The material of the emission region 8 can be one or more selected from GaN, _{AlxGa1 - xN} , _{InxAl1 - xN} and InxAlyGa1 _-xyN , or selected from Si and SiC One or more of them, or SiGe, or one or more of GaAs and InP, 0≤x≤0.3; the material of the emission region 8 is a single component or element group with constant element component content Gradient composition whose content changes linearly along the thickness direction; the doping impurity in the emission region 8 is a donor impurity, such as Si, Ge, and the emission region 8 can be a fixed doping concentration or a different doping concentration The multilayer structure can also be a graded doping concentration.

In step S07, the conductive mask layer 5, the p-type base region 4 and the n-type lightly doped collector region 3 are etched to form a downwardly recessed mesa.

According to an embodiment of the present invention, referring to FIG. 2( g ), the conductive mask layer 5 , the p-type base region 4 and the n-type lightly doped collector region 3 are etched to form a downwardly recessed mesa. The method of etching the p-type base region 4 and the n-type lightly doped collector region 3 is dry etching. It should be noted that, after etching the conductive mask layer 5 , the p-type base region 4 and the n-type lightly doped collector region 3 to form a downwardly recessed mesa, the sidewalls can be kept or removed.

In step S08 , a passivation layer 9 is formed on the n-type heavily doped sub-collector region 2 , the conductive mask layer 5 , the emitter region 8 and the side walls.

According to an embodiment of the present invention, as shown in FIG. 2( h), remove the sidewall, and form Passivation layer9.

According to an embodiment of the present invention, the above manufacturing method further includes: steps S09-S10.

In step S09, an emitter electrode through hole is formed on the passivation layer 9 on the emitter region 8, a base through hole is formed on the passivation layer 9 on the conductive mask layer 5, and an n-type heavily doped A collector via hole is formed on the passivation layer 9 on the sub-collector region 2 .

In step S10 , the emitter electrode 1001 is formed in the emitter electrode through hole, the base electrode 1002 is formed in the base through hole, and the collector electrode 1003 is formed in the collector through hole.

According to an embodiment of the present invention, as shown in FIG. ; Fill the stacked layers of metal or metal alloy into the emitter electrode through hole, the base through hole and the collector through hole to form the emitter electrode 1001 , the base electrode 1002 and the collector electrode 1003 .

According to an exemplary embodiment of the present invention, as shown in FIG. 2(i), the present invention also provides a bipolar transistor obtained by the above manufacturing method, comprising: a substrate 1; an n-type heavily doped The sub-collector region 2 is formed on the substrate 1; the n-type lightly doped collector region 3 is formed on the n-type heavily doped sub-collector region 2; the p-type base region 4 is formed on the n-type lightly doped On the doped collector region 3, the n-type lightly doped collector region 3 and the p-type base region 4 form a mesa on the n-type heavily doped sub-collector region 2; a conductive mask layer 5 is formed On the p-type base region 4, an emission region window is formed on the conductive mask layer 5; the emission region 8 is formed in the emission region window, and a side wall is formed between the emission region 8 and the conductive mask layer 5; The layer 9 is formed on the n-type heavily doped sub-collector region 2, the conductive mask layer 5, the emitter region 8 and the side wall; wherein, the p-type base region 4 is suitable for injecting an external current, and the emitter region 8 is suitable for Electron current is generated and passed through the p-type base region 4 to form an amplified current, and the n-type heavily doped collector region 2 is suitable for outputting the aforesaid amplified current.

According to an embodiment of the present invention, the above-mentioned bipolar transistor further includes: emitter electrode 1001, suitable for grounding; base electrode 1002, suitable for applying current to p-type base region 4; collector electrode 1003, suitable for applying current to n-type base region 4; A voltage is applied to the heavily doped sub-collector region 2 .

3 is a flowchart of a method for manufacturing a bipolar transistor according to another embodiment of the present invention;

4(a)-4(i) are schematic cross-sectional views of the fabrication process of a bipolar transistor according to another embodiment of the present invention.

It should be noted that an npn-type GaN-based bipolar transistor is taken as an example to describe embodiments of the present invention.

According to an exemplary embodiment of the present invention, the present invention provides a method for manufacturing a bipolar transistor, as shown in FIG. 3 , including steps S01-S13.

In step S01 , a heavily n-type doped sub-collector region 2 , a lightly n-type doped collector region 3 , and a p-type base region 4 are sequentially formed on a substrate 1 .

In step S02 , a conductive mask layer 5 is formed on the p-type base region 4 .

In step S03 , a dielectric mask layer 11 is formed on the conductive mask layer 5 .

According to an embodiment of the present invention, as shown in FIG. 4(a), a dielectric mask layer 11 is formed on the conductive mask layer 5, and the dielectric mask layer 11 and the conductive mask layer 5 have a higher etching selectivity ratio. The material of the dielectric mask layer 11 is SiO ₂ , SiN; the thickness is 50-300 nm, for example, 50 nm, 100 nm, 150 nm, 200 nm, 300 nm.

In step S04, the dielectric mask layer 11 and the conductive mask layer 5 are etched to form an emission region window.

According to an embodiment of the present invention, as shown in FIG. 4( b ), a photoresist layer 6 is coated on the dielectric mask layer 11 , and a patterned mask is formed after exposure. With the photoresist layer 6 as a mask, etch the dielectric mask layer 11 and the conductive mask layer 5, remove the dielectric mask layer 11 and the conductive mask layer 5 that are not covered by the photoresist layer 6, and retain the photoresist layer The dielectric mask layer 11 and the conductive mask layer 5 covered by the glue layer 6 form the window of the emission region. After the emission window is formed, the photoresist layer 6 is removed. Wherein, the method of etching the dielectric mask layer 11 and the conductive mask layer 5 includes dry etching or wet etching.

In step S05, an insulating dielectric layer 7 is formed on the dielectric mask layer 11 and the emission region window.

According to an embodiment of the present invention, as shown in FIG. 4(c), an insulating dielectric layer 7 is formed on the dielectric mask layer 11 and the emission region window, and the insulating dielectric layer 7 and the dielectric mask layer 11 have higher etching options. Compare. The pyrolysis temperature of the insulating dielectric layer 7 is greater than 1000°C; the insulating dielectric layer 7 can be made of SiO ₂ or SiN with a thickness of 10-100nm, for example, 10nm, 20nm, 50nm, 70nm, 100nm.

In step S06, the insulating dielectric layer 7 is etched to form spacers in the window of the emission region.

According to an embodiment of the present invention, as shown in FIG. 4( d), the insulating dielectric layer 7 is etched by a dry method, so that the insulating dielectric layer 7 forms sidewalls on the sidewalls of the conductive mask layer 5 and the dielectric mask layer 11. .

In step S07, the emission area 8 is formed in the emission area window.

According to an embodiment of the present invention, as shown in FIG. 4( e ), an emission region 8 is formed in the emission region window.

In step S08, the dielectric mask layer 11, the conductive mask layer 5, the p-type base region 4 and the n-type lightly doped collector region 3 are etched to form a downwardly recessed mesa.

According to an embodiment of the present invention, as shown in FIG. 4( f ), a photoresist layer is coated on the dielectric mask layer 11 , sidewalls and emission regions 8 , and a patterned mask is formed after exposure. Using the photoresist layer as a mask, the dielectric mask layer 11, the conductive mask layer 5, the p-type base region 4 and the n-type lightly doped collector region 3 are etched to form a downwardly recessed mesa. The method of etching the dielectric mask layer 11, the conductive mask layer 5, the p-type base region 4 and the lightly n-type doped collector region 3 is dry etching. It should be noted that after etching the dielectric mask layer 11, the conductive mask layer 5, the p-type base region 4 and the n-type lightly doped collector region 3 to form a downwardly recessed mesa, the spacer can be retained, Side walls can also be removed.

In step S09, the dielectric mask layer 11 is removed.

According to an embodiment of the present invention, referring to FIG. 4( g ), the dielectric mask layer 11 is removed by dry etching or wet etching.

In step S10 , an emitter electrode 1001 is formed on the emitter region 8 and the conductive mask layer 5 .

According to an embodiment of the present invention, as shown in FIG. 4( h ), an emitter electrode 1001 is formed on the emitter region 8 and the conductive mask layer 5 .

In step S11 , a passivation layer 9 is formed on the n-type heavily doped sub-collector region 2 , the emitter electrode 1001 and side walls.

In step S12, a collector via hole is formed on the passivation layer 9 located on the n-type heavily doped sub-collector region 2, and a base via hole is formed on the passivation layer 9 located on the conductive mask layer 5, On the passivation layer 9 located on the emitter region 8, a through hole for connecting the electrode outside the emitter region is formed.

In step S13, the base electrode 1002 is formed in the base through hole, the collector electrode 1003 is formed in the collector through hole, and the emitter region external electrode 1004 is formed in the emitter region external electrode through hole, as shown in FIG. 4(i) .

According to an embodiment of the present invention, the bipolar transistor is manufactured by using the above-mentioned manufacturing method, and the self-alignment of the base electrode can be realized by using one sidewall process, that is, the maximum Covering the mesa of the base area in a large area can simplify the manufacturing process of the device and reduce the difficulty of manufacturing high-frequency and small-size devices.

According to an embodiment of the present invention, the bipolar transistor is manufactured by the above-mentioned manufacturing method, and the distance between the emitter region and the base region electrode is controlled by controlling the thickness of the sidewall, so as to realize the minimum size of the distance between the base region electrode and the emitter region, so as to reduce the The size of the external base area is small, and the external parasitic parameters of the device are reduced, so that the working frequency and working efficiency of the device can be effectively improved.

According to the embodiment of the present invention, the bipolar transistor is fabricated by the above-mentioned manufacturing method. Since the side wall is formed between the emitter region and the base electrode, the emitter electrode can cover the emitter region with the largest area, and the emitter region can be realized. Electrode self-alignment, that is, without the need for photolithographic alignment process, the electrodes in the emission area can be completely covered on the emission area, achieving the largest electrode contact area, obtaining lower electrode contact resistance, and improving the operating frequency and operating frequency of the device. Efficiency; at the same time, it can simplify the manufacturing process of the device and reduce the difficulty of manufacturing high-frequency small-size devices.

FIG. 5 is a schematic cross-sectional view of a bipolar transistor according to yet another embodiment of the present invention.

According to an exemplary embodiment of the present invention, as shown in FIG. 5 , it includes: the present invention also provides a bipolar transistor obtained by the above manufacturing method, including: a substrate 1; The collector region 2 is formed on the substrate 1; the n-type lightly doped collector region 3 is formed on the n-type heavily doped sub-collector region 2; the p-type base region 4 is formed on the n-type lightly doped On the heterogeneous collector region 3, wherein, the n-type lightly doped collector region 3 and the p-type base region 4 form a mesa on the n-type heavily doped sub-collector region 2; the conductive mask layer 5 is formed on On the p-type base region 4; the insulating dielectric layer 11 is formed on the conductive mask layer, and an emission region window is formed on the conductive mask layer 5 and the insulating dielectric layer 11; the emission region 8 is formed in the emission region window, and emits A spacer is formed between the region 8, the conductive mask layer 5 and the insulating dielectric layer 11; the emitter electrode 1001 is formed on the emitter region 8; and the passivation layer 9 is formed on the n-type heavily doped sub-collector region 2. The insulating medium layer 11, the emitter electrode 1001 and the side wall; wherein, the p-type base region 4 is suitable for injecting an external current, and the emitter region 8 is suitable for generating electron current and forming an amplified current after passing through the p-type base region 4, n The heavily doped sub-collector region 2 is suitable for outputting the above-mentioned amplified current.

According to an embodiment of the present invention, the above-mentioned bipolar transistor further includes: an emitter external electrode 1004, suitable for grounding; a base electrode 1002, suitable for applying current to the p-type base region 4; a collector electrode 1003, suitable for supplying n A voltage is applied to the heavily doped sub-collector region 2.

FIG. 6 is a flowchart of a method for manufacturing a pin junction diode according to an embodiment of the present invention. 7( a ) to 7 ( i ) are schematic cross-sectional views of the fabrication process of a pin junction diode according to an embodiment of the present invention.

It should be noted that the embodiments of the present invention will be described by taking a GaN-based pin junction diode as an example.

According to an exemplary embodiment of the present invention, the present invention provides a method for manufacturing a pin junction diode, as shown in FIG. 6 , including steps S01-S10.

In step S01 , an n-type layer 02 and an i-type layer 03 are sequentially formed on a substrate 1 .

According to an embodiment of the present invention, as shown in FIG. 7( a ), an n-type layer 02 and an i-type layer 03 are sequentially formed on a substrate 1 . The substrate 1 includes one of the following: a Si substrate, a sapphire substrate, a SiC substrate, and a GaN free-standing substrate. The n-type layer 02 is GaN, InN, AlN and their ternary or quaternary alloys. The i-type layer 03 may be lightly doped GaN-based material, or GaN/InGaN, GaN/AlGaN multiple quantum well material.

In step S02 , a conductive mask layer 5 is formed on the i-type layer 03 .

According to an embodiment of the present invention, as shown in FIG. 7( b ), a conductive mask layer 5 is formed on the i-type layer 03 , and the conductive mask layer 5 forms an ohmic contact with the i-type layer 03 . The material of the conductive mask layer 5 is NiO, W, Cr, Mo; the thickness is 20-300nm, for example, 20nm, 50nm, 100nm, 200nm, 300nm.

In step S03, the conductive mask layer 5 is etched to form windows.

According to an embodiment of the present invention, as shown in FIG. 7( c ), a photoresist layer 6 is coated on the conductive mask layer 5 , and a patterned mask is formed after exposure. With the photoresist layer 6 as a mask, the conductive mask layer 5 is etched, the conductive mask layer 5 not covered by the photoresist layer 6 is removed, and the conductive mask layer 5 covered by the photoresist layer 6 is retained to form window. Wherein, the method of etching the conductive mask layer 5 includes dry etching or wet etching.

In step S04, an insulating dielectric layer 7 is formed on the conductive mask layer 5 and the window.

According to an embodiment of the present invention, referring to FIG. 7( d ), an insulating dielectric layer 7 is formed on the conductive mask layer 5 and the window. The pyrolysis temperature of the insulating dielectric layer 7 is greater than 1000°C; the insulating dielectric layer 7 can be made of SiO ₂ or SiN with a thickness of 10-100nm, for example, 10nm, 20nm, 50nm, 70nm, 100nm.

In step S05, the insulating dielectric layer 7 is etched to form spacers in the window.

According to an embodiment of the present invention, referring to FIG. 7( e ), the insulating dielectric layer 7 is etched by a dry method so that the insulating dielectric layer 7 forms sidewalls on the sidewalls of the conductive mask layer 5 .

In step S06, a p-type layer 08 is formed inside the window.

According to an embodiment of the present invention, as shown in FIG. 7( f ), the p-type layer 08 is formed in the window by metal organic compound chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The material of p-type layer 08 is GaN, InN, AlN and its ternary or quaternary alloy; A certain component can also be a gradient component. The doping impurity of the p-type layer 08 is a donor impurity, such as Si, Ge, and the p-type layer 08 can be a fixed certain doping concentration, or a multi-layer structure with different doping concentrations, or can be Gradient concentration doping in which the concentration in the thickness direction changes linearly.

In step S07, the conductive mask layer 5, the i-type layer 03 and the n-type layer 02 are etched to form a downwardly recessed mesa.

According to an embodiment of the present invention, referring to FIG. 7( g ), the conductive mask layer 5 , the i-type layer 03 and the n-type layer 02 are etched to form a downwardly recessed mesa. The method of etching the i-type layer 03 and the n-type layer 02 is dry etching. It should be noted that, after etching the conductive mask layer 5 , the i-type layer 03 and the n-type layer 02 to form a downwardly recessed mesa, the sidewall may or may not be removed.

In step S08 , a passivation layer 9 is formed on the substrate 1 , the conductive mask layer 5 , the sidewalls and the p-type layer 08 .

According to an embodiment of the present invention, referring to FIG. 7( h ), the spacer is removed, and a passivation layer 9 is formed on the substrate 1 , the conductive mask layer 5 , the i-type layer 03 and the p-type layer 08 .

In step S09 , a p-type electrode through hole is formed on the passivation layer 9 on the p-type layer 08 , and an n-type electrode through hole is formed on the passivation layer 9 on the conductive mask layer 5 .

In step S10, a p-type electrode 1005 is formed on the p-type electrode through hole, and an n-type electrode 1006 is formed on the n-type electrode through hole.

According to an embodiment of the present invention, as shown in FIG. The stacked layers of the metal alloy are filled in the p-type electrode through hole and the n-type electrode through hole to form the p-type electrode 1005 and the n-type electrode 1006 .

According to an embodiment of the present invention, the pin junction diode is manufactured by the above-mentioned manufacturing method, and the distance between the n-type electrode and the p-type layer can be controlled by controlling the thickness of the sidewall, so as to realize the minimum size of the distance between the n-type electrode and the p-type layer , can reduce the external parasitic parameters of the device, reduce the resistance of the device, and improve the operating frequency and efficiency of the device.

According to an exemplary embodiment of the present invention, as shown in FIG. 7(i), the pin junction diode provided by the present invention includes:

Substrate 1; n-type layer 02, formed on substrate 1; i-type layer 03, formed on n-type layer 02, i-type layer 03 and n-type layer 02 form a mesa on substrate 1; conductive mask layer 5. Formed on the i-type layer 03, a window is formed on the conductive mask layer 5; a p-type layer 08 is formed in the window, and a side wall is formed between the p-type layer 08 and the conductive mask layer 5; passivation The layer 9 is formed on the substrate 1, the conductive mask layer 5, the p-type layer 08 and the side wall; the p-type electrode 1005 is formed in the p-type electrode through hole, and the p-type electrode through hole is formed in the p-type layer 8 The n-type electrode 1006 is formed in the n-type electrode through hole, and the n-type electrode through hole is formed on the passivation layer 9 on the conductive mask layer 5 .

According to an embodiment of the present invention, the positions of the n-type layer 02 and the p-type layer 08 can be exchanged to form a pin junction diode with the p-type layer on the bottom and the n-type layer on the top.

According to an embodiment of the present invention, a pn junction diode not including the i-type layer 03 can be formed by using the above fabrication method.

According to an embodiment of the present invention, the n-type layer 02 and the p-type layer 08 may be GaN, InN, AlN and their ternary or quaternary alloys. The i-type layer 03 may be a lightly doped GaN-based material; or, the i-type layer 03 is a multiple quantum well material including GaN/InGaN or GaN/AlGaN.

According to the manufacturing method of the semiconductor device provided by the above-mentioned embodiments of the present invention, the bipolar transistor can be manufactured by using the manufacturing method, the distance between the base electrode and the emitter region can be controlled by controlling the thickness of the sidewall, and the distance between the base electrode and the emitter region can be realized. The minimum size of the distance between regions, and then the minimum size of the external base region, can reduce the external parasitic parameters of the device, reduce the resistance of the device, and improve the operating frequency and efficiency of the device.

According to the manufacturing method of the semiconductor device provided by the above-mentioned embodiments of the present invention, the bipolar transistor can be manufactured by using the manufacturing method, and the self-alignment of the base region electrode can be realized by using one sidewall process, which can simplify the manufacturing process of the device and reduce the high frequency Difficulty in making small-sized devices.

According to the manufacturing method of the semiconductor device provided by the above-mentioned embodiments of the present invention, using the manufacturing method to manufacture a bipolar transistor, since a side wall is formed between the emitter region and the base electrode, the emitter electrode on the emitter region can be realized. The largest size realizes the self-alignment of electrodes in the emission area, reduces the difficulty of manufacturing high-frequency small-size devices, and improves the yield and uniformity of devices.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention.

Claims (10)

1. A method for manufacturing a semiconductor device, comprising: forming a basic functional layer on the substrate (1); forming a conductive mask layer (5) on the basic functional layer; Etching the conductive mask layer (5) to form a downwardly recessed window on the conductive mask layer (5); forming an insulating dielectric layer (7) on the conductive mask layer (5) and the window; Etching the insulating dielectric layer (7) to form sidewalls in the window, the sidewalls are located on the sidewalls of the conductive mask layer (5); forming a carrier supply layer between the sidewalls; Etching the conductive mask layer (5) and the basic functional layer on the periphery of the window to form a downwardly recessed mesa; and A passivation layer (9) is formed on the mesa, the conductive mask layer (5), the carrier supply layer and the side wall. 2. The preparation method according to claim 1, characterized in that, The semiconductor device is a bipolar transistor, the window is an emission region window, and the carrier supply layer is an emission region (8); The forming of the basic functional layer on the substrate (1) includes: sequentially forming an n-type heavily doped sub-collector region (2) and an n-type lightly doped collector region ( 3), p-type base region (4); Etching the conductive mask layer (5) and the basic functional layer to form a downwardly recessed mesa includes: etching the conductive mask layer (5), the p-type base region (4), the The n-type lightly doped collector region (3) is used to form a downwardly recessed mesa. 3. The preparation method according to claim 2, further comprising: forming a dielectric mask layer (11) on the conductive mask layer (5); The etching the conductive mask layer (5) to form a window includes: etching the dielectric mask layer (11) and the conductive mask layer (5) to form the emission region window; Wherein, the sidewalls formed in the window of the emission area are located on the sidewalls of the conductive mask layer (5) and the dielectric mask layer (11). 4. The preparation method according to claim 2 or 3, further comprising: An emitter electrode through hole is formed on the passivation layer (9) on the emitter region (8), and an emitter electrode through hole is formed on the passivation layer (9) on the conductive mask layer (5). A base through hole, forming a collector through hole on the passivation layer (9) located on the n-type heavily doped sub-collector region (2); An emitter electrode (1001) is formed in the emitter electrode through hole, a base electrode (1002) is formed in the base through hole, and a collector electrode (1003) is formed in the collector through hole. 5. The manufacturing method according to claim 2 or 3, characterized in that, the material of the n-type heavily doped sub-collector region (2) is one or more selected from GaN and AlGaN, or SiGe, or SiC, or one or more selected from GaAs and InP; The thickness of the n-type heavily doped sub-collector region (2) is 100nm-20μm, The doping elements of the n-type heavily doped sub-collector region (2) include Si, Ge, N, P, and the doping concentration is 1×10 ¹⁹ cm ^-3 -1×10 ²⁰ cm ^-3 ; Preferably, the material of the n-type lightly doped collector region (3) is one or more selected from GaN and AlGaN, or SiGe, or SiC, or one or more selected from GaAs and InP various; The thickness of the n-type lightly doped collector region (3) is 50nm-20μm, The doping elements of the n-type lightly doped collector region (3) include Si, Ge, N, P, and the doping concentration is 1×10 ¹⁵ cm ^-3 -5×10 ¹⁷ cm ^-3 . 6. The manufacturing method according to claim 2 or 3, characterized in that, the material of the p-type base region (4) is selected from GaN, AlxGa1 _{- xN} , InxAl1 _{- xN} , One or more of In _x Al _y Ga _1-xy N and In _x Ga _1-x N, or one or more of Si and SiC, or SiGe, or one or more of GaAs and InP One or more, 0≤x≤0.45, The p-type base region (4) is a single component with constant element component content or a gradient component with element component content that changes linearly along the thickness direction; The thickness of the p-type base region (4) is 50nm-500nm; The doping elements of the p-type base region (4) include Si, Ge, B, Al, and the doping concentration is 2×10 ¹⁷ cm ^-3 -3×10 ²⁰ cm ^-3 , The p-type base region (4) is doped at a fixed concentration or doped at a gradient concentration in which the concentration changes linearly along the thickness direction; Preferably, the emission region (8) is formed by chemical vapor deposition of metal organic compounds, molecular beam epitaxy, pulsed laser deposition, hydride vapor phase epitaxy or physical vapor deposition; The material of the emission region (8) is one or more selected from GaN, Al _x Ga _1-x N, In _x Al _1-x N and In _x Aly Ga _{1-xy N} , or selected from One or more of Si and SiC, or SiGe, or one or more of GaAs and InP, 0≤x≤0.3; The emission area (8) is a single component with constant element component content or a gradual component with element component content that changes linearly along the thickness direction; The emission region (8) is n-type doped. 7. The manufacturing method according to claim 1, characterized in that, the formation method of the insulating dielectric layer (7) comprises one of vapor deposition, evaporation, atomic layer deposition, and sputtering; The material of the insulating dielectric layer (7) includes one or more of SiO ₂ , SiN _x , and polysilicon; The thickness of the insulating medium layer (7) is 10-100 nm. 8. The preparation method according to claim 1, characterized in that, The semiconductor device is a pin junction diode, and the carrier supply layer is a p-type layer (08); The forming of the basic functional layer on the substrate (1) includes: sequentially forming an n-type layer (02) and an i-type layer (03) on the substrate (1), The etching the conductive mask layer (5) and the basic functional layer to form a downwardly recessed mesa includes: etching the conductive mask layer (5), the i-type layer (03), The n-type layer (02) forms a downwardly recessed mesa. 9. A semiconductor device obtained by the manufacturing method according to any one of claims 1 to 7, wherein the semiconductor device is a bipolar transistor, comprising: Substrate(1); an n-type heavily doped sub-collector region (2), formed on the substrate (1); An n-type lightly doped collector region (3), formed on the n-type heavily doped sub-collector region (2); A p-type base region (4) is formed on the n-type lightly doped collector region (3), wherein the n-type lightly doped collector region (3) and the p-type base region ( 4) forming a mesa on the n-type heavily doped sub-collector region (2); a conductive mask layer (5), formed on the p-type base region (4), and an emission region window is formed on the conductive mask layer (5); an emission region (8), formed in the emission region window, and a side wall is formed between the emission region (8) and the conductive mask layer (5); and a passivation layer (9), formed on the n-type heavily doped sub-collector region (2), the conductive mask layer (5), the emitter region (8) and the side walls; Wherein, the p-type base region (4) is suitable for injecting an external current, and the emitter region (8) is suitable for generating electron current and forming an amplified current after passing through the p-type base region (4), and the n-type heavy The doped sub-collector region (2) is suitable for outputting said amplified current. 10. A semiconductor device obtained by the manufacturing method according to claim 8, wherein the semiconductor device is a pin junction diode, comprising: Substrate(1); an n-type layer (02), formed on the substrate (1); an i-type layer (03), formed on the n-type layer (02), the i-type layer (03) and the n-type layer (02) forming a mesa on the substrate (1); a conductive mask layer (5), formed on the i-type layer (03), and a window is formed on the conductive mask layer (5); a p-type layer (08), formed in the window, and a side wall is formed between the p-type layer (08) and the conductive mask layer (5); a passivation layer (9), formed on the substrate (1), the conductive mask layer (5), the p-type layer (08) and the sidewall; a p-type electrode (1005) formed in a p-type electrode through hole formed on the passivation layer (9) on the p-type layer (08); and An n-type electrode (1006) is formed in an n-type electrode through hole, and the n-type electrode through hole is formed on the passivation layer (9) on the conductive mask layer (5).

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