CN115470060A

CN115470060A - Hardware board card, test equipment, test system and synchronous test method

Info

Publication number: CN115470060A
Application number: CN202211210588.4A
Authority: CN
Inventors: 欧茂宇; 彭良宝; 邓伟炫; 张伟; 门洪达
Original assignee: Shenzhen Tianmicro Electronic Co ltd
Current assignee: Shenzhen Tianmicro Electronic Co ltd
Priority date: 2022-09-30
Filing date: 2022-09-30
Publication date: 2022-12-13

Abstract

The application relates to a hardware board card, include: the receiving and transmitting port group comprises an input port for receiving a preceding stage indication signal and an output port for outputting a cascade completion signal; the main control chip is used for testing the device to be tested and generating a test completion signal after the test is completed; the synchronous port is connected with the main control chip and used for sending or receiving a synchronous signal; the logic circuit is respectively connected with the main control chip, the input port and the output port and is used for generating a cascade completion signal when receiving a test completion signal and a preceding stage indication signal from the input port; the hardware board card is used for selecting to output a cascade completion signal through the output port or output a synchronous signal through the synchronous port after generating the cascade completion signal, wherein the synchronous signal is generated by the main control chip in response to the cascade completion signal. The hardware board card can realize that a plurality of hardware board cards automatically and synchronously execute the test task.

Description

Hardware board card, test equipment, test system and synchronous test method

Technical Field

The present application relates to the field of semiconductor testing technologies, and in particular, to a hardware board, a test device, a test system, and a synchronous test method.

Background

As semiconductor test technology develops, there are various types of test equipment. The hardware testing equipment is divided into high-end equipment and low-end equipment according to the number of available hardware resources on the testing equipment and the research and development cost, and the hardware board card is a core component of the testing equipment regardless of the testing equipment. A plurality of hardware resources are arranged in one hardware board card, the number of the hardware board cards of the testing equipment is increased, and accordingly, the number of the hardware resources can be increased, so that the performance of the testing equipment is improved, and different testing requirements can be flexibly met.

When the test equipment performs test operation, there is a situation that one hardware board tests one semiconductor device, and there is also a situation that a plurality of hardware boards test the same semiconductor device because the number of pins of the semiconductor device to be tested is large and the number of channels is large. When a plurality of hardware boards execute test tasks together, the hardware boards are difficult to test synchronously because the execution speed of the test tasks is divided into different speeds.

Disclosure of Invention

In view of the above, it is necessary to provide a hardware board, a test device, a test system and a synchronous test method for solving the above technical problems.

In a first aspect, the present application provides a hardware board, including:

a receive-transmit port group including an input port for receiving a preceding stage indication signal and an output port for outputting a cascade completion signal;

the main control chip is used for testing the device to be tested and generating a test completion signal after the test is completed;

the synchronous port is connected with the main control chip and used for sending or receiving a synchronous signal;

a logic circuit, connected to the main control chip, the input port, and the output port, respectively, and configured to generate the cascade complete signal when receiving the test complete signal and the preceding stage indication signal from the input port;

the hardware board card is used for selecting to output the cascade connection completion signal through the output port or output the synchronous signal through the synchronous port after the cascade connection completion signal is generated, wherein the synchronous signal is generated by the main control chip in response to the cascade connection completion signal.

In one embodiment, the hardware board includes two transceiver port groups and two logic circuits, and the hardware board is configured to adopt one transceiver port group and a corresponding logic circuit in one test.

In one embodiment, the logic circuit is an and circuit, two input ends of the and circuit are respectively connected with the input port and the main control chip, and an output end of the and circuit is connected with the output port.

In a second aspect, the present application further provides a testing apparatus, comprising:

the n hardware board cards are used for synchronously testing the devices to be tested;

the controller module is respectively connected with each hardware board card and is used for respectively sending a test task to each hardware board card and sending a transmission trigger signal, wherein the test task comprises at least one test item;

wherein, n the hardware integrated circuit board includes:

the input port of the first hardware board card is connected with the controller module to receive the transmission trigger signal sent by the controller module as the preceding stage indication signal;

the nth hardware board card is used for selecting the synchronous signal to be output through the synchronous port after the cascade connection completion signal is generated, and the synchronous signal is used for indicating the execution of a command for synchronously starting the next test item;

the input port of the mth hardware board card in the intermediate hardware board cards is connected with the output port of the (m-1) th hardware board card, and m is more than 1 and less than n;

the synchronous ports of the n hardware board cards are connected with each other, the input port of the nth hardware board card is connected with the output port of the (n-1) th hardware board card in the intermediate hardware board cards, the first hardware board card and each intermediate hardware board card are used for outputting the cascade completion signal through the output port after the cascade completion signal is generated, and the nth hardware board card and each intermediate hardware board card are used for taking the cascade completion signal received by the input port as the preceding stage indication signal.

In one embodiment, when the hardware board includes two transceiver port groups, the two transceiver port groups are respectively a first port group and a second port group;

the input port of the first port group of the mth hardware board card is connected with the output port of the first port group of the m-1 th hardware board card, and the output port of the first port group of the mth hardware board card is connected with the input port of the first port group of the m +1 th hardware board card;

the input port of the second port group of the mth hardware board is connected with the output port of the second port group of the m +1 th hardware board, and the output port of the second port group of the mth hardware board is connected with the input port of the second port group of the m-1 th hardware board;

the controller module is configured to select one of the first port group and the second port group to transmit the cascade completion signal.

In one embodiment, the input ports of the first port group of the first hardware board card are connected to the output ports of the first port group of the nth hardware board card, and the output ports of the second port group of the first hardware board card are connected to the input ports of the second port group of the nth hardware board card.

In a third aspect, the present application further provides a test system, including:

the test equipment is as described above;

a device under test configured with a plurality of pins;

the interface circuits are respectively connected with the hardware boards of the test equipment in a one-to-one correspondence mode, each interface circuit is respectively configured with a plurality of test channels, and the test channels are respectively connected with the pins of the device to be tested in a one-to-one correspondence mode.

In a fourth aspect, the present application further provides a synchronous testing method, where the method is applied to the controller module in the above testing apparatus, and the method includes:

respectively sending the test tasks to the n hardware board cards so that the hardware board cards can independently test the devices to be tested at the same time;

sending the transmission trigger signal to a first hardware board card of the n hardware board cards;

and sending a synchronization end signal to the nth hardware board card, wherein the synchronization end signal is used for indicating the nth hardware board card to output the synchronization signal through the synchronization port after the cascade completion signal is generated.

In a fifth aspect, the present application further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the above method when executing the computer program.

In a sixth aspect, the present application also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the above method.

The hardware board card comprises a receiving and transmitting port group comprising an input port and an output port, a main control chip, a synchronous port and a logic circuit. The input port is used for receiving a preceding stage indication signal; the main control chip is used for testing the device to be tested and generating a test completion signal after the test is completed; the logic circuit is respectively connected with the input port and the main control chip and is used for generating a cascade completion signal after the received preceding stage indication signal and the test completion signal are operated. In addition, the logic circuit is also connected with an output port for outputting the cascade connection completion signal, and the main control chip is also connected with a synchronous port for sending or receiving the synchronous signal. After the cascade completion signal is generated according to the function requirement, the hardware board card can select to output the cascade completion signal through an output port connected with the logic circuit, or output the synchronous signal through a synchronous port connected with the main control chip after the main control chip generates the synchronous signal in response to the cascade completion signal. When one hardware board card sends a synchronous signal, other hardware board cards which jointly execute the test task can receive the synchronous signal through the synchronous port, so that the hardware board cards automatically and synchronously execute the test task, the test result has higher reliability, stability and accuracy, and the time and labor cost for manually adjusting the test progress of the hardware board cards can be reduced.

Drawings

FIG. 1 is one of the structures of a hardware board in one embodiment;

FIG. 2 is a second block diagram of a hardware board of an embodiment;

FIG. 3 is a third block diagram of a hardware board of an embodiment;

FIG. 4 is a timing diagram illustrating internal signals of the hardware board of one embodiment;

FIG. 5 is one of the block diagrams of the test apparatus in one embodiment;

FIG. 6 is a second block diagram of the test equipment in one embodiment;

FIG. 7 is a third block diagram of the test apparatus in one embodiment;

FIG. 8 is one of the block diagrams of a test system in one embodiment;

FIG. 9 is a flow diagram of a method for synchronous testing in one embodiment;

FIG. 10 is a diagram showing an internal structure of a computer device according to an embodiment.

Element number description:

hardware board card: 100, respectively; input port of the transceiving port group: 111; output port of the transceiving port group: 112, a first electrode; a main control chip: 120 of a solvent; a synchronous port: 130, 130; a logic circuit: 140; and gate circuit: 141, a solvent; output of and circuit: 142; input terminal of and circuit: 143; a controller module: 150; and (3) testing equipment: 160; a device under test 170; pin of the device to be tested: 171; an interface circuit: 180; test channel of interface circuit: 181; the test system comprises: 190.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, the first port group may be referred to as a second port group, and the second port group may also be referred to as a first port group, without departing from the scope of the present application. The first port group and the second port group are both port groups, but are not the same port group. Similarly, the first hardware board, the mth hardware board, and the nth hardware board are all hardware boards, but they are not the same hardware board.

It is to be understood that "connected" in the following embodiments is to be understood as "electrically connected", "communicatively connected", and the like, if the connected circuits, modules, and the like have electrical signals or data transmission therebetween.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

The embodiment of the application provides a hardware board card applied to the technical field of semiconductor testing. Fig. 1 is a structural diagram of a hardware board in an embodiment, and referring to fig. 1, in the embodiment, a hardware board 100 includes a transceiver port group, a main control chip 120, a synchronization port 130, and a logic circuit 140.

And a transceiver port group including an input port 111 for receiving a preceding stage indication signal, and an output port 112 for outputting a cascade completion signal.

The main control chip 120 is configured to test the device to be tested, and generate a test completion signal after the test is completed.

A synchronization port 130 connected to the main control chip 120, for sending or receiving a synchronization signal.

A logic circuit 140, respectively connected to the main control chip 120, the input port 111, and the output port 112, and configured to generate the cascade complete signal when receiving the test complete signal and the previous stage indication signal from the input port 111.

The hardware board 100 is configured to select to output the cascade completion signal through the output port 112 or output the synchronization signal through the synchronization port 130 after generating the cascade completion signal, where the synchronization signal is generated by the main control chip 120 in response to the cascade completion signal.

In this embodiment, the logic circuit 140 is respectively connected to the input port 111 and the main control chip 120, and configured to generate a cascade complete signal after computing the received previous stage indication signal and the test complete signal. According to the function requirement, after the cascade completion signal is generated, the hardware board 100 may select to output the cascade completion signal through the output port 112 connected to the logic circuit 140, or output the synchronization signal through the synchronization port 130 connected to the main control chip 120 after the main control chip 120 generates the synchronization signal in response to the cascade completion signal. When one hardware board 100 sends a synchronization signal, other hardware boards 100 that execute a test task together can receive the synchronization signal through the synchronization port 130, thereby implementing that each hardware board 100 automatically and synchronously executes the test task.

In one embodiment, fig. 2 is a second structural diagram of a hardware board in an embodiment, and referring to fig. 2, the hardware board 100 includes two transceiver port sets and two logic circuits 140, respectively, and the hardware board 100 is configured to adopt one transceiver port set and one corresponding logic circuit 140 in one test.

In this embodiment, one transceiving port group corresponds to one logic circuit 140, the input port 111 of one transceiving port group and the output port 112 of another transceiving port group may be located on the same side of the hardware board 100, and accordingly, the output port 112 thereof and the input port 111 of another transceiving port group may be located on the other side of the hardware board 100. Based on the two transceiving port groups with different directions, the hardware board 100 supports bidirectional signal receiving and transmitting, that is, signals can be transmitted from left to right or from right to left, and either one of the two is selected and defined by a user according to needs, so that the flexibility of the hardware board 100 in executing test tasks is enhanced.

In one embodiment, fig. 3 is a third structural diagram of the hardware board in an embodiment, fig. 4 is a timing diagram of internal signals of the hardware board in an embodiment, referring to fig. 3 and fig. 4, the logic circuit 140 is an and circuit 141, two input terminals 143 of the and circuit 141 are respectively connected to the input port 111 and the main control chip 120, and an output terminal 142 of the and circuit 141 is connected to the output port 112.

In this embodiment, when the input port 111 receives the previous stage indication signal and the main control chip 120 generates the test completion signal, that is, both the input terminals 143 of the and circuit 141 receive the high level signal, the output terminal 142 of the and circuit 141 outputs the cascade completion signal which is also the high level signal after the operation.

The application also provides a test device. Fig. 5 is a structural diagram of a test apparatus in an embodiment, and referring to fig. 5, in this embodiment, the test apparatus 160 includes n hardware boards 100 and a controller module 150 as described above.

The n hardware board cards 100 are used for synchronously testing the device to be tested.

The controller module 150 is connected to each of the hardware boards 100, and configured to send a test task to each of the hardware boards 100, and send a transmission trigger signal, where the test task includes at least one test item.

The n hardware boards 100 include a first hardware board 100, an nth hardware board 100, and a plurality of intermediate hardware boards 100.

The input port 111 of the first hardware board 100 is connected to the controller module 150 to receive the transfer trigger signal sent by the controller module 150 as the pre-stage indication signal.

The nth hardware board 100 is configured to select the synchronization signal output through the synchronization port 130 after the cascade completion signal is generated, where the synchronization signal is used to instruct execution of an instruction for synchronizing a next test item.

The input port 111 of the mth hardware board 100 of the intermediate hardware boards 100 is connected to the output port 112 of the m-1 th hardware board 100, where m is greater than 1 and less than n.

The synchronization ports 130 of the n hardware boards 100 are connected to each other, the input port 111 of the nth hardware board 100 is connected to the output port 112 of the (n-1) th hardware board 100 in the intermediate hardware boards 100, the first hardware board 100 and each intermediate hardware board 100 are configured to output the cascade completion signal through the output port 112 after generating the cascade completion signal, and the nth hardware board 100 and each intermediate hardware board 100 are configured to use the cascade completion signal received by the input port 111 as the preceding stage indication signal.

In this embodiment, the controller module 150 controls n hardware boards 100 respectively connected to the controller module to synchronously test the devices to be tested. The n hardware boards 100 are connected in series, and the first hardware board 100 refers to the hardware board 100 that is designated by the user as the first option and outputs the cascade completion signal through the output port 112. According to the output direction and the output sequence of the cascade connection completion signals, the hardware board cards 100 are sequentially defined as a first hardware board card 100, a second hardware board card 100, a third hardware board card 100 \8230- \8230, an mth hardware board card 100 \8230- \8230, an m is more than 1 and less than n, and the second hardware board card 100 to the nth-1 hardware board card 100 are intermediate hardware board cards 100. The nth hardware board 100 refers to the last hardware board 100 designated by the user to receive the cascade completion signal as the preceding stage indication signal, and is also designated as the hardware board 100 to select the synchronization signal output through the synchronization port 130. It should be noted that a user may designate any hardware board 100 as the first hardware board 100, and may also designate any hardware board 100 as the nth hardware board 100, and accordingly, any designated nth hardware board 100 may select to output a synchronization signal through the synchronization port 130 after generating a cascade completion signal.

Specifically, the controller module 150 sends a test task including at least one test item to each hardware board 100, so that the main control chip 120 of each hardware board 100 simultaneously performs independent tests on the devices to be tested after receiving the test task, and sends a transfer trigger signal to the input port 111 of any specified first hardware board 100. After the first hardware board 100 is to be tested and the main control chip 120 generates the test completion signal, the input end of the logic circuit 140 of the first hardware board 100 receives the transfer trigger signal and the test completion signal as the preceding stage indication signal, respectively, so as to generate the cascade completion signal, and selects the output port 112 of the first hardware board 100 to output the cascade completion signal. Further, the input port 111 of the second hardware board 100 receives the cascade completion signal as the preceding stage instruction signal, and performs the same operation and signal output process as the first hardware board 100. The working principle of the middle hardware board 100 is the same until the n-1 th hardware board 100 selects to output the cascade completion signal through the output port 112. The input port 111 of the nth hardware board 100 receives the cascade completion signal output from the output port 112 of the nth-1 hardware board 100 as the preceding stage indication signal, and after the simultaneous independent test is completed and the main control chip 120 generates the test completion signal, the logic circuit 140 of the nth hardware board 100 operates to generate the cascade completion signal, and at this time, it can be determined that all the hardware boards 100 used in the test item have completed the current test work. Further, the main control chip 120 generates a synchronization signal indicating an instruction to execute a synchronization start of the next test item in response to the cascade completion signal, and then the nth hardware board 100 selects to output the synchronization signal through the synchronization port 130.

In this embodiment, the synchronization ports 130 of the hardware boards 100 are connected to each other, that is, the n hardware boards 100 are also connected in parallel, when an arbitrary n-th hardware board 100 selects to output a synchronization signal through the synchronization port 130 after a test of one test item is completed, the synchronization signal can be received by the synchronization port 130 by the other n-1 hardware boards 100 that commonly execute a test task, and after the synchronization signal is determined by the main control chip 120, an instruction for synchronously starting the next test item is immediately executed, so as to implement the n hardware boards 100 to synchronously test the device to be tested.

It can be understood that each hardware board 100 can independently execute the operation of issuing the synchronization signal when executing the test task, and therefore, when a time deviation occurs between the hardware boards 100 in the process of executing the test task together, the scheme of the embodiment may also be used to perform adjustment to implement the synchronization test. Further, the test equipment 160 in this embodiment also allows the number of the hardware boards 100 and the number of the hardware resources disposed on the hardware boards 100 to be increased, so that the test equipment 160 can coordinate to test more semiconductor devices, and flexibly meet different test requirements. Specifically, the test equipment 160 may include more than n hardware boards 100, and only n of the hardware boards 100 may be enabled during testing. For example, 2n hardware boards 100 are arranged in total, only n of the hardware boards 100 are enabled to test a first semiconductor device, the remaining n hardware boards 100 may be selected not to be enabled, or may be selected to test a second semiconductor device synchronously, and a plurality of semiconductor devices which are tested synchronously may occupy different numbers of hardware boards 100. In this embodiment, the connection relationship between the hardware boards 100 is utilized to realize the common synchronous test of the hardware boards 100, and the number of the hardware boards 100 is allowed to be increased or decreased according to the requirement, so the test equipment 160 in this embodiment further has the characteristics of simple structure, easy implementation, strong operability, high expandability, and low cost.

In one embodiment, fig. 6 is a second structural diagram of the test equipment in an embodiment, and referring to fig. 6, when the hardware board 100 includes two transceiver port groups, the two transceiver port groups are a first port group and a second port group respectively. The input port 111 of the first port group of the mth hardware board 100 is connected to the output port 112 of the first port group of the m-1 th hardware board 100, and the output port 112 of the first port group of the mth hardware board 100 is connected to the input port 111 of the first port group of the m +1 th hardware board 100. The input ports 111 of the second port group of the mth hardware board 100 are connected to the output ports 112 of the second port group of the m +1 th hardware board 100, and the output ports 112 of the second port group of the mth hardware board 100 are connected to the input ports 111 of the second port group of the m-1 th hardware board 100. The controller module 150 is configured to select one of the first port group and the second port group to transmit the cascade completion signal.

In this embodiment, based on the characteristic that the hardware board 100 may have two transceiving port groups in different directions and support bidirectional receiving and sending of signals, a user may arbitrarily select a direction in which a signal is transmitted between the hardware boards 100 through the controller module 150, that is, may select a left-to-right transmission or a right-to-left transmission of a signal between the hardware boards 100. One transfer direction corresponds to the transceiver port groups in the same direction of each hardware board 100, and the transceiver port groups in different directions of each hardware board 100 are connected respectively, but only the transceiver port group in one direction is in a working state according to the signal transfer direction when a test task is executed.

In one embodiment, fig. 7 is a third structural diagram of the test equipment in an embodiment, and referring to fig. 7, the input port 111 of the first port group of the first hardware board 100 is connected to the output port 112 of the first port group of the nth hardware board 100, and the output port 112 of the second port group of the first hardware board 100 is connected to the input port 111 of the second port group of the nth hardware board 100.

In this embodiment, the first hardware board 100 and the nth hardware board 100 may be connected, so that the hardware boards 100 form a closed loop in a serial connection manner. Based on this connection manner, no matter which hardware board 100 is used as the first hardware board 100, it can be ensured that signals can be transmitted among all the hardware boards 100.

The present application further provides a test system, fig. 8 is one of the structural diagrams of the test system in an embodiment, and referring to fig. 8, a test system 190 includes the test equipment 160, the devices under test 170, and a plurality of interface circuits 180 as described above.

The device under test 170 is configured with a plurality of pins 171.

The plurality of interface circuits 180 are respectively connected to the plurality of hardware boards 100 of the testing apparatus 160 in a one-to-one correspondence manner, each interface circuit 180 is configured with a plurality of testing channels 181, and the plurality of testing channels 181 are respectively connected to the plurality of pins 171 of the device under test 170 in a one-to-one correspondence manner.

In this embodiment, the test equipment 160 including the hardware board 100 establishes a connection with the device under test 170 through the interface circuit 180, so as to perform a test task on the device under test 170.

The present application further provides a synchronous testing method, which is applied to the controller module 150 in the testing apparatus 160, and fig. 9 is a flowchart of the synchronous testing method in an embodiment, referring to fig. 8 and 9, the method includes:

step 1000, the test tasks are respectively sent to the n hardware boards 100, so that each hardware board 100 simultaneously and independently tests the device under test 170.

Step 2000, sending the transfer trigger signal to a first hardware board 100 of the n hardware boards 100.

Step 3000, sending a synchronization end signal to the nth hardware board 100, where the synchronization end signal is used to instruct the nth hardware board 100 to output the synchronization signal through the synchronization port 130 after the cascade completion signal is generated.

In this embodiment, after the controller module 150 sends the test task to the n hardware boards 100, each hardware board 100 simultaneously and independently starts the test, and sequentially receives the cascade completion signal output by the previous hardware board 100 according to the signal transmission direction, and generates the cascade completion signal as the preceding stage indication signal received by the next hardware board 100 on the premise of completing the independent test. The first hardware board 100 receives a transmission trigger signal sent by the controller module 150 as a preceding stage indication signal. Meanwhile, the controller module 150 sends a synchronization completion signal to the nth hardware board 100, so that the nth hardware board 100 selects to output a synchronization signal through the synchronization port 130 after generating the cascade completion signal. Furthermore, the other n-1 hardware boards 100 that execute the testing task together receive the synchronization signal and execute the instruction of starting the next testing item synchronously, so that the n hardware boards 100 test the device to be tested 170 synchronously, and the testing result has higher reliability, stability and accuracy.

It should be understood that, although the steps in the flowchart of fig. 9 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 9 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

Fig. 10 is an internal structure diagram of a computer device in an embodiment, and referring to fig. 10, the computer device includes a memory and a processor, where the memory stores a computer program, and the processor implements the steps of the synchronization test method when executing the computer program.

Those skilled in the art will appreciate that the architecture shown in fig. 10 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as a particular computing device may include more or less components than those shown in fig. 10, or may combine certain components, or have a different arrangement of components.

The present application further provides a computer-readable storage medium, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of the above synchronization test method.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), magnetic Random Access Memory (MRAM), ferroelectric Random Access Memory (FRAM), phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.

All possible combinations of the technical features in the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A hardware board card, comprising:

the hardware board card is used for selecting to output the cascade connection completion signal through the output port or output the synchronous signal through the synchronous port after the cascade connection completion signal is generated, and the synchronous signal is generated by the main control chip in response to the cascade connection completion signal.

2. The hardware board of claim 1, wherein the hardware board comprises two transceiver port sets and two logic circuits, respectively, and wherein the hardware board is configured to employ one transceiver port set and a corresponding one logic circuit in a test.

3. The hardware board of any of claims 1 to 2, wherein the logic circuit is an and circuit, two input terminals of the and circuit are respectively connected to the input port and the main control chip, and an output terminal of the and circuit is connected to the output port.

4. A test apparatus, comprising:

n hardware boards as claimed in any one of claims 1 to 3, the n hardware boards being adapted to test devices under test simultaneously;

wherein, n the hardware integrated circuit board includes:

5. The test apparatus of claim 4,

when the hardware board card comprises two receiving and transmitting port groups, the two receiving and transmitting port groups are respectively a first port group and a second port group;

the input port of the first port group of the mth hardware board is connected with the output port of the first port group of the m-1 th hardware board, and the output port of the first port group of the mth hardware board is connected with the input port of the first port group of the m +1 th hardware board;

the input port of the second port group of the mth hardware board card is connected with the output port of the second port group of the (m + 1) th hardware board card, and the output port of the second port group of the mth hardware board card is connected with the input port of the second port group of the m-1 th hardware board card;

6. The test equipment of claim 5, wherein the input ports of the first port set of the first hardware board are connected with the output ports of the first port set of the nth hardware board, and the output ports of the second port set of the first hardware board are connected with the input ports of the second port set of the nth hardware board.

7. A test system, comprising:

the test device of any one of claims 4 to 6;

a device under test configured with a plurality of pins;

8. A synchronous testing method, which is applied to the controller module in the testing equipment according to any one of claims 4 to 7, and comprises the following steps:

sending the transfer trigger signal to a first hardware board card of the n hardware board cards;

and sending a synchronization end signal to the nth hardware board, wherein the synchronization end signal is used for indicating the nth hardware board to output the synchronization signal through the synchronization port after the cascade completion signal is generated.

9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of claim 8 when executing the computer program.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method as claimed in claim 8.