CN115458639B - LED chip and preparation method thereof - Google Patents

Abstract

The invention provides an LED chip and a preparation method thereof, wherein the method comprises the following steps: (1) preparing a GaAs epitaxial wafer; (2) thinning the GaAs substrate; (3) growing a transparent conductive layer on the P-type epitaxial layer; (4) Attaching a patch with electrode holes to the transparent conductive layer; (5) evaporating a first metal layer on the patch to form a P electrode; (6) Evaporating a second metal layer on the N-type epitaxial layer to form an N electrode; (7) Taking down the patch, and annealing to enable the P electrode and the N electrode to form ohmic contact; (8) cutting to form a plurality of LED chips. Compared with the prior art, the method reduces the process steps of photoetching, corrosion and the like, greatly reduces the process flow and shortens the process cycle; meanwhile, the use of various photoetching and corrosive liquids and scrapping and returning work caused by abnormality caused by unstable photoetching and corrosive liquids are reduced, the preparation cost of the LED chip is reduced, and the process is simple and convenient and is suitable for large-scale production.

Description

LED chip and preparation method thereof

Technical Field

The present invention relates to the technical field of chip processing, and in particular to an LED chip and a preparation method thereof.

Background Art

LED is a new lighting source in the 21st century. At the same brightness, the power consumption of semiconductor lamps is only 1/10 of that of ordinary incandescent lamps, but the life span can be extended by 100 times. LED devices are cold light sources with high light efficiency, low operating voltage, low power consumption, small size, flat packaging, easy development of thin and light products, strong structure and long life. The light source itself does not contain harmful substances such as mercury and lead, no infrared and ultraviolet pollution, and will not cause pollution to the outside world during production and use. Therefore, semiconductor lamps have the characteristics of energy saving, environmental protection, and long life.

Gallium arsenide, chemical formula GaAs, is a black-gray solid with a melting point of 1238°C. It can exist stably in the air below 600°C and is not corroded by non-oxidizing acids. Gallium arsenide is an important semiconductor material belonging to the III-V group of compound semiconductors. GaAs LED positive polarity chip is currently a small-sized, highly popular and low-priced LED chip.

In the prior art, in the preparation process of GaAs LED upright positive polarity chips, there are many process steps (photolithography → etching → evaporation → photolithography → evaporation → etching → annealing → thinning → evaporation → annealing → cutting), which leads to a long cycle, low final yield and high cost. At the same time, in the process of photolithography and etching, the use of photolithography and etching liquid and the instability of photolithography and etching liquid are prone to abnormalities, resulting in scrapping and rework.

Summary of the invention

In view of the shortcomings of the prior art, the purpose of the present invention is to provide an LED chip and a preparation method thereof, aiming to solve the technical problems of long processing cycle and low yield in the prior art.

In order to achieve the above object, the present invention is implemented by the following technical solution: a method for preparing an LED chip, comprising the following steps:

(1) preparing a GaAs epitaxial wafer, wherein the GaAs epitaxial wafer comprises a GaAs substrate, an N-type epitaxial layer, an MQW light-emitting layer, and a P-type epitaxial layer stacked in sequence;

(2) thinning the GaAs substrate;

(3) growing a transparent conductive layer on the P-type epitaxial layer of the GaAs epitaxial wafer;

(4) attaching a patch with electrode holes to the transparent conductive layer;

(5) evaporating a first metal layer on the patch so that the first metal layer contacts the transparent conductive layer through the electrode hole to form a P electrode;

(6) evaporating a second metal layer on a side of the GaAs epitaxial GaAs substrate away from the N-type epitaxial layer to form an N-electrode;

(7) removing the patch and performing annealing so that the P electrode and the N electrode form ohmic contacts with the P-type epitaxial layer and the N-type epitaxial layer respectively;

(8) Cutting the annealed GaAs epitaxial wafer into a plurality of LED chips.

Compared with the prior art, the invention has the following beneficial effects: by thinning the GaAs substrate of the GaAs epitaxial wafer first, after the evaporation of the first metal layer of the P-type epitaxial layer is completed, the thinned GaAs substrate can be directly flipped over to expose the thinned GaAs substrate, and the second metal layer can be evaporated, and then a unified annealing treatment is performed, and the ohmic contact of the P electrode and the N electrode is completed at the same time, which is equivalent to reducing the annealing treatment of the primary electrode, simplifying the process steps, and reducing the production cycle and production cost; at the same time, by arranging a reusable patch with electrode holes on the P-type epitaxial layer to quickly obtain the required P electrode pattern, compared with the prior art, the process steps such as photolithography and corrosion are reduced, the process flow is greatly reduced, the process cycle is shortened, and the production efficiency is greatly improved; at the same time, the use of various photolithography and etching solutions and the abnormalities caused by the instability of photolithography and etching solutions, which lead to scrapping and rework operations, reduce the preparation cost of LED chips, and the process is simple and suitable for large-scale production; in addition, by growing a transparent conductive layer on one side of the P-type epitaxial layer of the GaAs epitaxial wafer, because it has both light-transmitting and conductive properties, the current expansion of the entire surface can be achieved, the brightness of the LED chip is effectively improved, and the operating voltage is reduced.

Furthermore, in step (2), the thickness of the GaAs epitaxial wafer after thinning is 140 to 220 um.

Furthermore, in step ( ₃ ), the material of the transparent conductive layer is selected from one or more of ITO ( _In2O3 : _SnO2 ), IZO (ZnO: In), ATO ( _SnO2 : Sb), AZO (ZnO: Al), GZO (ZnO: Ga) or FTO ( _SnO2 : F).

Furthermore, in step (3), the method specifically comprises:

Performing evaporation by electron beam evaporation to form the transparent conductive layer;

Wherein, the transparent conductive layer is an ITO film, and the thickness of the ITO film is During the electron beam evaporation process, the temperature is 200-400°C and the evaporation rate is The oxygen flow rate is 5 to 20 sccm.

Furthermore, in step (4), the thickness of the patch is 5 to 10 μm, and the electrode holes are conical holes.

Furthermore, in step (5), the thickness of the first metal layer is 1.4 to 3 um.

Furthermore, in step (5), the method specifically comprises:

Performing evaporation by electron beam evaporation to form the first metal layer;

Wherein, during the electron beam evaporation process, the temperature is 200-600°C and the evaporation rate is

Furthermore, in step (6), the thickness of the second metal layer is 0.2-0.6 um.

Furthermore, in step (7), the annealing temperature is 200-500°C.

Another aspect of the present invention provides an LED chip, wherein the LED chip is obtained by the method for preparing the LED chip provided by the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of an LED chip in the present invention;

FIG2 is a schematic diagram of the product structure after steps (1) to (3) in the first embodiment of the present invention;

FIG3 is a schematic diagram of the product structure after steps (4) to (6) in the first embodiment of the present invention;

FIG4 is a schematic diagram of the product structure after step (7) in the first embodiment of the present invention;

Description of main component symbols:

N electrode 10 GaAs substrate 20 N-type epitaxial layer 30 MQW layer 40 P-type epitaxial layer 50 Transparent conductive layer 60 First metal layer 70 Upper metal layer 71 P electrode 72 Patches 80

The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings.

DETAILED DESCRIPTION

In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and/or" used herein includes any and all combinations of one or more related listed items.

Based on this, the first embodiment of the present invention provides a method for preparing an LED chip, comprising the following steps:

(1) A GaAs epitaxial wafer is prepared, wherein the GaAs epitaxial wafer includes a GaAs substrate 20, an N-type epitaxial layer 30, an MQW light-emitting layer 40, and a P-type epitaxial layer 50 stacked in sequence.

Specifically, in this embodiment, the MQW layer 40 is a Multiple Quantum Well layer, i.e., a multi-quantum well layer. A multi-quantum well refers to a system in which multiple quantum wells are combined together. In terms of material structure and growth process, there is no substantial difference between a multi-quantum well and a superlattice, except that the superlattice barrier layer is relatively thin, and the coupling between the potential wells is relatively strong, forming a microstrip; while the barrier layer between the multi-quantum wells is thick, and there is basically no tunneling coupling, and no microstrip is formed. The multi-quantum well structure is mainly used for its optical properties.

(2) The GaAs substrate 20 is thinned.

For ease of understanding, a substrate is a wafer made of semiconductor single crystal material. The substrate can directly enter the wafer manufacturing process to produce semiconductor devices, or it can be processed by epitaxy to produce epitaxial wafers. Epitaxy refers to the process of growing a new single crystal on a single crystal substrate that has been carefully processed by cutting, grinding, and polishing. The new single crystal can be the same material as the substrate, or a different material (homoepitaxial or heteroepitaxial). Since the new single crystal layer grows along the substrate crystal phase, it is called an epitaxial layer (usually a few microns thick, taking silicon as an example: the meaning of silicon epitaxial growth is to grow a layer of crystal with good lattice structure integrity with the same resistivity and thickness as the substrate on a silicon single crystal substrate with a certain crystal orientation), and the substrate with an epitaxial layer is called an epitaxial wafer (epitaxial wafer = epitaxial layer + substrate).

Specifically, in this step, the thinning operation is based on grinding the epitaxial wafer with a sanding wheel, and the thickness of the GaAs epitaxial wafer after thinning is 140-220 um. Preferably, in this embodiment, the thickness of the GaAs epitaxial wafer is 180 um.

It is easy to understand that when the IC circuit is powered on, the chip will experience thermal effects due to the resistance of the chip substrate material and the interconnected metal layer. During the operation of the chip, the thermal effect will cause internal stress on the back of the chip. The continuous generation of heat in the chip will aggravate the thermal differences between the metal layers, and the stress in the chip will further increase. One of the main reasons for chip damage and breakage is the increase in internal stress. Therefore, through the thinning process, the chip resistance can be reduced, the chip's thermal diffusion efficiency can be improved, and the chip damage rate can be minimized, thereby improving the reliability and yield of the integrated circuit.

(3) A transparent conductive layer 60 is grown on the P-type epitaxial layer 50 of the GaAs epitaxial wafer.

Specifically, in this step, the transparent conductive layer 60 can be grown by a method selected from evaporation, magnetron sputtering or arc ion plating. In this embodiment, the material of the transparent conductive layer 60 is selected from one or more of ITO (In ₂ O ₃ :SnO ₂ ), IZO (ZnO:In), ATO (SnO ₂ :Sb), AZO (ZnO:Al), GZO (ZnO:Ga) or FTO (SnO ₂ :F).

Preferably, in this embodiment, the transparent conductive layer 60 is an ITO film, and is grown by evaporation. Specifically, the ITO film is formed by electron beam evaporation;

Electron beam evaporation is a type of vacuum evaporation coating. It is a method that uses electron beams to directly heat the evaporation material under vacuum conditions, vaporizes the evaporation material and transports it to the substrate, and condenses on the substrate to form a thin film. In the electron beam heating device, the heated material is placed in a water-cooled crucible to prevent the evaporation material from reacting with the crucible wall to affect the quality of the film. Therefore, the electron beam evaporation deposition method can prepare high-purity films. At the same time, multiple crucibles can be placed in the same evaporation deposition device to achieve simultaneous or separate evaporation and deposition of multiple different substances; electron beam evaporation can evaporate high-melting point materials, and has higher thermal efficiency, larger beam current density, and faster evaporation speed than general resistance heating evaporation. The films produced are of high purity and good quality, and the thickness can be more accurately controlled. It can be widely used in the preparation of high-purity films and various optical material films such as conductive glass.

In this embodiment, during the electron beam evaporation process, the following conditions are met: the temperature is 200-400°C, the evaporation rate is The oxygen flow rate is 5 to 20 sccm. Preferably, in this embodiment, during the electron beam evaporation process, the temperature is 300°C and the evaporation rate is The oxygen flow rate was 10 sccm.

It can be understood that since the transparent conductive layer 60 is made of semiconductor material, the thickness of the transparent conductive layer 60 can be controlled to be within a relatively thin range by combining the above-mentioned evaporation parameters. To ensure the light transmittance of the thin semiconductor medium, and limit the lower limit of the growth thickness to ensure the continuity of the thin current transfer medium, so that it has both light transmittance and conductive properties, thereby achieving current expansion on the entire surface, effectively improving the brightness of the LED chip and reducing the operating voltage. Preferably, in this embodiment, the thickness of the ITO film is

(4) Pasting the patch 80 with electrode holes on the transparent conductive layer 60. Specifically, in this step, the patch includes a plurality of electrode holes arranged in an array. The electrode holes are conical holes, and the side with a larger opening is arranged close to the transparent conductive layer 60, that is, the side of the electrode hole facing the evaporation direction has a smaller opening. During the evaporation process, the metal can be prevented from falling on the side wall of the electrode hole during evaporation, affecting the growth shape of the electrode, and facilitating the subsequent removal of the patch 80. In addition, in this embodiment, the diameter of the electrode hole is determined according to the electrode pattern design of the product. The first metal layer 70 includes an upper metal layer 71 arranged on the surface of the patch 80 and an electrode hole located in the patch 80. The lower metal layer in the hole, the lower metal layer in the electrode hole contacts the ITO film to form a P electrode 72, and the metal layer on the surface of the patch 80 can be removed together with the patch 80, and a plurality of array-arranged P electrode 72 patterns corresponding to the electrode holes are quickly obtained. Compared with the prior art, the process steps such as photolithography and corrosion are reduced, the process flow is greatly reduced, the process cycle is shortened, and the production efficiency is greatly improved; at the same time, the use of various photolithography and corrosion solutions is reduced, and the abnormalities caused by the instability of photolithography and corrosion solutions, resulting in scrapping and rework operations, reduce the preparation cost of LED chips, and the process is simple and suitable for large-scale production.

In this embodiment, the thickness of the patch 80 is 5 to 10 μm. Preferably, in this embodiment, the thickness of the patch 80 is 8 μm. It can be understood that the patch 80 should be made of a material that is resistant to high temperatures and not easily deformed, and can be made of PVC material or metal material, etc., so as to facilitate the reuse of the patch and save production costs. In this embodiment, the patch 80 is made of PVC material.

(5) Depositing a first metal layer 70 on the patch 80 so that the first metal layer 70 contacts the transparent conductive layer 60 through the electrode hole to form a P electrode 72. Specifically, in this step, the thickness of the first metal layer 70 is 1.4 to 3 μm. The first metal layer 70 is deposited by electron beam evaporation. During the electron beam evaporation, the following conditions are met: the temperature is 200 to 600°C, and the deposition rate is Preferably, in this embodiment, during the electron beam evaporation process, the temperature is 400°C and the evaporation rate is The thickness of the first metal layer 70 obtained by evaporation is 2.3 um.

(6) A second metal layer is evaporated on the thinned N-type epitaxial layer 30 of the GaAs epitaxial wafer to form an N-electrode 10. Specifically, in this step, the thickness of the second metal layer is 0.2-0.6 um, and preferably, in this embodiment, the thickness of the second metal layer is 0.4 um.

Specifically, the materials of the first metal layer 70 and the second metal layer are Au, Ti, Pt, AuGe, Cr, AuGeNi, Al, etc. In this embodiment, the materials of the first metal layer 70 and the second metal layer are both Au, that is, the materials of the N electrode 10 and the P electrode 72 are both Au.

In addition, it can be understood that since the thinning operation of the GaAs substrate 20 has been completed in step (2), when the evaporation of the first metal layer 70 is completed, that is, after the growth of the P electrode 72, the GaAs epitaxial wafer can be directly flipped over to expose the thinned GaAs epitaxial wafer GaAs substrate 20, and the N electrode 10 is formed by evaporating the second metal layer in contact with the N-type epitaxial layer 30. It can be understood that the above-mentioned evaporation process is basically the same as the evaporation process in step (5), and both use electron beam evaporation for evaporation, which will not be described in detail here.

(7) The patch 80 is removed and annealed so that the P electrode 72 and the N electrode 10 form ohmic contacts with the P-type epitaxial layer 50 and the N-type epitaxial layer 30 respectively.

When metal and semiconductor are in contact, they can form non-rectifying contact, i.e., ohmic contact, which is another important type of metal-semiconductor contact. Ohmic contact refers to a contact that does not produce significant additional impedance and does not significantly change the equilibrium carrier concentration inside the semiconductor. Electrically speaking, the contact resistance of an ideal ohmic contact should be very small compared to the semiconductor sample or device. When current flows through, the voltage drop on the ohmic contact should be much smaller than the voltage drop of the sample or device itself. This type of contact does not affect the current-voltage characteristics of the device, or in other words, the current-voltage characteristics are determined by the resistance of the sample or the characteristics of the device.

In this step, the annealing temperature is 200-500° C., preferably, in this embodiment, the annealing temperature is 350° C. It can be understood that compared with the prior art, after the growth of the P electrode 72 is completed by evaporating metal, the ohmic contact of the P electrode 72 is completed by annealing once, and then the GaAs substrate 20 is thinned first, and then the growth of the N electrode 10 is completed by evaporating metal, and the ohmic contact of the N electrode 10 is completed by secondary annealing. By placing the thinning operation in advance, one annealing can be reduced, and the annealing after the two metal layer evaporation is combined, which greatly improves the production efficiency and reduces the production cost. In addition, after the ITO film in step (3) is evaporated, it can also be based on the one annealing treatment in this step. The crystal surface of the ITO film can be smoother and the resistance can be reduced, thereby further improving the conductive performance.

(8) Cutting the annealed GaAs epitaxial wafer into a plurality of LED chips. Specifically, in this step, cutting is performed using a diamond knife.

For ease of understanding, the product structure obtained after the above steps (1) to (3) is as shown in FIG2, wherein the above ITO film is arranged on one side of the P-type epitaxial layer 50; the product structure obtained after the above steps (4) to (6) is as shown in FIG3, wherein the above patch 80 is arranged on one side of the transparent conductive layer 60, the first metal layer 70 includes a metal layer on the surface of the patch 80 and a P electrode 72 in contact with the ITO film through an electrode hole, and the N electrode 10 is arranged on the thinned side of the GaAs substrate 20; the product structure obtained after the above step (7) is as shown in FIG4, after the patch 80 is removed, annealing treatment is performed to make the P electrode 72 and the N electrode 10 form ohmic contact with the P-type epitaxial layer 50, namely the N-type epitaxial layer 30; the product structure obtained after the above step (8) is as shown in FIG1, wherein the chip structure in FIG4 is cut into core particles, namely the final product structure.

In summary, the method for preparing the LED chip in the above-mentioned embodiment of the present invention first thins the GaAs substrate 20 of the GaAs epitaxial wafer, and after completing the evaporation of the first metal layer 70 of the P-type epitaxial layer 50, the thinned GaAs substrate 20 can be directly flipped over to expose the thinned GaAs substrate 20, and the second metal layer is evaporated, and then a unified annealing treatment is performed, and the ohmic contact between the P electrode 72 and the N electrode 10 is completed at the same time, which is equivalent to reducing the annealing treatment of the primary electrode, simplifying the process steps, and reducing the production cycle and production cost; at the same time, a reusable patch 80 with an electrode hole is set on the P-type epitaxial layer 50 to quickly obtain the required P electrode 72 pattern, which reduces the photolithography, corrosion, etc. compared with the prior art. The process steps can greatly reduce the process flow, shorten the process cycle, and greatly improve the production efficiency; at the same time, the use of various photolithography and etching solutions and the abnormalities caused by the instability of photolithography and etching solutions, which lead to scrapping and rework operations, can be reduced, and the preparation cost of LED chips can be reduced. The process is simple and suitable for large-scale production; in addition, by growing a transparent conductive layer 60 on one side of the P-type epitaxial layer 50 of the GaAs epitaxial wafer, since it has both light-transmitting and conductive properties, the current expansion of the entire surface can be achieved, the brightness of the LED chip can be effectively improved, and the operating voltage can be reduced. After the transparent conductive layer 60 is evaporated, it can also be subjected to an annealing treatment in this step, so that the crystalline surface of the ITO film can be smoother and the resistance can be reduced, thereby further improving the conductive performance.

A second embodiment of the present invention provides an LED chip, which is manufactured by the method for manufacturing the LED chip in the above embodiment.

Specifically, in this embodiment, the above-mentioned LED chip is a GaAs LED positive polarity chip, including a GaAs substrate 20 and an N electrode 10 and an N-type epitaxial layer 30 respectively arranged on both sides of the GaAs substrate 20, and the N-type epitaxial layer 30 is provided with a MQW layer 40, a P-type epitaxial layer 50, a transparent conductive layer 60 and a P electrode 72 in sequence.

In summary, in the preparation process of the LED chip in this embodiment, the GaAs substrate 20 of the GaAs epitaxial wafer is first thinned. After the first metal layer 70 of the P-type epitaxial layer 50 is evaporated, the thinned GaAs substrate 20 can be directly flipped to expose the thinned GaAs substrate 20, and the second metal layer is evaporated, and then a unified annealing treatment is performed, and the ohmic contact between the P electrode 72 and the N electrode 10 is completed at the same time, which is equivalent to reducing the annealing treatment of the electrode once, simplifying the process steps, and reducing the production cycle and production cost; at the same time, a reusable patch 80 with an electrode hole is set on the P-type epitaxial layer 50 to quickly obtain the required P electrode 72 pattern, which greatly reduces the process steps such as photolithography and corrosion compared to the prior art. The process flow is reduced, the process cycle is shortened, and the production efficiency is greatly improved; at the same time, the use of various photolithography and etching solutions and the abnormalities caused by the instability of photolithography and etching solutions, which lead to scrapping and rework operations, are reduced, and the preparation cost of LED chips is reduced. The process is simple and suitable for large-scale production; in addition, by growing a transparent conductive layer 60 on one side of the P-type epitaxial layer 50 of the GaAs epitaxial wafer, since it has both light-transmitting and conductive properties, the current expansion of the entire surface can be achieved, the brightness of the LED chip is effectively improved, and the operating voltage is reduced. After the transparent conductive layer 60 is evaporated, it is also based on the one-time annealing treatment in this step, which can make the crystal surface of the ITO film smoother and the resistance is reduced, thereby further improving the conductive performance and luminous efficiency of the LED chip.

In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

The above-described embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the attached claims.

Claims (10)

1. The preparation method of the LED chip is characterized by comprising the following steps of:

(1) Preparing a GaAs epitaxial wafer, wherein the GaAs epitaxial wafer comprises a GaAs substrate, an N-type epitaxial layer, an MQW luminescent layer and a P-type epitaxial layer which are sequentially stacked;

(2) Thinning the GaAs substrate;

(3) Growing a transparent conducting layer on the P-type epitaxial layer of the GaAs epitaxial wafer;

(4) Attaching a patch with electrode holes to the transparent conductive layer;

(5) Evaporating a first metal layer on the patch so that the first metal layer contacts the transparent conductive layer through the electrode hole to form a P electrode;

(6) Evaporating a second metal layer on one surface of the GaAs epitaxial GaAs substrate far away from the N-type epitaxial layer to form an N electrode;

(7) Taking down the patch, and annealing to enable the P electrode and the N electrode to form ohmic contact with the P-type epitaxial layer and the N-type epitaxial layer respectively;

(8) And cutting the annealed GaAs epitaxial wafer to form a plurality of LED chips.

2. The method of manufacturing an LED chip according to claim 1, wherein in the step (2), the thickness of the thinned GaAs epitaxial wafer is 140 to 220um.

3. The method of manufacturing an LED chip according to claim 1, wherein In the step (3), the material of the transparent conductive layer is selected from one or more of ITO (In ₂O₃：SnO₂)、IZO(ZnO：In)、ATO(SnO₂: sb), AZO (ZnO: al), GZO (ZnO: ga), or FTO (SnO ₂: F).

4. The method for manufacturing an LED chip according to claim 1, wherein in the step (3), the method specifically comprises:

evaporating by electron beam evaporation to form the transparent conductive layer;

wherein the transparent conductive layer is an ITO film, and the thickness of the ITO film is In the electron beam evaporation process, the temperature is 200-400 ℃, and the evaporation rate isThe oxygen flow is 5-20 sccm.

5. The method of manufacturing an LED chip according to claim 1, wherein in the step (4), the thickness of the patch is 5 to 10 μm, and the electrode hole is a tapered hole.

6. The method of manufacturing an LED chip of claim 1, wherein in said step (5), the thickness of said first metal layer is 1.4 to 3um.

7. The method for manufacturing an LED chip according to claim 1, characterized in that in the step (5), the method specifically comprises:

evaporating by electron beam evaporation to form the first metal layer;

Wherein, in the process of electron beam evaporation, the temperature is 200-600 ℃, and the evaporation rate is

8. The method of manufacturing an LED chip of claim 1, wherein in said step (6), the thickness of said second metal layer is 0.2 to 0.6um.

9. The method of manufacturing an LED chip according to claim 1, wherein in the step (7), the annealing temperature is 200 to 500 ℃.

10. An LED chip, characterized in that it is obtained by the manufacturing method according to any one of claims 1 to 9.