CN115458512A - Encapsulation structure and encapsulation method thereof - Google Patents
Encapsulation structure and encapsulation method thereof Download PDFInfo
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- CN115458512A CN115458512A CN202211245685.7A CN202211245685A CN115458512A CN 115458512 A CN115458512 A CN 115458512A CN 202211245685 A CN202211245685 A CN 202211245685A CN 115458512 A CN115458512 A CN 115458512A
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000005538 encapsulation Methods 0.000 title claims description 14
- 238000004806 packaging method and process Methods 0.000 claims abstract description 80
- 239000010410 layer Substances 0.000 claims description 147
- 238000007789 sealing Methods 0.000 claims description 53
- 239000000758 substrate Substances 0.000 claims description 45
- 238000000465 moulding Methods 0.000 claims description 29
- 238000002955 isolation Methods 0.000 claims description 17
- 150000001875 compounds Chemical class 0.000 claims description 12
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 230000007704 transition Effects 0.000 claims 2
- 238000001746 injection moulding Methods 0.000 abstract description 6
- 239000000243 solution Substances 0.000 description 12
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/041—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass H10F
- H01L25/042—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass H10F the devices being arranged next to each other
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/50—Encapsulations or containers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/93—Interconnections
- H10F77/933—Interconnections for devices having potential barriers
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
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Abstract
Description
技术领域technical field
本发明属于半导体封装技术领域,特别关于一种封装结构及其封装方法。The invention belongs to the technical field of semiconductor packaging, in particular to a packaging structure and a packaging method thereof.
背景技术Background technique
光感芯片是一种能够感受外部光线并能将其转化为电信号的电子器件。以CMOS(CMOS Image Sensor,CIS)芯片为例,其广泛应用于智能手机、安防、汽车自动驾驶等拍照录像系统中。CIS芯片通常采用半导体制造工艺进行芯片制作,再通过对CIS芯片进行一系列封装工艺形成封装结构。A photosensitive chip is an electronic device that can sense external light and convert it into electrical signals. Taking CMOS (CMOS Image Sensor, CIS) chips as an example, they are widely used in camera and video recording systems such as smartphones, security systems, and auto-driving cars. The CIS chip is usually manufactured using a semiconductor manufacturing process, and then a package structure is formed by performing a series of packaging processes on the CIS chip.
然而,现有的CIS芯片在加工生产过程中大多采用注塑封装的方式对CIS芯片进行封装,采用这一封装方式进行封装的CIS芯片,由于塑封模具的顶杆和芯片直接接触,顶杆容易导致其玻璃片受压碎裂,塑封料溢料,进而造成芯片良率低以及封装成本高的缺点,因此,对CIS芯片进行封装的效果较差。However, most of the existing CIS chips are packaged by injection molding during the processing and production process. For the CIS chips packaged by this packaging method, the ejector pins of the plastic packaging mold are in direct contact with the chip, and the ejector pins are easy to cause damage. The glass sheet is crushed under pressure, and the molding compound overflows, thereby causing the disadvantages of low chip yield and high packaging cost. Therefore, the effect of packaging the CIS chip is poor.
另外,现有的CIS芯片的封装结构体积较大,不符合电子设备的轻薄化设计的趋势。In addition, the packaging structure of the existing CIS chip is relatively large, which does not conform to the trend of thinner and thinner design of electronic equipment.
有鉴于此,提供需要对上述封装工艺进行优化和改进,克服现有的注塑封装导致的易破片、良率低和封装效果差的问题。In view of this, it is necessary to optimize and improve the above packaging process to overcome the problems of fragile chips, low yield and poor packaging effect caused by the existing injection molding packaging.
发明内容Contents of the invention
本发明解决的问题是如何改善现有注塑封装过程中的感光芯片易破片、塑封料溢料导致的封装良率低和封装体效果差的问题,同时,满足感光芯片小体积封装的趋势。The problem to be solved by the present invention is how to improve the problems of low packaging yield and poor package effect caused by easily broken pieces of photosensitive chips and overflow of plastic packaging materials in the existing injection molding packaging process, and at the same time, meet the trend of small-volume packaging of photosensitive chips.
为解决上述问题,本发明技术方案提供了一种封装结构,所述封装结构包括:封装基座,所述封装基座包括第一互连结构;弹性支撑件,所述弹性支撑件盖设于所述封装基座的一侧,所述弹性支撑件包括若干贯孔,所述第一互连结构自所述若干贯孔中露出;感光芯片,所述感光芯片贴装于所述弹性支撑件远离所述封装基座一侧,所述感光芯片经所述若干贯孔和所述第一互连结构电性连接;以及外部塑封层,所述外部塑封层塑封所述感光芯片和所述弹性支撑件至所述封装基座上,所述外部塑封层包括镂空区,所述感光芯片的感光区自所述镂空区中露出。In order to solve the above problems, the technical solution of the present invention provides a packaging structure, the packaging structure includes: a packaging base, the packaging base includes a first interconnection structure; an elastic support member, the elastic support member covers the On one side of the packaging base, the elastic support includes a plurality of through holes, the first interconnection structure is exposed from the plurality of through holes; a photosensitive chip, the photosensitive chip is mounted on the elastic support On the side away from the packaging base, the photosensitive chip is electrically connected to the first interconnection structure through the plurality of through holes; and an outer plastic sealing layer, the outer plastic sealing layer encapsulates the photosensitive chip and the elastic The supporting member is on the packaging base, the outer plastic sealing layer includes a hollow area, and the photosensitive area of the photosensitive chip is exposed from the hollow area.
作为可选的技术方案,所述封装基座包括:基板;有源芯片,所述有源芯片设置于所述基板一侧表面上且与所述基板电性连接;转接层,所述转接层设置于所述第一互连结构和所述有源芯片之间,所述转接层包括若干导通柱,每一导通柱相对的两端分别电性连接所述第一互连结构和所述有源芯片。As an optional technical solution, the packaging base includes: a substrate; an active chip disposed on one side of the substrate and electrically connected to the substrate; a transfer layer, the transfer layer The connection layer is arranged between the first interconnection structure and the active chip, the transfer layer includes a plurality of conductive columns, and the opposite ends of each conductive column are respectively electrically connected to the first interconnection structure and the active chip.
作为可选的技术方案,所述第一互连结构为再布线层,所述再布线层包括若干第一连接垫,所述若干第一连接垫和所述若干贯孔一一对应。As an optional technical solution, the first interconnection structure is a redistribution layer, and the redistribution layer includes a plurality of first connection pads, and the plurality of first connection pads correspond to the plurality of through holes one by one.
作为可选的技术方案,所述封装基座还包括内部塑封层,所述内部塑封层塑封所述有源芯片和所述转接层至所述基板上;其中,所述再布线层设置于所述内部塑封层上,所述再布线层上的若干第二连接垫和每一导通柱自所述内部塑封层中露出的一端电性连接,所述若干第二连接垫和所述若干第一连接垫位于所述再布线层相背的两侧表面上。As an optional technical solution, the packaging base further includes an inner plastic sealing layer, and the inner plastic sealing layer plastic seals the active chip and the transfer layer onto the substrate; wherein, the rewiring layer is disposed on On the inner plastic sealing layer, the plurality of second connection pads on the rewiring layer are electrically connected to one end exposed from the inner plastic sealing layer, and the plurality of second connection pads and the plurality of The first connection pads are located on opposite side surfaces of the redistribution layer.
作为可选的技术方案,所述封装基座还包括中间塑封层,所述中间塑封层塑封所述再布线层和所述内部塑封层至所述基板上;其中,所述若干第一连接垫自所述中间塑封层远离所述基板的一侧露出。As an optional technical solution, the packaging base further includes an intermediate molding layer, and the intermediate molding layer molds the rewiring layer and the inner molding layer onto the substrate; wherein, the plurality of first connection pads It is exposed from the side of the middle plastic sealing layer away from the substrate.
作为可选的技术方案,所述弹性支撑件设置于所述中间塑封层上方,且所述弹性支撑件至少部分区域不与所述中间塑封层直接接触。As an optional technical solution, the elastic supporting member is disposed above the intermediate plastic sealing layer, and at least a part of the elastic supporting member is not in direct contact with the intermediate plastic sealing layer.
作为可选的技术方案,所述弹性支撑件包括朝向所述基板伸出的侧壁,所述侧壁位于所述中间塑封层的外部,所述侧壁的边缘与所述基板固定连接。As an optional technical solution, the elastic supporting member includes a side wall protruding toward the substrate, the side wall is located outside the middle plastic encapsulation layer, and an edge of the side wall is fixedly connected to the substrate.
作为可选的技术方案,所述有源芯片朝向所述转接层的一侧表面设有第二互连结构,所述第二互连结构和每一导通柱相对的另一端电性连接。As an optional technical solution, a second interconnection structure is provided on the surface of the active chip facing the transfer layer, and the second interconnection structure is electrically connected to the opposite end of each via column. .
作为可选的技术方案,还包括透明隔离层,所述透明隔离层至少覆盖所述感光区。As an optional technical solution, a transparent isolation layer is further included, and the transparent isolation layer covers at least the photosensitive area.
本发明还提供一种封装方法,用于感光芯片封装,所述封装方法包括:The present invention also provides a packaging method for photosensitive chip packaging, the packaging method comprising:
制备封装基座,所述封装基座包括第一互连结构;preparing a package base, the package base including a first interconnection structure;
装配弹性支撑件至所述封装基座的一侧,所述弹性支撑件包括若干贯孔;Assembling an elastic support to one side of the packaging base, the elastic support includes a plurality of through holes;
贴装感光芯片至所述弹性支撑件远离所述封装基座一侧,键合所述感光芯片和所述第一互连结构;attaching the photosensitive chip to the side of the elastic support away from the package base, and bonding the photosensitive chip and the first interconnection structure;
于所述感光芯片的感光区一侧形成透明隔离层,制得待塑封单元;Forming a transparent isolation layer on one side of the photosensitive area of the photosensitive chip to obtain a unit to be plastic-encapsulated;
提供塑封模具,所述塑封模具包括相互适配上模具、下模具和顶杆,所述上模具和所述下模具共同界定塑封腔,所述顶杆至少部分位于所述塑封腔中;A plastic sealing mold is provided, the plastic sealing mold includes an upper mold, a lower mold and a ejector rod adapted to each other, the upper mold and the lower mold jointly define a plastic sealing cavity, and the ejector pin is at least partially located in the plastic sealing cavity;
装载所述待塑封单元至所述塑封腔中,所述顶杆接触所述透明隔离层并与所述感光区相对;Loading the unit to be molded into the molded cavity, the ejector pin contacts the transparent isolation layer and is opposite to the photosensitive area;
提供塑封料并注入所述塑封腔中,形成将所述感光芯片和所述弹性支撑框架塑封至所述封装基座上的外部塑封层;providing a molding compound and injecting it into the molding cavity to form an outer molding layer for molding the photosensitive chip and the elastic support frame to the packaging base;
移除所述塑封模具,所述外部塑封层在所述感光区一侧形成镂空部,所述感光区位于所述镂空部中,制得所述感光芯片的封装结构。The plastic encapsulation mold is removed, the outer plastic encapsulation layer forms a hollow part on one side of the photosensitive area, and the photosensitive area is located in the hollow part, so as to obtain the packaging structure of the photosensitive chip.
作为可选的技术方案,还包括:涂布透明胶层至所述感光区一侧形成所述透明隔离层。As an optional technical solution, the method further includes: coating a transparent adhesive layer on one side of the photosensitive area to form the transparent isolation layer.
作为可选的技术方案,所述制备封装基座的步骤还包括:提供基板和有源芯片;贴装所述有源芯片至所述基板上,键合所述有源芯片和所述基板进行电性连接;于所述有源芯片上形成第二互连结构;提供转接层,所述转接层倒装键合于所述第二互连结构上;提供塑封料,形成将所述有源芯片、所述第二互连结构和所述转接层塑封至所述基板上的内部塑封层;于所述内部塑封层上制作所述第一互连结构,所述第一互连结构和所述转接层电性连接;提供塑封料,形成将所述第一互连结构塑封至所述基板上的中间塑封层,制得所述封装基座;其中,所述转接层包括若干导通柱,每一导通柱相对的两端分别电性连接所述第二互连结构和所述第一互连结构。As an optional technical solution, the step of preparing the package base further includes: providing a substrate and an active chip; attaching the active chip to the substrate, and bonding the active chip and the substrate to carry out electrical connection; forming a second interconnection structure on the active chip; providing a transfer layer, the transfer layer is flip-chip bonded on the second interconnection structure; providing a plastic encapsulant to form the The active chip, the second interconnection structure, and the transfer layer are plastic-sealed to the inner plastic layer on the substrate; the first interconnection structure is fabricated on the inner plastic layer, and the first interconnection The structure is electrically connected to the transfer layer; a molding compound is provided to form an intermediate molding layer for molding the first interconnection structure onto the substrate to obtain the packaging base; wherein the transfer layer It includes a plurality of conducting columns, and opposite ends of each conducting column are electrically connected to the second interconnection structure and the first interconnection structure respectively.
与现有技术相比,本发明提供一种封装结构和封装方法,在封装基座上盖设弹性支撑件,利用弹性支撑件提供感光芯片的装片区,以及,利用弹性支撑件上的贯孔设计实现封装基座和感光芯片的电性连接。其中,弹性支撑件对感光芯片的弹性支撑用于分散注塑封装感光芯片工艺中施加在感光芯片上的外力,克服压伤、碎片的问题,对封装良率的提升存在明显有益效果。另外,封装基座中各元器件层叠布置在基板上,因此,可以有效实现封装结构的封装体积减小,符合封装小型化、集成化的封装趋势。Compared with the prior art, the present invention provides a packaging structure and a packaging method. An elastic support is covered on the package base, and the elastic support is used to provide a mounting area for the photosensitive chip, and the through hole on the elastic support is used to The design realizes the electrical connection between the package base and the photosensitive chip. Among them, the elastic support of the photosensitive chip by the elastic support is used to disperse the external force applied to the photosensitive chip in the injection molding process of packaging the photosensitive chip, overcome the problems of crushing and debris, and have a significant beneficial effect on improving the packaging yield. In addition, the various components in the package base are stacked and arranged on the substrate, therefore, the package volume of the package structure can be effectively reduced, which conforms to the trend of package miniaturization and integration.
以下结合附图和具体实施例对本发明进行详细描述,但不作为对本发明的限定。The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.
附图说明Description of drawings
图1为本发明一实施中提供的封装结构的侧视示意图。FIG. 1 is a schematic side view of a packaging structure provided in an implementation of the present invention.
图2为图1中的封装基座的制作过程的侧视示意图。FIG. 2 is a schematic side view of the manufacturing process of the package base in FIG. 1 .
图3为图1中弹性支撑件和封装基座连接的侧视示意图。FIG. 3 is a schematic side view of the connection between the elastic support member and the package base in FIG. 1 .
图4为图1中感光芯片装贴至弹性支撑件上的侧视示意图。FIG. 4 is a schematic side view of the photosensitive chip in FIG. 1 attached to the elastic support.
图5为图1中塑封感光芯片和弹性支撑件至封装基座上的侧视示意图。FIG. 5 is a schematic side view of plastically encapsulating the photosensitive chip and the elastic supporting member on the package base in FIG. 1 .
图6为本发明另一实施例中提供的封装方法的流程图。FIG. 6 is a flowchart of a packaging method provided in another embodiment of the present invention.
具体实施方式detailed description
为了使本发明的目的、技术方案及优点更加清楚明白,下面结合实施例及附图,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅用以解释本发明,并不用于限定本发明。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the embodiments and accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.
如图1所示,本发明的目的之一在于提供一种封装结构100,其包括封装基座、弹性支撑件20、感光芯片30和外部塑封层40,其中,封装基座包括第一互连结构11;弹性支撑件20盖设于封装基座的一侧,弹性支撑件包括若干贯孔21,第一互连结构11从若干贯孔21中露出;感光芯片设置于弹性支撑件20远离封装基座的一侧,且感光芯片20经若干贯孔21与第一互连结构11电性连接;外部塑封层40塑封感光芯片30和弹性支撑件20至封装基座上,外部塑封层40包括镂空区41,感光芯片30的感光区31自镂空区41中露出。As shown in FIG. 1 , one of the objectives of the present invention is to provide a
本发明提供的封装结构100中,外部塑封层40的塑封过程中,由弹性支撑件20对感光芯片30进行弹性支撑,以抵消塑封模具施加在感光芯片30上的压力,可有效避免感光芯片30的压伤。In the
如图1所示,弹性支撑件20与封装基座之间设有间隙S,间隙S用于缓冲塑封模具施加在感光芯片30上的压力,进而有效克服感光芯片30的压伤,避免芯片破裂。As shown in FIG. 1 , there is a gap S between the
在一优选的实施例中,弹性支撑件20例如是塑胶盖等结构。In a preferred embodiment, the elastic supporting
在一优选的实施例中,弹性支撑件20的至少部分区域不与封装基座接触,从而在弹性支撑件20和封装基座之间界定用于提供缓冲作用的间隙。In a preferred embodiment, at least a partial area of the elastic supporting
如图1和图2所示,封装基座包括层叠设置的基板10、有源芯片12、转接层13以及第一互连结构11,有源芯片12通过贴装材料装贴于基板10一侧表面上,经金属线122和基板10电性链接;转接层13设置于第一互连结构11和有源芯片12之间,转接层13包括若干导通柱131,每一导通柱131相对的两端分别电性连接第一互连结构11和有源芯片12。As shown in Figures 1 and 2, the package base includes a
本实施例中,有源芯片12靠近转接层13一侧的表面上设有第二互连结构121,第二互连结构121例如是通过钢网印刷形成的若干锡柱,每一锡柱和对应的每一导通柱131相对的另一端电性连接。优选的,若干锡柱的尺寸例如是60-80微米。In this embodiment, a
另外,在本发明其他实施例中,第二互连结构也可以是形成在有源芯片上的再布线层,经再布线层和转接层之间实现电性连接。In addition, in other embodiments of the present invention, the second interconnection structure may also be a rewiring layer formed on the active chip, and the electrical connection is realized between the rewiring layer and the transfer layer.
进一步,转接层13例如是TSV(Through-Silicon Via)硅转接板,若干导通柱131例如是嵌设在硅基板中的金属柱,金属柱优选为铜柱,铜柱相对的两端从硅基板相背的两个表面上露出用于和第一互连结构11和第二互连结构121实现电性连接,并将感光芯片30中光电信号输入至有源芯片12中,经处理后经基板10向外输出。Furthermore, the
本实施例中,硅转接板倒装键合至第二互连结构121上。In this embodiment, the silicon interposer is flip-chip bonded to the
在一优选的实施例中,感光芯片30具体可为CIS芯片,用于将感测到的光信号转换为电信号。有源芯片12具体可包括数字信号处理(Digital Signal Process,DSP)芯片,用于对感光芯片30转换的电信号进行处理。In a preferred embodiment, the
继续参照图1和图2,封装基座的第一互连结构11例如是再布线层,再布线层层叠于转接层13的上方,再布线层例如包括多层交替布置的金属层和层间介质层,任意相邻的金属层通过层间介质层上的过孔进行电性连接。Continuing to refer to FIG. 1 and FIG. 2, the
本实施例中,再布线层相背的两个表面上分别包括若干第一连接垫111和若干第二连接垫112,其中,若干第一连接垫111与若干贯孔21对应,并从若干贯孔21中露出;若干第二连接垫112和若干导通柱131的一端对应。第一连接垫111和第二连接垫112例如是铜焊盘、锡球、锡柱等金属垫。In this embodiment, the two opposite surfaces of the rewiring layer respectively include a plurality of
再布线层形成于封装基座的内部塑封层14远离基板10的一侧表面,内部塑封层14用于塑封转接层13、有源芯片12至基板10上,内部塑封层14为再布线层的制作提供了平台。内部塑封层14对应转接层13的导通柱131包括开孔141,导通柱131从开孔141中露出,与再布线层中的第二连接垫112电性连接。The rewiring layer is formed on the surface of the inner
另外,封装基座中基板10、有源芯片12、转接层13和第一互连结构依次层叠设置,可以用于缩减封装体积,进而满足封装小型化、集成化的要求。In addition, the
继续参照图1和图2,再布线层上方还包括中间塑封层15,中间塑封层15用于将再布线层塑封至内部塑封层14上,提高封装基座的稳定性,使得再布线层和转接层13之间的电性连接稳定性提升。Continuing to refer to FIG. 1 and FIG. 2 , an intermediate
如图3所示,将弹性支撑件20与基板10固定连接包括:基板10上预留凹槽101,凹槽101内涂布粘胶;弹性支撑件20朝向基板10伸出的侧壁22的边缘部分插入凹槽101中,固化粘胶实现弹性支撑件20与基板10的固定连接。As shown in FIG. 3 , the fixed connection of the
其中,弹性支撑件20的侧壁22围设于中间塑封层15的外部,且不与中间塑封层15接触;弹性支撑件20的顶壁23悬空于再布线层上方,也不与再布线层接触;进而在弹性支撑件和封装基座之间形成间隙S。其中,侧壁22围绕顶壁23的周边设置,顶壁23与再布线层相对。Wherein, the
在本发明本发明其他实施例中,优选在弹性支撑件的顶壁和再布线层之间形成间隙。主要原因在于,顶壁23对应再布线层的上方设置感光芯片30(如图4所示),注塑塑封制程中,塑封模具的顶杆600直接作用于感光芯片30的感光区31上方(如图5所示),当间隙位于感光区31对应的下方时,可以更好的缓冲顶杆600的作用力,避免压伤和破片的问题。In other embodiments of the present invention, a gap is preferably formed between the top wall of the elastic support and the rewiring layer. The main reason is that the
继续参照图3,顶壁23的边缘和侧壁22连接处具有突出的肩部,肩部的表面高于顶壁23的表面,肩部和顶壁23共同界定出感光芯片30的装片区。其中,若干贯孔21形成在顶壁23上,位于上述装片区中。Continuing to refer to FIG. 3 , there is a protruding shoulder at the junction between the edge of the
如图4所示,感光芯片30装片至上述装片区中包括,感光芯片30经贴装材料装贴于顶壁23上,感光芯片30经金属线33和第一互连结构11打线连接,其中,金属线33的一端电性连接感光芯片30上的引脚,金属线33的另一端穿过对应的贯孔21与第一互连结构上的第一连接垫111电性连接。As shown in FIG. 4 , loading the
需要说明的是,在本发明其他实施例中,感光芯片还可以通过其他结构和第一互连结构电性连接,例如,在感光芯片和顶壁之间形成另一再布线层,再布线层对贯孔包括若干锡柱,若干锡柱穿过贯孔和第一互连结构电性连接,再布线层的另一侧和感光芯片电性连接。It should be noted that, in other embodiments of the present invention, the photosensitive chip can also be electrically connected to the first interconnection structure through other structures, for example, another rewiring layer is formed between the photosensitive chip and the top wall, and the rewiring layer pair The through hole includes a plurality of tin pillars, and the plurality of tin pillars pass through the through hole and are electrically connected to the first interconnection structure, and then the other side of the wiring layer is electrically connected to the photosensitive chip.
继续参照图4,感光芯片30远离基板10一侧包括感光区31,感光区31上方覆盖有透明隔离层32,透明隔离层32用于避免感光区31直接暴露于外部环境中,影响产品寿命。透明隔离层32可以是透明胶或者其他透明膜片。Continuing to refer to FIG. 4 , the side of the
如图1、图4和图5所示,在感光芯片30和弹性支撑件20的外部形成外部塑封层40包括:As shown in FIG. 1, FIG. 4 and FIG. 5, forming an external
将包括封装基座、弹性支撑件20和感光芯片30的待塑封单元放置在塑封模具的塑封腔500中,其中,塑封腔500位于上模具300和下模具200之间,待塑封单元例如承载于下模具200一侧,顶杆600用于向塑封腔500提供推挤力,将塑封料400推挤至塑封强500中,并包覆弹性支撑件20和感光芯片30,其中,顶杆600接触感光芯片30上方的透明隔离层32,用于在塑封料400固化形成的外部塑封层40中制得镂空部41,感光区31位于镂空部41中并暴露出来用于接收外界光线。The unit to be molded including the package base, the
由图5可知,顶杆600推挤塑封料400朝向塑封腔500移动的过程中,塑封料400移动施加在感光芯片30上的作用力和顶杆600接触感光芯片30施加的作用力都可以通过其下方的弹性支撑件20形变进行缓冲,优选的,通过弹性支撑件20和封装基座之间的间隙S进行缓冲吸收,有效缓解感光芯片30上的外力,克服压伤、碎片的问题,对封装良率的提升存在明显有益效果。It can be seen from FIG. 5 that when the
如图6所示,本发明还提供一种封装方法1000,适用于感光芯片的封装,用于有效降低芯片压伤,同时实现小体积封装的技术效果。As shown in FIG. 6 , the present invention also provides a
封装方法1000包括:
制备封装基座,封装基座包括第一互连结构;Prepare a packaging base, the packaging base includes a first interconnection structure;
装配弹性支撑件至封装基座的一侧,弹性支撑件包括若干贯孔;Assembling the elastic support to one side of the packaging base, the elastic support includes a plurality of through holes;
贴装感光芯片至弹性支撑件远离封装基座一侧,键合感光芯片和第一互连结构;Mounting the photosensitive chip to the side of the elastic support away from the package base, bonding the photosensitive chip and the first interconnection structure;
于感光芯片的感光区一侧形成透明隔离层,制得待塑封单元;A transparent isolation layer is formed on the side of the photosensitive area of the photosensitive chip to obtain a unit to be plastic-encapsulated;
提供塑封模具,塑封模具包括相互适配上模具、下模具和顶杆,上模具和下模具共同界定塑封腔,顶杆至少部分位于塑封腔中;A plastic sealing mold is provided, the plastic sealing mold includes an upper mold, a lower mold and a ejector rod adapted to each other, the upper mold and the lower mold jointly define a plastic sealing cavity, and the ejector pin is at least partially located in the plastic sealing cavity;
装载所述待塑封单元至所述塑封腔中,所述顶杆接触所述透明隔离层并与所述感光区相对;Loading the unit to be molded into the molded cavity, the ejector pin contacts the transparent isolation layer and is opposite to the photosensitive area;
提供塑封料并注入所述塑封腔中,形成将所述感光芯片和所述弹性支撑框架塑封至所述封装基座上的外部塑封层;以及providing a molding compound and injecting it into the molding cavity to form an outer molding layer for molding the photosensitive chip and the elastic support frame to the packaging base; and
移除所述塑封模具,所述外部塑封层在所述感光区一侧形成镂空部,所述感光区位于所述镂空部中,制得所述感光芯片的封装结构。The plastic encapsulation mold is removed, the outer plastic encapsulation layer forms a hollow part on one side of the photosensitive area, and the photosensitive area is located in the hollow part, so as to obtain the packaging structure of the photosensitive chip.
在一优选的实施例中,涂布透明胶层至所述感光区一侧形成所述透明隔离层。In a preferred embodiment, the transparent isolation layer is formed by coating a transparent adhesive layer on one side of the photosensitive region.
在一优选的实施例中,制备封装基座的步骤还包括:提供基板和有源芯片;贴装有源芯片至所述基板上,键合有源芯片和基板进行电性连接;于有源芯片上形成第二互连结构;提供转接层,倒装键合转接层于第二互连结构上;提供塑封料,形成将有源芯片、第二互连结构和转接层塑封至基板上的内部塑封层;于内部塑封层上制作第一互连结构,第一互连结构和所述转接层电性连接;提供塑封料,形成将第一互连结构塑封至基板上的中间塑封层,制得封装基座;其中,转接层包括若干导通柱,每一导通柱相对的两端分别电性连接第二互连结构和第一互连结构。In a preferred embodiment, the step of preparing the package base further includes: providing a substrate and an active chip; attaching the active chip to the substrate, bonding the active chip and the substrate for electrical connection; A second interconnection structure is formed on the chip; a transfer layer is provided, and the transfer layer is flip-chip bonded on the second interconnection structure; a plastic encapsulant is provided to form the active chip, the second interconnection structure and the transfer layer. An internal plastic sealing layer on the substrate; a first interconnection structure is fabricated on the internal plastic sealing layer, and the first interconnection structure is electrically connected to the transfer layer; a plastic sealing compound is provided to form a plastic sealing of the first interconnection structure on the substrate The middle plastic sealing layer is used to make the packaging base; wherein, the transfer layer includes a plurality of conducting columns, and the opposite ends of each conducting column are respectively electrically connected to the second interconnection structure and the first interconnection structure.
综上,本发明提供一种封装结构和封装方法,在封装基座上盖设弹性支撑件,利用弹性支撑件提供感光芯片的装片区,以及,利用弹性支撑件上的贯孔设计实现封装基座和感光芯片的电性连接。其中,弹性支撑件对感光芯片的弹性支撑用于分散注塑封装感光芯片工艺中施加在感光芯片上的外力,克服压伤、碎片的问题,对封装良率的提升存在明显有益效果。另外,封装基座中各元器件层叠布置在基板上,因此,可以有效实现封装结构的封装体积减小,符合封装小型化、集成化的封装趋势。本发明已由上述相关实施例加以描述,然而上述实施例仅为实施本发明的范例。此外,上面所描述的本发明不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。必需指出的是,本发明还可有其他多种实施例,在不背离本发明精神及其实质的情况下,熟悉本领域的技术人员可根据本发明作出各种相应的改变和变形,但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。To sum up, the present invention provides a packaging structure and packaging method. An elastic support is provided on the package base, and the elastic support is used to provide a mounting area for the photosensitive chip, and the through-hole design on the elastic support is used to realize the The electrical connection between the seat and the photosensitive chip. Among them, the elastic support of the photosensitive chip by the elastic support is used to disperse the external force applied to the photosensitive chip in the injection molding process of packaging the photosensitive chip, overcome the problems of crushing and debris, and have a significant beneficial effect on improving the packaging yield. In addition, the various components in the package base are stacked and arranged on the substrate, therefore, the package volume of the package structure can be effectively reduced, which conforms to the trend of package miniaturization and integration. The present invention has been described by the above-mentioned related embodiments, however, the above-mentioned embodiments are only examples for implementing the present invention. In addition, the technical features involved in the different embodiments of the present invention described above can be combined with each other as long as there is no conflict with each other. It must be pointed out that the present invention can also have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these Corresponding changes and deformations should belong to the scope of protection of the appended claims of the present invention.
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040065963A1 (en) * | 2002-09-17 | 2004-04-08 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield |
US20060102992A1 (en) * | 2004-11-17 | 2006-05-18 | Heung-Kyu Kwon | Multi-chip package |
CN101183676A (en) * | 2007-02-15 | 2008-05-21 | 日月光半导体制造股份有限公司 | Package structure and method for manufacturing the same |
CN104051354A (en) * | 2013-03-12 | 2014-09-17 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
WO2020019263A1 (en) * | 2018-07-26 | 2020-01-30 | 深圳市汇顶科技股份有限公司 | Chip packaging structure, method and terminal device |
CN110808240A (en) * | 2019-10-31 | 2020-02-18 | 北京燕东微电子有限公司 | Package-on-package structure and method for manufacturing the same |
CN210668369U (en) * | 2019-12-17 | 2020-06-02 | 江苏爱矽半导体科技有限公司 | Stacked packaging structure |
-
2022
- 2022-10-12 CN CN202211245685.7A patent/CN115458512B/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040065963A1 (en) * | 2002-09-17 | 2004-04-08 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield |
US20060102992A1 (en) * | 2004-11-17 | 2006-05-18 | Heung-Kyu Kwon | Multi-chip package |
CN101183676A (en) * | 2007-02-15 | 2008-05-21 | 日月光半导体制造股份有限公司 | Package structure and method for manufacturing the same |
CN104051354A (en) * | 2013-03-12 | 2014-09-17 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
WO2020019263A1 (en) * | 2018-07-26 | 2020-01-30 | 深圳市汇顶科技股份有限公司 | Chip packaging structure, method and terminal device |
CN110808240A (en) * | 2019-10-31 | 2020-02-18 | 北京燕东微电子有限公司 | Package-on-package structure and method for manufacturing the same |
CN210668369U (en) * | 2019-12-17 | 2020-06-02 | 江苏爱矽半导体科技有限公司 | Stacked packaging structure |
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