CN1154559A

CN1154559A - Semi-conductor memory device and it testing circuit, memory device system and data transmission system

Info

Publication number: CN1154559A
Application number: CN96121178A
Authority: CN
Inventors: 户田春希
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1995-10-04
Filing date: 1996-10-04
Publication date: 1997-07-16
Anticipated expiration: 2016-10-04
Also published as: CN1099118C; TW309657B; KR970023369A; KR100261641B1

Abstract

The semiconductor memory of the present invention can increase the data transfer speed of the memory without increasing the chip area. Memory cells 11 - 0 to 11 - 3 are arranged in a matrix on the memory chip 10 . The data input/output circuit 12 is arranged along one side of the memory chip 10 . The data bus 13 is arranged between the memory cells and connected to the data input/output circuit 12 . In each memory unit, the element array controller CAC and the row decoder RD are opposite to each other, and the column decoders CD0 and CD1 are opposite to the DQ buffer DQ. The local DQ line 18a is arranged between the storage element arrays CAL, CAR, and the global DQ line 18b is arranged on the storage elements CAL, CAR. The direction in which the local DQ line 18a extends is perpendicular to the direction in which the global DQ line 18b extends.

Description

Semiconductor memory and test circuit thereof, accumulator system and data communication system

The invention relates to many bits N-type semiconductor N storer of the input and output of the data of carrying out a plurality of bits simultaneously.

In digital display circuit, following these measures have been taked for improving data transfer rate with DRAM semiconductor memories such as (dynamic RAM).

First method is to make semiconductor memory become many bits type.Many bits (* 2 ⁿ) the N-type semiconductor N storer generally is constituted as and can carries out 2 simultaneously ⁿThe data input and output of (n is a natural number) bit.

Second kind of way is to make the input and output action of carrying out data with the high frequency external clock synchronization ground by CPU (CPU (central processing unit)) output.In such clock synchronous semiconductor memory (SDRAM, RDRAM etc.), just can be because the frequency of external clock is high more with the continuous data of high more speed input and output, thus can improve data transfer rate.

The third way is that a plurality of storeies (bank) unit is set in a semiconductor memory (memory chip).These a plurality of memory cells are made to has identical element mutually, and makes these a plurality of memory cells can carry out the defeated output function of data independently of one another.Thus, can shorten until the time (stand-by period) of access, thereby can improve data transfer rate to original date.

Fig. 3 represents the outline of the chip layout of semiconductor memory always.

This semiconductor memory possesses above-mentioned whole three kinds of measures.

On a memory chip 10, dispose four memory cell 11-0～11-3.In each memory cell 11-0～11-3, form memory element array, element arrays controller, also forming the peripheral circuit of line decoder, column decoder, DQ buffer (buffer that is called the output input part of memory cell) etc. simultaneously.

And on a memory chip 10, dispose data input and output zone 12.In data input and output zone 12, form a plurality of imput output circuits (I/O), when for example carrying out the input and output of data of 16 bits (2 byte) at the same time, forming 16 imput output circuits.

Between memory cell 11-0～11-3, dispose data bus 13.Data bus 13 becomes the data path between memory cell 11-0～11-3 and the data input and output zone 12.Data bus 13 for example carries out at the same time under the situation of input and output of data of 16 bits (2 byte) transmitting by the data of carrying out 16 bits and constitutes like that.

The data input-output operation of above-mentioned semiconductor memory carries out as follows.

At first, by selecting a storage unit among four memory cell 11-0～11-3.In a selected memory cell, carry out the accessing operation of memory element, by selected memory cell output 2 according to address signal ⁿThe data of bit (for example 16 bits (2 byte)).

These are 2 years old ⁿThe bit data are imported into data input and output zone 12 by data bus 13, and output to semiconductor memory (memory chip) outside by data input and output zone 12.

The problem that must inquire in the above-mentioned semiconductor memory is the ratio in shared data bus 13 zones in the whole zone on a memory chip.That is, make the zone of data bus 13 as much as possible little, this is vital to dwindling area of chip.

Along with the bit number that carries out input and output simultaneously increases, the zone of data bus also increases.

Also in other words, always along with the structure of semiconductor memory when being transformed into many bits like that, is being deposited the shortcoming that chip area increases towards 16 bit formula (* 16) → 32 bit formula (* 32) → 64 bit formulas (* 64).

The present invention makes in the semiconductor memory of many bits and storage unit formula clock synchronization for solving above-mentioned shortcoming, its objective is, can not increase chip area and improves data transfer rate.

For achieving the above object, semiconductor memory of the present invention is provided with a plurality of memory cells that dispose on memory chip and the described memory chip.Described a plurality of memory cell carries out the read operation of many bits data or many bits data write operation separately independently of each other.

Described a plurality of memory cell has a plurality of middle storage blocks (block) separately.Storage block has two little storage blocks that are made of memory element array, the sensor amplifier that disposes and the word line that disposes, data line and column selection line separately in described on described memory element array between described two little storage blocks.Storage block is configured on the column direction of the right prolongation of aforementioned column selection line and aforementioned data line separately in described.Aforementioned little storage block is configured on the aforementioned column direction separately.

Aforementioned a plurality of memory cell has at least one column decoder side, that be connected to aforementioned column selection line in two ends that are configured in aforementioned column direction separately.

Aforementioned a plurality of memory cell have separately two ends of line direction that are configured in aforementioned word line extend a side, aforementioned in storage block line decoder one, that be connected to aforementioned word line is set separately.

Aforementioned a plurality of memory cell has the DQ buffer on the other hand that is configured in aforementioned column direction two ends separately.

Aforementioned a plurality of memory cell has the element arrays controller of the write operation of read operations the opposing party of being configured in aforementioned line direction two ends, the aforementioned many bits data of control or aforementioned many bits data separately.

Semiconductor memory of the present invention have be configured on the aforementioned memory chip, be the data input and output zone of carrying out the input and output of aforementioned many bits data, and aforementioned a plurality of memory cell data bus that set up jointly, prolong and constitute the path of the aforementioned many bits data between aforementioned a plurality of memory cell and the aforementioned data input and output zone at aforementioned line direction.

Aforementioned a plurality of memory cell have separately be configured in constitute aforementioned in each between aforementioned two little storage blocks of storage block, on aforementioned line direction, prolong and to be connected to the local DQ line of aforementioned reading magnifier right, with aforementioned column direction prolongation on the storage block in aforementioned and be connected aforementioned local DQ line right with the overall DQ line of aforementioned DQ buffer.

A plurality of main storage units that semiconductor memory of the present invention is provided with memory chip and disposes on described memory chip.Each free a plurality of quantum memories unit of aforementioned a plurality of main storage unit constitutes.Aforementioned a plurality of quantum memories unit carries out the read operation of many bits data or the write operation of many bits data separately independently of each other.

Aforementioned a plurality of quantum memories unit has a plurality of middle storage blocks separately.Storage block has two little storage blocks, the reading magnifier of being made up of memory element array that disposes separately and is configured in word line, data line and column selection line on the aforementioned memory element array in aforementioned between aforementioned two little storage blocks.Storage block is configured on aforementioned column selection line and the column direction of aforementioned data line to prolongation separately in aforementioned.Aforementioned little storage block is configured on the aforementioned column direction separately.

Aforementioned a plurality of quantum memories unit has separately and is configured at least one a column decoder side, that be connected to aforementioned column selection line in aforementioned column direction two ends.

Aforementioned a plurality of quantum memories unit have separately a side in line direction two ends that are configured in aforementioned word line extend, aforementioned in storage block be provided with one and be connected to the line decoder of aforementioned word line separately.

Aforementioned a plurality of quantum memories unit has the DQ buffer that is configured in the opposing party in aforementioned column direction two ends separately.

Aforementioned a plurality of quantum memories unit has the element arrays controller of the write operation of read operations the opposing party of being configured in aforementioned line direction two ends, the aforementioned many bits data of control or aforementioned many bits data separately.

Semiconductor memory of the present invention has the data output output area for the input and output of carrying out aforementioned many bits data that is configured on the aforementioned memory chip, and common be provided with, a plurality of data buss of becoming the path of the aforementioned many bits data between aforementioned quantum memory unit and the aforementioned data input and output zone on aforementioned line direction before the prolongation in two above quantum memory unit in the layer portion quantum memory unit of aforementioned a plurality of main storage units.

Aforementioned a plurality of quantum memories unit have separately be configured in constitute aforementioned in each between aforementioned two little storage blocks of storage block, on aforementioned line direction, prolong and to be connected to the local DQ line of aforementioned reading magnifier right, with prolong on the aforementioned column direction in storage block upper edge in aforementioned and to be connected aforementioned local DQ line right to the overall DQ line that reaches aforementioned DQ buffer.

The semiconductor memory that is provided with test circuit of the present invention has the memory element array that is made of a plurality of storage blocks, n bit data is write the register that storage block in the memory element in the individual storage block of n in aforementioned a plurality of storage block (n for greater than 2 natural number) writes means and keeps writing the aforementioned n bit data of an aforementioned n storage block in advance simultaneously.

Test circuit of the present invention is provided with in test pattern and is used for the test pattern write/read means that write simultaneously the aforementioned n bit data that aforementioned register keeps in the memory element of aforementioned memory element array and read the aforementioned n bit data of aforementioned memory element; The aforementioned n bit data that keep in the aforementioned register and the aforementioned n bit data of being read from aforementioned memory element by aforementioned test pattern write/read means are compared and according to this comparative result judge the aforesaid semiconductor memory whether well reach output show its whether good result's 1 bit data the comparison means and will be outputed to by the aforementioned 1 bit data that aforementioned relatively means are exported the test imput output circuit of aforesaid semiconductor memory outside.

Whether good test circuit of the present invention be provided with the means that latch of the n bit data that keep the aforementioned comparative result in the aforementioned relatively means of expression and the aforementioned n bit data that latch means be not added to the conversion means that imput output circuit is used in aforementioned test in proper order in aforementioned result when good.

The semiconductor memory that is provided with test circuit of the present invention is for carrying out the n bit N-type semiconductor N storer of n bit data input and output simultaneously, the aforesaid semiconductor storer has n the output contact pin of using in the normal manipulation mode, and the test of test circuit of the present invention is connected to an aforementioned n output contact pin of exporting in the contact pin with output circuit.

Data communication system of the present invention has a plurality of memory blocks that prolong the ground configuration at column direction, each memory block by be configured to two switch arrays that rectangular a plurality of switches constitute, in line direction two ends of aforementioned two switch arrays side configuration and select before line decoder, the configuration and along the local DQ line of aforementioned line direction prolongation be connected to a plurality of switches of each switch arrays and the data line that data direct into aforementioned local DQ line is formed between aforementioned two switch arrays of row of these two switch arrays.

And data communication system of the present invention also has in aforementioned a plurality of storage blocks upper edge aforementioned column direction and prolongs the overall DQ line that configuration and an end are connected to aforementioned local DQ line, dispose to a side in two ends of the aforementioned column direction of aforementioned a plurality of storage blocks and select the column decoder of row of the switch arrays of aforementioned a plurality of storage blocks, with the go forward side by side data imput output circuit of line data input and output of the opposing party ground configuration in two ends of the aforementioned column direction of aforementioned a plurality of data blocks and the other end that is connected to aforementioned overall DQ line.

Fig. 1 is the figure of expression as the chip layout of the semiconductor memory of first reference example of the present invention;

Fig. 2 is the figure of the chip layout in the memory cell of detailed presentation graphs 1;

Fig. 3 is the figure of expression as the chip layout of partly leading storer of the present invention's second reference example;

Fig. 4 is the figure of the chip layout in the memory cell of detailed presentation graphs 3;

Fig. 5 is the figure of the chip layout of simple presentation graphs 1;

Fig. 6 is the figure of expression as the chip layout of the variation of Fig. 1 first reference example;

Fig. 7 is the figure of the chip layout of detailed presentation graphs 6;

Fig. 8 is the figure of expression as the chip layout of the variation of first reference example of Fig. 1;

Fig. 9 is the figure of the chip layout of detailed presentation graphs 8;

Figure 10 is the figure of expression as the chip layout of the semiconductor memory of first embodiment of the invention;

Figure 11 is the figure of chip layout that represents the memory cell of Figure 10 in detail;

Figure 12 is the figure of the construction of switch example of expression Figure 11;

Figure 13 is the figure of the topology example of expression column decoder;

Figure 14 is the figure that the expression memory cell is selected the topology example of circuit;

Figure 15 is the figure of expression data inputting and outputting circuit structure example;

Figure 16 is the figure of the major part of expression test circuit structure;

Figure 17 is the figure that represents the test circuit structure of Figure 16 in detail;

Figure 18 is the figure of expression test with the topology example of change-over circuit;

The figure of the signal waveform when Figure 19 is the expression test pattern;

The figure of the signal waveform when Figure 20 is the expression test pattern;

Figure 21 is the figure of expression as the chip layout of second embodiment of the invention;

Figure 22 is the figure that the chip layout of Figure 10 represented in summary;

Figure 23 is the figure of first variation of the chip layout of expression Figure 22;

Figure 24 is the figure that represents the chip layout of Figure 23 in detail;

Figure 25 is the figure of first variation of the chip layout of expression Figure 21;

Figure 26 is the figure of second variation of the chip layout of expression Figure 22;

Figure 27 is the figure that represents the chip layout of Figure 26 in detail;

Figure 28 is the figure of second variation of expression Figure 21 chip layout;

Figure 29 is the figure of the 3rd variation of the chip layout of expression Figure 22;

Figure 30 is the figure that represents the chip layout of Figure 29 in detail;

Figure 31 is the figure of the 3rd variation of the chip layout of expression Figure 21;

Figure 32 is the figure of the 4th variation of the chip layout of expression Figure 22;

Figure 33 is the figure that represents the chip layout of Figure 32 in detail;

Figure 34 is the figure of the 4th variation of the chip layout of expression Figure 21;

Figure 35 is the figure of expression data communication system of the present invention;

Figure 36 is the figure of expression accumulator system of the present invention; With

Figure 37 is the figure that represents the chip layout of semiconductor memory always.

Following limit elaborates to semiconductor memory of the present invention and test circuit thereof and data communication system with reference to the accompanying drawing limit.

Fig. 1 represents the chip layout (design) as the semiconductor memory of the present invention's first reference example.Fig. 2 shows the topological design in the memory cell of Fig. 1 in detail.

Describe with 16 bit type (* 16) semiconductor memories of this reference example the 16 bit data of input and output simultaneously.

On a memory chip 10, dispose 4 memory cell 11-0～11-3.Be formed with memory element array CAL, CAR, element arrays controller CAC among each memory cell 11-0～11-3, also be formed with the peripheral circuit of line decoder RD, column decoder CD0, CD1, DQ buffer (buffer that is called memory cell input and output portion) DQ etc.

The interior memory element array of memory cell is split up into 4 middle storage block BLa, BLb, BLc and BLd.And storage block is split up into 2 little storage block CAL, CAR in each.Thereby the interior memory element display of memory cell promptly is made up of 8 storage blocks.

Line decoder RD is arranged in each of 4 middle storage block BLa, BLb, BLc and BLd separately.This line decoder RD selects among 2 little storage block CAL, the CAR one according to row address signal, and selects delegation's (word line 17) in a plurality of row from a selecteed storage block.

Column decoder CD0, CD1 are provided with 2 in a memory cell.This column decoder CD0, CD1 select one or more row of the memory element array of 4 storage block BLa, BLb, BLc and BLd respectively according to column address signal.

That is, selected certain column selection line 15-0,15-1 by column decoder CD0, CD1 after, be connected to this certain column selection line 15-0, the column select switch 16 of 15-1 promptly becomes conducting state, data line just is led to DQ buffer DQ by reading magnifier SA and data line to (below that this data line is right to being called the DQ line, to be different from data line to 14) 18 to 14 data or a plurality of data line to 14 data.

In this reference example, make to become a column decoder and select the such structure of two row.In this case, owing to have two column decoders, by the data of storage block BLa, BLb, BLc and BLd input and output 4 bits in each.Also in other words, by the data of memory cell input and output 16 bits (2 byte).These 16 bit data are by data bus 13 contact one of in data cell 11-0～11-3 and between the data input and output zone 12.

This gets amplifier SA and column select switch 16 is configured between little storage block CAL, the CAR of memory element array in separately middle storage block BLa, BLb, BLc and the BLd of memory element array.

Line decoder RD and DQ buffer DQ are by the ground configuration of the mutual subtend of sandwich memory element array CAL, CAR.It is one distolateral that column decoder CD0 is configured in two ends of the configuration direction of 4 middle storage block BLa, BLb, BLc and BLd that is column direction (data line to or the direction that prolongs of column selection line), and it is distolateral that column decoder CD1 then is configured in this two end another.

The adjacent ground connection configuration of element arrays controller CAC with line decoder RD.This element arrays controller CAC carries out the input-output operation of the data in the memory cell.

And then DQ buffer DQ back disposes the memory cell selector switch SEL that is used for the selection memory unit usually.

Data are led to the DQ line to 18 by data line to 14, behind reading magnifier SA and the column select switch 16.The DQ line is configured between little storage block CAL, the CAR of memory element array in separately middle storage block BLa, BLb, BLc and the BLd of memory element array 18.

Thereby data are exported from memory cell by DQ buffer DQ to move the back with perpendicular direction of 4 directions that middle storage block BLa, BLb, BLc and BLd disposed (column direction) of memory element array that is line direction (direction of word line extend) 18 by the DQ line.

Common data bus 13 is configured between memory cell 11-0,11-1 and memory cell 11-2, the 11-3 in 4 memory cells, extends on the direction of middle storage block BLa, the BLb of memory element, BLc and BLd configuration that is column direction.Data bus 13 is the data input and output path in 12 in memory cell 11-0～11-3 and data input and output zone.

In this reference example because be semiconductor memory with 16 bit types as prerequisite, constitute like this so data bus 13 is input and output by the data of carrying out 16 bits (2 byte) simultaneously.

In data input and output zone 12,, be formed with 16 imput output circuits (I/O) for the feasible input and output of carrying out the data of 16 bits (2 byte) simultaneously.

At first, memory cell selector switch SEL selects a memory cell from 4 memory cell 11-0～11-3.In a selected memory cell, carry out the accessing operation of memory element by address signal.

In the situation of data outputs (reading), from this selecteed memory cell, export 2 to 18 by the DQ line ⁿThe data of bit (for example 16 bits (2 byte)).From then on 2 of storage unit output ⁿThe bit data are led to data input and output zone 12 by data bus 13, and output to semiconductor memory (memory chip) outside by data input and output zone 12.

In the situation of data inputs (writing), 2 ⁿThe data of bit (for example 16 bits (2 byte)) are imported into this selecteed memory cell by data input and output zone 12, data bus 13.This is imported into 2 of this selecteed memory cell ⁿThe data of bit by the DQ line to 18 and reading magnifier SA be stored in the memory element of memory element array.

There is following shortcoming in the chip layout design of above-mentioned semiconductor memory.

The first, 4 memory cell 11-0～～11-3 shared data bus 13 run through the middle part of memory chip 10 and dispose, extend along column direction (data line to or the column selection line direction of extending).In this situation, increase the radical of data bus 13 pro rata with the bit pattern of semiconductor memory that is with the bit number that carries out input-output operation simultaneously, the zone of data bus 13 also increases.

For example, in the situation of the semiconductor memory of 16 bit types (* 16), data bus 13 must transmit the wiring of quantity of the data of 16 bit sizes, equally, in the situation of the semiconductor memory of 32 bit types (* 32), data bus 13 just becomes the wiring of the quantity of the data that must make to transmit 32 bit sizes.

The second, the DQ line that the middle storage block BLa～BLd in the memory cell is disposed separately only is configured between little storage block CAL, the CAR of memory element array 18, only extends at line direction (word line bearing of trend).In this case, increase the DQ line pro rata to 18 radical with bit number by a middle storage block output, the DQ line increases 18 zone.

For example, in a middle storage block, carry out under the situation of input and output of 4 bit data, the DQ line is to 18 wirings of quantity that just must be able to transmit the data of 4 bit sizes, equally, carry out in a middle storage block under the situation of data input and output of 8 bits, the DQ line is to 18 wirings that just become the quantity of the data that must be able to transmit 8 bit sizes.

The 3rd, in memory cell, dispose line decoder RD on the side of two of line direction ends, dispose DQ buffer DQ the opposing party.In this case, column decoder CD0 is configured in a side of two ends of column direction in memory cell, and column decoder CD1 is configured in the opposing party of these two ends.

Element arrays controller CAC is configured in a side of two ends of line direction with then crossing over 4 middle storage block BLa, BLb, BLc and BLd.

Thereby line decoder RD and element arrays controller CAC are owing to be configured in a side of two ends of line direction jointly, and the configuration of components of just feasible formation line decoder RD and element arrays controller CAC and wiring etc. are very complicated.

Fig. 3 represents the chip layout as the semiconductor memory of the present invention's second reference example.Fig. 4 shows the topological design in the memory cell of Fig. 3 in detail.

Come the semiconductor memory of 32 bit types (* 32) of the data of input and output 32 bits is simultaneously described with this reference example.

On a memory chip 10, dispose 4 memory cell 11-0～11-3.Be formed with memory element array CAL, CAR, element arrays controller CAC among each memory cell 11-0～11-3, also be formed with the peripheral circuit of line decoder RD, column decoder CD0, CD1 and DQ buffer (buffer that is called the input and output portion of memory cell) DQ etc. simultaneously.

Memory element array in memory cell is split up into 4 middle storage block BLa, BLb, BLc and BLd.Storage block then is split up into two little storage block CAL, CAR in each.Thereby the memory element array in memory cell promptly is made of 8 storage blocks.

Line decoder RD is arranged in each of 4 middle storage block BLa, BLb, BLc and BLd separately.This line decoder RD selects among two storage block CAL, the CAR one according to row address signal, and selects delegation's (word line 17) in a plurality of row from a selecteed storage block.

Column decoder CD0～CD3 has been set up 4 at a memory cell.This column decoder CD0～CD3 selects one or more row of the memory element array of 4 middle storage block BLa, BLb, BLc and BLd respectively according to column address signal.

Also be exactly, after selecting certain column selection line 15-0～15-3 by column decoder CD0-CD3, the column select switch 16 that is connected to this certain column selection line 15-0～15-3 promptly becomes conducting state, data line is sent to DQ buffer DQ by reading magnifier SA and data to line (following that this data line is right to being referred to as the DQ line, to be different from data line to 14) 18 to 14 data to 14 data or a plurality of data line.

In this reference example, select two row to constitute like this by a column decoder.In this case, owing to exist 4 column decoders, so by middle storage block BLa, BLb, BLc and the BLd data of input and output 8 bits separately.Also be exactly, by the data of memory cell input and output 32 bits (4 byte).These 32 bit data are come and gone by between data bus 13 in memory cell 11-0～11-3 and the data input and output zone 12.

Reading magnifier SA and column select switch 16 are configured between little storage block CAL, the CAR of memory element array in separately middle storage block BLa, BLb, BLc and the BLd of memory element array.

Line decoder RD and DQ buffer DQ by to be configured memory element array CAL, CAR with being clipped in the middle mutual subtend.Column decoder CD0 is configured in the side's side in two ends of the direction of 4 middle storage block BLa, BLb, BLc and BLd configuration that is column direction (data line to or the bearing of trend of column selection line), and column decoder CD1 then is configured in the opposing party's side in these two ends.

Element arrays controller CAC is contiguous to line decoder and is disposed.This element arrays controller CAC controls the input-output operation of data in the memory cell.

After being right after DQ buffer DQ, dispose the memory cell selector switch SEL that is used for the selection memory unit usually.

Data are being guided main DQ line to 18 by data line to 14, behind reading magnifier SA and the column select switch 16.The DQ line is configured between little storage block CAL, the CAR of memory element array in each middle storage block BLa, BLb, BLc and BLd of memory element array 18.

Thereby, data by the DQ line to 18 with the perpendicular direction of 4 directions that middle storage block BLa, BLb, BLc and BLd disposed (column direction) of memory element array, be that line direction (direction that word line extends) moves the back and exports from memory cell by DQ buffer DQ.

4 memory cell data shared buses 13 are configured between memory cell 11-0,11-1 and memory cell 11-2, the 11-3, in the direction of middle storage block BLa, the BLb of memory element array, BLc and BLd configuration, be to extend on the column direction.Data bus 13 is input and output paths of the data between memory cell 11-0～11-3 and the data input and output zone 12.

In this reference example and since be semiconductor memory with 32 bit types as prerequisite, constitute like this so data bus 13 is input and output according to the data of carrying out 32 bits (4 byte) simultaneously.

Input and output by the data of carrying out 32 bits (4 byte) simultaneously in data input and output zone 12 are formed with 32 imput output circuits (I/O) like that.

At first, from 4 memory cell 11-0～11-3, select a memory cell by memory cell selector switch SEL.In a selected memory cell, carry out the accessing operation of memory element according to address signal.

In the situation of data outputs (reading), export 2 to 18 from this selecteed memory cell by the DQ line ⁿThe data of bit (for example 32 bits (4 byte)).Thus 2 of memory cell output ⁿThe data of bit are guided data input and output zone 12 by data bus 13, and data input and output zone 12 is output to outside the semiconductor memory (memory chip) thus.

In the situation of data inputs (writing), 2 ⁿThe data of bit (for example 32 bits (4 byte)) are transfused in this selecteed memory cell by data input and output zone 12, data bus 13.This is imported into 2 in this selecteed memory cell ⁿThe data of bit by the DQ line to 18 and reading magnifier SA be stored in the memory element of memory element array into.

In the chip layout of above-mentioned semiconductor memory, have the same shortcoming of chip layout with the semiconductor memory of first reference example shown in Fig. 2 and Fig. 3.

That is, the first, with the bit pattern of semiconductor memory that is carry out the radical that the bit number of input-output operation simultaneously is increased in the common data bus 13 that is provided with in a plurality of memory cells pro rata, the zone of data bus 13 increases.The second, increase DQ line in the memory cell pro rata to 18 radical with the bit number of storage block from each memory cell output, the DQ line increases 18 zone.The 3rd, line decoder RD and element arrays controller CAC be because be configured in a side of two ends of line direction simultaneously, so that the configuration of the element of composition line decoder RD and element arrays controller CAC and wiring etc. just become is very complicated.

In addition in this reference example, because two ends of column direction dispose two column decoders separately, so the configuration of the element of formation column decoder CD0～CD3 and wiring etc. are also just very complicated.

Fig. 5 is the position of the memory cell of the semiconductor memory of first reference example of presentation graphs 1 and Fig. 2 and the position of data bus roughly.

Zone on the memory chip 10 is mainly occupied by memory cell 11-0～11-3 and data input and output zone (I/O) 12.One of being contiguous in two limits of in 4 limits of memory chip 10 that is column direction in data input and output zone 12 is disposed.

Memory element array in the memory cell is made of a plurality of little storage block that is configured in column direction, and constitutes a middle storage block by two little storage blocks.

Dispose word line that extends at line direction and data line and the column selection line that upward extends at column direction (direction of little storage block configuration) in each little storage block.

The DQ line follows direction to 18 and extends between two little storage blocks.DQ line between two little storage blocks only exists the quantity that can transmit 4 bit data to 18.

Data bus 13 is configured between memory cell 11-0,11-1 and memory cell 11-2, the 11-3, and extends on column direction.This data bus 13 constitutes like that by the data that can transmit 16 bits (2 byte).

The variation of the chip layout of the semiconductor memory of first reference example of Fig. 6 presentation graphs 1 and Fig. 2.The chip layout design of the semiconductor memory of the detailed presentation graphs 6 of Fig. 7.

The chip layout of this chip layout and Fig. 1 and Fig. 1 relatively has following some difference.

The first, constitute a memory cell (main storage unit) by two sub-memory cells.

That is, main storage unit 11-0 is made of quantum memory unit 11-0-#0,11-0-#1, main storage unit 11-1 is made of memory cell 11-1-#0,11-1-#1, main storage unit 11-2 by quantum memory unit 11-2-#0,11-2-#1 constitutes and main storage unit 11-3 is made of quantum memory unit 11-3-#0,11-3-#1.

Quantum memory unit 11-0-#0,11-0-#1 select circuit to select by memory cell simultaneously.Under quantum memory unit 11-0-#0, the selecteed situation of 11-0-#1, do not select remaining quantum memory unit.Equally, for example under quantum memory unit 11-1-#0, the selecteed situation of 11-1-#1, also no longer select remaining quantum memory unit.

And, constitute one group by 4 sub-memory cell 11-0-#0,11-1-#0,11-2-#0 and 11-3-#0, constitute one group by 4 sub-memory cell 11-0-#1,11-1-#1,11-2-#1 and 11-3-#1.

Also in other words, in quantum memory unit 11-0-#0,11-1-#0,11-2-#0,11-3-#0 one group, carry out the input and output of the data of 8 bits simultaneously, in quantum memory unit 11-0-#1,11-1-#1,11-2-#1 and 11-3-#1 one group, carry out the input and output of the data of 8 bits simultaneously.

The second, in a sub-memory cell, constitute like that by the data input and output of carrying out 8 bits (1 byte).

The topological design of quantum memory unit as with the topological design of the memory cell of Fig. 1 and Fig. 2 relatively, difference is that a column decoder CD is only arranged.Because in the situation of this example, carry out the input and output of the data of 8 bits by a sub-memory cell, so column decoder CD one just enough.But the semiconductor memory of column decoder CD and Fig. 1 and Fig. 2 is similarly selected two row, also just becomes the input and output of carrying out 2 bit data among storage block BLa, BLb, BLc and the BLd in each of memory element array.

Memory element array CAL, CAR in the quantum memory unit, line decoder RD, the DQ line is then almost identical with layout in the memory cell of the semiconductor memory of Fig. 1 and Fig. 2 with the layout of DQ buffer DQ to 18.

The 3rd, data imput output circuit (I/O) 12a, 12b follow direction elongation ground and are disposed at the middle part of memory chip 10, data bus 13a is configured in the both sides of data imput output circuit 12a in quantum memory unit 11-0-#0,11-1-#0,11-2-#0 and 11-3-#0 one group, data bus 13b is configured in the both sides of data input and output 12b in quantum memory unit 11-0-#1,11-1-#1,11-2-#1 and 11-3-#1 one group.

Along extending on the column direction, be connected to data imput output circuit 12a, the 12b of memory chip 10 middle bodies between each comfortable quantum memory unit of data bus 13a, 13b.This data bus 13a ', 13b constitute like this by the data that can transmit 8 bits separately.

In the semiconductor memory of such chip layout, for example, when chooser memory cell 11-0-#0,11-0-#1, carry out giving and accepting of 8 bit data by data bus 13a between quantum memory unit 11-0-#0 and data imput output circuit 12a, carry out giving and accepting of 8 bit data by data bus 13b between quantum memory unit 11-0-#1 and data imput output circuit 12b.

The variation of the chip layout of the semiconductor memory of first reference example of Fig. 8 presentation graphs 1 and Fig. 2.The chip layout of detailed presentation graphs 8 semiconductor memories of Fig. 9.

This chip layout and the chip layout of Fig. 1 and Fig. 2 these points of having compared are different.

That is, main storage unit 11-0 is made of quantum memory unit 11-0-#0,11-0-#1, main storage unit 11-1 is made of quantum memory unit 11-1-#0,11-1-#1, main storage unit 11-2 is made of quantum memory unit 11-2-#0,11-2-#1, and main storage unit 11-3 is made of quantum memory unit 11-3-#0,11-3-#1.

Quantum memory unit 11-0-#0,11-0-#1 select circuit to select simultaneously by memory cell.Under quantum memory unit 11-0-#0, the selecteed situation of 11-0-#1, no longer select remaining quantum memory unit.Be that remaining quantum memory unit is also indiscriminate under the situation about selecting equally, for example at quantum memory unit 11-1-#0,11-1-#1.

And by 4 sub-memory cell 11-0-#0,11-1-#0,11-2-#0,11-3-#0 form one group, form one group by 4 sub-memory cell 11-0-#1,11-1-#1,11-2-#1 and 11-3-#1.

Also in other words, at quantum memory unit 11-0-#0,11-1-#0, carry out the input and output of the data of 8 bits in one group of 11-2-#0 and 11-3-#0 simultaneously, in quantum memory unit 11-0-#1,11-1-#1,11-2-#1 and 11-3-#1 one group, carry out the input and output of the data of 8 bits simultaneously.

Input and output by the data of carrying out 8 bits (1 byte) in the second, one sub-memory cell constitute like that.

The layout of this memory cell is compared with the layout of the memory cell of Fig. 1 and Fig. 2, and dissimilarity is that a column decoder CD is only arranged.Because in the situation of this example, a sub-memory cell carries out the data input and output of 8 bits, so only exist a column decoder CD also enough.But column decoder CD is also same with the semiconductor memory of Fig. 1 and Fig. 2, selects 2 row, makes the input and output of carrying out the data of 2 bits in each of memory element array among storage block BLa, BLb, BLc and the BLd.

Memory element array CAL, CAR in the memory cell, line decoder RD, all the topological design with the semiconductor memory of Fig. 1 and Fig. 2 is identical with the topological design of DQ buffer DQ to 18 for the DQ line.

The 3rd, data bus 13a makes column direction and extends the ground configuration in the group of sub-storage unit 11-0-#0,11-1-#0,11-2-#0 and 11-3-#0, data bus 13b makes column direction and extends the ground configuration in the group of sub-storage unit 11-0-#1,11-1-#1,11-2-#1 and 11-3-#1.

That is, data bus 13a prolongs along column direction from the data imput output circuit 12a that is configured in the column direction end between the quantum memory unit, and data bus 13b extends along column direction from the data imput output circuit 12b that is configured in the column direction end between the quantum memory unit.

Data bus 13a, 13b all constitute by the data that can transmit 8 bits separately like that.

In the semiconductor memory of such chip layout, for example under the selecteed situation of quantum memory unit 11-0-#0,11-0-#1,12 of quantum memory unit 11-0-#0 and data imput output circuits carry out the giving and accepting of data of 8 bits by data bus 13a, and carry out the giving and accepting of data of 8 bits between sub-storage unit 11-0-#1 and data imput output circuit 12b by data bus 13b.

Figure 10 represents the chip layout design as the semiconductor memory of first embodiment of the invention.Figure 11 represents the topological design in the memory cell of Figure 10 in detail.

With this embodiment the semiconductor memory of 16 bit types (* 16) of the data of 16 bits of input and output is simultaneously described.

On a memory chip 10, dispose 4 memory cell 11-0～11-3.In each memory cell 11-0～11-3, form memory element array CAL, CAR, element arrays controller CAC, also forming the peripheral circuit of line decoder RD, column decoder CD0, CD1 and DQ buffer (buffer that is called the input and output portion of memory cell) DQ etc.

Memory element array in memory cell is split up into 4 middle storage block BLa, BLb, BLc and BLd.And storage block is divided into two little storage block CAL, CAR in each.Thereby the memory element array in memory cell is made of 8 storage blocks.

Line decoder RD is arranged in each of 4 middle storage block BLa, BLb, BLc and BLd respectively.This line decoder RD selects among two little storage block CAL, the CAR one according to row address signal, and by selecting delegation's (word line 17) in the multirow in the selecteed storage block.

The selection of the little storage block of memory element array with on the either party in two word line 19a, 19b in addition high voltage carry out.For example, as high voltage in addition on word line 19a, switch 20a just becomes conducting state, and little storage block CAL promptly is selected.This moment, because be carried out low-voltage, so switch 20b is a cut-off state, little storage block CAR promptly was not selected on word line 19b.

The two is set at column decoder CD0, CD1 in the memory cell.This column decoder CD0, CD1 select one or more row of the memory element array of 4 middle storage block BLa, BLb, BLc and BLd separately according to column address signal.

For example when selecting column selection line 15 by column decoder CD1, two column select switches 16 that are connected to this column selection line 15 just become conducting state.Thereby, the data of 2 bits promptly from two data lines being connected to this two column select switch 16 to 14 by reading magnifier SA and column select switch 16 be output to data line to (below that this data line is right to being called local DQ line) 18a to be different from data line to 14.

In the present embodiment, select two row to constitute like that by a column decoder.In this case because have two column decoders, thus from each storage block BLa, BLb, BLc and BLd data of input and output 4 bits separately.Also in other words, by the data of memory cell input and output 16 bits (2 byte).

Line decoder RD and element arrays controller CAC are disposed with mutual subtend ground that memory element array CAL, CAR are clipped in the middle.That is, line decoder RD is configured in the direction perpendicular with the configuration direction of 4 middle storage block BLa, BLb, BLc and BLd, be on side's side of two ends of line direction (direction that word line 17,19a, 19b prolong), element arrays controller CAC then is configured on the opposing party's side in these two ends.

Element arrays controller CAC is used to carry out the control to the input-output operation of the data in the memory cell.

Column decoder CD0, CD1 be configured in 4 middle storage block BLa, BLb, BLc and BLd the configuration direction, be on the side of a side in two ends of column direction (data line to or the column selection line direction of extending).

Two column decoder CD0, CD1 dispose on line direction like that by dividing the row of bearing memory element array by each column decoder CD0, CD1 equally.

DQ buffer DQ is configured in two ends of column direction (data line to or the column selection line direction of extending) on the opposing party's side.That is, column decoder CD0, CD1 and DQ buffer DQ are disposed sample with mutual subtend ground that memory element array CAL, CAR are clipped in the middle.

After being right after DQ buffer DQ, dispose usually and make the memory cell selector switch SEL that memory cell is selected usefulness.

Data are led to local DQ line to 18a by data line to 14, behind reading magnifier SA and the column select switch 16.Local DQ line is configured between little storage block CAL, the CAR of memory element array in separately middle storage block BLa, BLb, BLc and the BLd of memory element array 18a.

Thereby local DQ line is gone up at line direction (direction that word line extends) 18a and is extended.

And data line is extended the ground configuration to (this data line of following title is right to being overall DQ line, to be different from data line to 14) 18b with column direction on little storage block CAL, the CAR of memory element array.Overall situation DQ line is connected to local DQ line to 18a to the end of 18b by switch 21, and the other end then is connected to DQ buffer DQ.

The conduction and cut-off of switch 21 is controlled by control signal CON.

4 total data buss 13 of memory cell are configured between memory cell 11-0,11-2 and memory cell 11-1, the 11-3, extend on line direction.This data bus 13 becomes the data input and output path between memory cell 11-0～11-3 and the data input and output zone 12.

In the present embodiment, because be that semiconductor memory with 16 bit types is a prerequisite, so data bus 13 constitutes like that by the input and output of the data of carrying out 16 bits (2 byte) simultaneously.

Data input and output zone 12 is configured in the side's side in two ends of line direction of memory chip 10.In this data input and output zone 12,, be formed with 16 imput output circuits (I/O) for making the input and output of the data of carrying out 16 bits (2 byte) simultaneously.

The data input-output operation of above-mentioned semiconductor memory carries out as following.

At first, memory cell selector switch SEL selects a memory cell from 4 memory cell 11-0～11-3.In a selecteed memory cell, carry out the accessing operation of memory element by address signal.

Under the situation of data outputs (reading), 2 ⁿThe data of bit (for example 16 bits (2 byte)) are exported by this selecteed memory cell 18b 18a and overall DQ line by local DQ line.Thus 2 of memory cell output ⁿThe data of bit are led to data input and output zone 12 by data bus 13, and are outputed to the outside of semiconductor memory (memory chip) by data input and output zone 12.

Under the situation of data inputs (writing), 2 ⁿThe data of bit (for example 16 bits (2 byte)) are imported in this selecteed memory cell by data input and output zone 12, data bus 13.This is imported into 2 of this selecteed memory cell ⁿThe bit data are stored the into memory element of memory element array to 18a, overall DQ line to 18b and reading magnifier SA by local DQ line.

The chip layout of above-mentioned semiconductor memory has following characteristics.

The first, element arrays controller CAC and line decoder RD are by to be clipped in the middle memory element array CAL, CAR and mutual subtend ground is disposed in the end of line direction.Column decoder CD0, CD1 and DQ buffer DQ are then by to be clipped in the middle memory element array CAL, CAR and mutual subtend ground is disposed in the end of column direction.

That is element arrays controller CAC, line decoder RD, column decoder CD0, CD1 and DQ buffer DQ can be in abutting connection with the border district configurations of any memory element array CAL, CAR.

Thereby, can make the configuration of the element that easily carries out composed component array control unit CAC, line decoder RD, column decoder CD0, CD1 and DQ buffer DQ and wiring etc.

The second, make the data can be at memory cell by being arranged on overall DQ line that local DQ line that line direction extends extends to 18a with at column direction to 18b, having made by the structure of the end output of the column direction of memory cell.

That is, DQ buffer DQ can be arranged on the end of the column direction of memory cell, so can realize above-mentioned first feature.

And, as present embodiment, even carrying out the bit number of input and output in the middle storage block of one of memory element array is the situation of 4 bits, also the local DQ line that is configured between little storage block CAL, CAR can be set at column decoder CD0 side 2 bits 18a, at column decoder CD1 side 2 bits.

This is for column decoder CD0, CD1 and memory element array are disposed at line direction in abutting connection with ground, and the input and output of data are carried out in the end of the column direction of memory cell.

Thereby can reduce the local DQ line zone required, specifically, can make half of reference example that required zone is become Fig. 1 and Fig. 2 because of configuration DQ line 18a.

And overall DQ line is to 18b, carries out in a middle storage block under the situation of input and output of data of 4 bits, must become the number that the data that can carry out 16 bits transmit in memory cell.Thereby overall DQ line because be configured on memory element array CAL, the CAR, is used to dispose overall DQ line zone to 18b and needn't reset to 18b.

The 3rd, data bus 13 is configured in and does the line direction extension between memory cell 11-0,11-2 and memory cell 11-1, the 11-3.This is on one of in two ends that the DQ buffer DQ in the memory cell are configured in column direction.

As a result, rely on planning just can reduce the wiring quantity of composition data bus 13, thereby can dwindle the zone of the data bus 13 that on memory chip 10, occupies memory cell and the configuration of data imput output circuit.

Figure 12 represents to constitute the structure example of

switch

16,21 of the semiconductor memory of Figure 10 and Figure 11.

Column select switch 16 is made of N-channel MOS transistor N1, N2.The grid of MOS transistor N1, N2 is connected to column selection line 15, and a side in source-drain region is connected to reading magnifier SA, and the opposing party in source-drain region is connected to local DQ line to 18a.

Switch 21 is made of N-channel MOS transistor N3, N4.The grid of MOS transistor N3, N4 is connected to control line 22, and a side in source-drain region is connected to local DQ line to 18a, and the opposing party in source-drain region is connected to DQ buffer DQ.

Figure 13 represents the example of structure of column decoder of the semiconductor memory of Figure 10 and Figure 11.

In this example, describe as an example with column decoder CD0.

Column address signal A0～A10 is imported into column decoder CD0.Column address signal A0～A7 with preposition code translator (NAND NAND circuit) 23-1,23-2 ,～output signal level of any preposition code translator among the 23-N is as " L (low) ", with the output signal level of all the other whole preposition code translators as " H (height) ".Column address signal signal A8-A10 then with code translator 24-1,24-2 ,～24-M in the output signal level of any code translator as " L (low) ", with the output signal level of all the other whole code translators as " H (height) ".

The output signal of preposition code translator 23-1,23-2,23-N be imported into storage block 25-1,25-2 ,～25-N, code translator 24-1,24-2 ,～output signal of 24-M be imported into whole storage block 25-1,25-2 ,～25-N.

NOR NOR circuit 26-0,26-1 ,～be transfused among the 26-7 preposition code translator 23-1,23-2 ,～output signal of 23-N and code translator 24-1,24-2 ,～output signal of 24-M.

For example, level that preposition code translator 23-1 goes out signal for the output signal level of " L ", code translator 24-1 under the situation of " L ", only have the output signal level of NOR circuit 26-0 to become " H ", the output signal level of all the other whole NOR circuit all becomes " L ".

NOR circuit 26-0,26-1 ,～output signal of 26-7, during the level of control signal L is " H ", by transmission gate 27-0,27-1 ,～27-7 be input to latch cicuit 28-0,28-1 ,～28-7.

Latch cicuit 28-0,28-1 ,～output signal of 28-7, during the level of control signal T is " H ", by AND "AND" circuit 29-0,29-1 ,～29-7 is added on the column selection line 15.

For example, the output signal level that at the output signal level that presets code translator 23-1 is " L ", code translator 24-1 is under the situation of " L ", in the column selection line 15 only the level of a column selection line CSL0 become " H ", the level of all the other whole column selection lines all becomes " L ".The column select switch that is connected to the column selection line of " H " level becomes conducting state.

BW is the storage block write signal.The level of this storage block write signal BW is " L " when normal mode, then becomes " H " when storage block writes pattern.Also in other words, when storage block writes pattern, all code translator 24-1,24-2 ,～output signal level and the column address signal A8-A10 of 24-M irrespectively become " L ".

Thereby for example the output signal level at preposition code translator 23-1 is under the situation of " L ", all becomes " H " by whole level of 8 column selection line CSL0～CSL7 of storage block 25-1 control.The column select switch that is connected to the column selection line of " H " level becomes conducting state.

Just be that unit carries out writing of data thus with the storage block.

Figure 14 represents that the memory cell of the semiconductor memory of Figure 10 and Figure 11 selects the example of the structure of circuit SEL.

Memory cell selects circuit SEL to be made of transmission gate T01, the T02, T11, T12, T21, T22, T31 and the T32 that are connected between DQ buffer DQ and the data bus 13.Transmission gate T01, T02, T11, T12, T21, T22, T31 and T32 are made of N-channel MOS transistor and P channel MOS transistor.

In memory cell 11-0, memory cell select signal BNK0 ,/BLK0 is imported into memory cell and selects circuit SEL.That is the transistorized grid of N-channel MOS that constitutes transmission gate T01, T02 is transfused to memory cell and selects signal BNK0, and the grid that constitutes the P channel MOS transistor of transmission gate T01, T02 is transfused to memory cell and selects signal/BNK0.

Equally, in memory cell 11-1, memory cell select signal BNK1 ,/BLK1 is imported into memory cell and selects circuit SEL, in memory cell 11-2, memory cell select signal BNK2 ,/BLK2 is imported into memory cell and selects circuit SEL, with in memory cell 11-3, memory cell select signal BNK3 ,/BLK3 is imported into memory cell and selects circuit SEL.

Memory cell is selected signal BNK0～BNK3, and wherein any level becomes " H ", and then remaining level promptly all becomes " L ".

For example, when memory cell 11-0 was selected, memory cell selected the level of signal BNK0 to become " H ", and memory cell selects the level of signal BNK1, BNK2 and BNK3 all to become " L ".Only have the DQ buffer DQ of memory cell 11-0 to be connected to data bus 13 this moment, and the DQ buffer DQ of memory cell 11-1,11-2 and 11-3 then cuts off with data bus 13.

The result just becomes and only may carry out data between memory cell 11-0 and data imput output circuit 12 and give and accept.

Figure 15 represents the topology example of data imput output circuit 12 of the semiconductor memory of Figure 10 and Figure 11.

A data imput output circuit to the data input and output of carrying out 1 bit describes in this example.That is for example in the semiconductor memory of 16 bit types (* 16), this routine data imput output circuit just needs 16.

This data imput output circuit mainly writes buffer DBWBF, output latch circuit 30, output circuit 31 and output state 32 by data bus reading magnifier DBSAMP, data bus and constitutes.

Data bus writes buffer DBWBF and writes fashionable application carrying out data.

Control signal NW is input to sync pulse inverter CI1, and control signal WX is transfused to sync pulse inverter CI2, CI5.In the data of normal manipulation mode write, the level of control signal NW became " H ", and synchronizing pulse gun stocks CI1 is activated.And during control signal WX was " H " level, (m was 0,1 to input data (writing data) RWDm ... or 15) be guided data bus 13 by synchronizing pulse gun stocks CI1, latch cicuit LA and sync pulse inverter CI2, CI5.These data are imported into selecteed memory cell by data bus 13.

Control signal BW is imported into sync pulse inverter CI3.The data that write pattern in storage block are write fashionable, and the level of control signal BW becomes " H ", and sync pulse inverter CI3 is activated.And during control signal WX became " H " level, (m was 0,1 to color register data CRm ... or 15) be led to data bus 13 by impulsive synchronization phase inverter CI3, latch cicuit LA and sync pulse inverter CI2, CI5.These data are imported into selecteed memory cell by data bus 13.

Color register data CRm is supplied with by color register.In color register, store the data style that when storage unit writes pattern, writes a plurality of memory elements simultaneously in advance.Color register generally is set in the video memory, when the data that are used at the same time the style that will be predetermined write a plurality of memory element.The content of color register (data style) changes in the pattern of the data of change color register.

Control signal TW is input to sync pulse inverter CI4.Write fashionablely in the data of test pattern, control signal TW becomes " H " level, and sync pulse inverter CI4 is activated.And during control signal WX was " H " level, the output signal of anticoincidence circuit EX was led to data bus 13 by sync pulse inverter CI4, latch cicuit LA and synchronizing pulse phase inverter CI2, CI5.These data are imported into selecteed memory cell by data bus 13.

Be transfused to color register data/CRm and data RWD0 among the anticoincidence circuit EX.That is the Data Styles of using when obtaining test pattern by color register constitutes in this example.

About the back explanation of the employed test circuit of the semiconductor storage unit of present embodiment.

Data bus reading magnifier DBSAMP uses when reading carrying out data.

This data bus reading magnifier DBSAMP contains N raceway groove operational amplifier SAN and P raceway groove operational amplifier SAP.Data bus reading magnifier DBSAMP is activated when activation signal RENBL becomes " H " level, and activation signal RENBL is not activated when being " L " level.

When activation signal RENBL was " L " level, sync pulse inverter CI6 was not activated, and data bus reading magnifier DBSAMP separates from read/write data line RWD.Read/write data line RWD both had been that output data (read data) path also is input data (write data) path.

Precharge transistor PR output data RWDm (m is 0,1 ... or 15) be output to before the read/write data line RWD this read/write data line RWD precharge is become " H " level.

Output data RWD one is by data bus reading magnifier DBSAMP output, and this output data RWDm promptly is imported into output circuit by output latch circuit 30.

Output latch circuit 30 is resetted by reset signal/RS.Synchronizing signal QST is input to output circuit 31.That is (m is 0,1 to output data DQm ... or 15) synchronously export with synchronizing signal QST, be output to outside the memory chip by output state 32 from output circuit 31.

The part of the test circuit that NAND circuit 33 and anticoincidence circuit 34 uses when making test pattern.

The output data of output latch circuit 30 and test signal ReDT are input in the NAND circuit 33.Test signal ReDT is " H " level during test pattern.The output signal of NAND circuit 33 and color register data/CRm are input in the anticoincidence circuit 34.34 outputs of this anticoincidence circuit show that test result is that (m is 0,1 for the output signal TRDm of "Yes" or " non-" ... or 15).

Figure 16 represents all structures of the test circuit that adopted in the semiconductor memory of the present invention.Among Figure 16, with the structural detail corresponding structure element of the data imput output circuit of Figure 15 all be marked with Figure 15 in the identical symbol of used symbol.

This test circuit is a prerequisite with the test of the semiconductor memory that carries out 32 bit types (* 32).

The test circuit of present embodiment is made of with change-over circuit 100 and defeated output circuit 200 on probation NAND circuit 33, anticoincidence circuit 34, test.

In test pattern, test signal ReDT becomes " H " level.(m is 0,1 to the output signal TRDm of anticoincidence circuit 34 ... or 15) be imported into test change-over circuit 100.

32 bit data of test result are represented in test with input in the change-over circuit 100.This test with change-over circuit 100 with these 32 bit data sequentially (serial) output to test usefulness output circuit 200.

Test is activated when control signal TQST-becomes " H " level with output circuit 200.At this moment, control signal QST is " L " level, and the employed output circuit of normal mode 31 is by deactivation.

Figure 17 represents the details of employed test circuit in the semiconductor memory of the present invention.In Figure 17, all be marked by the identical symbol of putting in marks with Figure 15 with the structural detail corresponding structure element of the data imput output circuit of Figure 15.

This test circuit is made prerequisite with the test of the semiconductor memory of 32 bit types (* 32).

Storage in advance has the data (0,1,0 of regulation pattern in the color register 35 ... 1).But the content of color register 35 (pattern) can be come change by input control signal Z in the pattern of change pattern.

Data/the CR0 of input color register 35 among the anticoincidence circuit EX ,/CR1 ,～CR31 and input data RWD0.The level of input data W D0 can be " L ", also can be " H ".

For example, when input data RWD is " L " level, be transfused to the data of " H " in the element arrays 0, be transfused to " L " data in the element arrays 1, be transfused to " H " data in the element arrays 2, be transfused to the data of " L " in the element arrays 31.

And under all normal situation of whole element arrays 0～31, naturally also just by

element arrays

0,1,2 ... 31 export " H ", " L ", " H " respectively ... the data of " L ".

In this case, the output signal TRDm of anticoincidence circuit 34 all becomes " L ".

The output signal TRDm of this anticoincidence circuit 34 exports to the memory chip outside as judgement signal DQ0 by test pattern change-over circuit 100 and test pattern output circuit 200.

Carrying out test result in estimating mode switching circuit 100 is the judgement of OK (element arrays is normal) or NG (element arrays is unusual).At element arrays just often, because the output signal TRDm of anticoincidence circuit 34 is " L " level entirely, promptly by the output signal of test pattern change-over circuit 100 output " L " level, test result is judged as OK.

On the other hand, when element arrays was unusual, the level of output signal TRDm of " unusually " circuit 34 that receives the output data of unusual element arrays just became " H ".At this moment, the output signal of test pattern change-over circuit 100 becomes " H " level, and judges that test result is NG.

When test result is NG, check which element arrays is abnormal in the element arrays 0～32.This inspection can be latched in latch cicuit LATCH0～31 by the output signal with anticoincidence circuit 34, these data that are latched series read-out are successively carried out.

According to such test circuit, the data of color register 35 are applied in the test of semiconductor memory, when test result is NG simultaneously, make serial output show the bad signal of memory element of a certain element arrays.

Thereby, with the test circuit of present embodiment, can when making test circuit itself simple in structure, only need a test usefulness contact pin (terminal) of only in test, using just enough, memory chip is dwindled and reduce cost.

Figure 18 represents the topology example of the test pattern change-over circuit 100 of Figure 17.

Whether " XNOR " circuit 36 for checking in the element arrays 0～31 in-problem part.

This " XNOR " circuit 36 by anticoincidence circuit EX-OR0, EX-OR1 ,～EX-OR30 and sync pulse inverter CI7 constitute.

Output signal TRD0～TRD31 be imported into anticoincidence circuit EX-OR0, EX-OR1 ,～EX-OR30.When output signal TRD0～TRD31 was " L " level entirely, the output signal level of anticoincidence circuit EX-OR30 became " L ".

Control signal/SRCH one becomes " H " level, and sync pulse inverter CI7 promptly is activated.At this moment, the output signal ReDRD of expression test result exports from sync pulse inverter CI7.

When output signal TRD0～TRD31 was " L " level entirely, output signal ReDRD became " H " level.That is, show that with output circuit output test result is the signal of OK by test.

When at least one level of output signal TRD0～TRD31 was " H ", output signal ReDRD promptly became " L " level.That is test shows that with output circuit output test result is the signal of NG.

Which element arrays existing problems or not good element arrays on-off circuit portion 37 for being used for specifying when estimating the result for NG.

On-off circuit portion 17 is made of transmission gate TG0, TG1～TG31 and sync pulse inverter CI8, and transmission gate TG0, TG1～TG31 constitute by N-channel MOS transistor and P channel MOS transistor separately.Disconnected/logical action of transmission gate TG0, TG1～TG31 is by 38 controls of sequence selection device.

Sequence selection device 38 is activated when control signal SRCH is " H " level, synchronously exports control signal Q0, Q1～Q31 with clock signal clk.One is " H " level among control signal Q0, the Q1～Q31, and all the other all are " L " level.The control signal of " H " level by Q0 to Q31 in turn (serial) conversion.That is data TRD0, TRD1～TRD31 order (serial) is by sync pulse inverter CI8 output.

Sync pulse inverter CI8 is activated when control signal SRCH is " H " level.

The action of semiconductor memory of the present invention during Figure 19 and Figure 20 represent to test.

In concluding test pattern, check in the semiconductor memery device array whether have problems.In the serial search test pattern, specify the inspection of the element arrays of existing problem in a plurality of element arrays.

/ RE determines row address signal is got moment in the semiconductor memory into.That is, /row address signal was taken in the semiconductor memory when RE was " L " level.

/ CE determines column address signal is taken into moment in the semiconductor memory.That is, /column address signal was taken in the semiconductor memory when CE was " L " level.

Concluding test pattern can be for example carry out by test signal TEST being set at " L " level during for " L " level at/CE.

The serial search test pattern can be for example carried out by test signal TEST being set at " H " level during for " L " level at/CE.

Figure 21 represents the chip layout design as the semiconductor memory of second embodiment of the invention.

In this embodiment, 32 bit type (* 32) semiconductor memories to the input and output of the data that can carry out 32 bits simultaneously are illustrated.

Dispose 4 memory cell 11-0～11-3 on the memory chip 10.Be formed with memory element array CAL, CAR and element arrays controller CAC among each memory cell 10-0～11-3, and be formed with the peripheral circuit of line decoder RD, column decoder CD0～CD3 and DQ buffer (buffer that is called memory cell input and output portion) DQ etc.

The interior memory element array of memory cell is split up into 4 middle storage block BLa, BLb, BLc and BLd.And storage block is divided into two little storage block CAL, CAR in each.Thereby the interior memory element array of memory cell promptly is made of 8 storage blocks.

Line decoder RD is arranged in each of 4 middle storage block BLa, BLb, BLc and BLd separately.This line decoder RD is according to one among row address signal selection two little storage block CAL, CAR, and a plurality of middle delegation's (word line) of selecting from a storage block of selecting.

Column decoder CD0～CD3 is provided with 4 in a memory cell.Column decoder CD0～CD3 selects one or more row of the memory element array of 4 middle storage block BLa, BLb, BLc and BLd respectively according to column address signal.

For example, after having selected the column selection line by column decoder CD0, two column select switches that are connected to this column selection line promptly become the state of leading.Then promptly from two data lines being connected to this two column select switch to the data of exporting 2 bits to local DQ line to 18a.

In the present embodiment, a column decoder is by selecting two row to constitute like this.In this case, because have 4 column decoders, storage block BLa, BLb, BLc and BLd data of 8 bits of input and output separately therefrom.Also in other words, import the data of 32 bits (4 byte) by memory cell output.

Reading magnifier and column select switch are configured between little storage block CAL, the CAR of memory element array in separately middle storage block BLa, BLb, BLc and the BLd of memory element array.

Line decoder RD and element arrays controller CAC are configured like that with mutual subtend ground that memory element array CAL, CAR are clipped in the middle.That is, line decoder RD is configured in side's side in two ends with perpendicular direction of the direction of 4 middle storage block BLa, BLb, BLc and BLd configuration that is line direction (direction that word line extends), and element arrays controller CAC then is configured in the opposing party's side in this two end.

Element arrays controller CAC carries out the input-output operation of the data in the memory cell.

Column decoder CD0～CD3 be configured in 4 middle storage block BLa, BLb, BLc and BLd configuration direction, be the side's side in two ends of column direction (data line to or the column selection line direction of extending).

4 column decoder CD0～CD3 make the quartern by the row of the memory element array that each column decoder CD0～CD3 is born and are configured on the line direction like that.

DQ buffer DQ is configured in the opposing party's side in two ends of column direction.That is column decoder CD0～CD3 and DQ buffer DQ are configured like that by mutual subtend that memory element array CAL, CAR are clipped in the middle.

Data are being led to local DQ line to 18a by data line after to, reading magnifier and column select switch.Local DQ line is configured between little storage block CAL, the CAR of memory element array in each middle storage block BLa, BLb, BLc and BLd of memory element array 18a.

Thereby local DQ line prolongs at line direction (direction of word line extend) 18a.

And overall DQ line extends ground configuration with column direction to 18b on little storage block CAL, the CAR of memory element array.Overall situation DQ line is connected to local DQ line to 18a to the end of 18b by switch, and the other end then is connected to DQ buffer DQ.

4 common data buss 13 of memory cell are configured between memory cell 11-0,11-2 and 11-1, the 11-3, follow direction and prolong.Data bus 13 is as the data input and output path between memory cell 11-0～11-3 and the data input and output zone 12.

In the present embodiment, owing to be as prerequisite, so data bus 13 constitutes like that by the data input and output of carrying out 32 bits (4 byte) simultaneously with the semiconductor memory of 32 bit types.

Data input and output zone 12 is configured in the side's side in two ends of line direction of memory chip 10.In data input and output zone 12, form 32 imput output circuits (I/O) of the input and output of the data that can carry out 32 bits (4 byte) simultaneously.

At first, the memory cell selector switch is selected a memory cell from 4 memory cell 11-0～11-3.In a selecteed memory cell, carry out the accessing operation of storage unit according to address signal.

In data output (reading) situation, the data of 32 bits (4 byte) are exported from this selecteed memory cell 18b 18a and overall DQ line by local DQ line.32 bit data of memory cell output from then on are guided data input and output zone 12 by data bus 13, and output to outside the semiconductor memory (memory chip) from data input and output zone 12.

In the situation of data inputs (writing), 32 bits (4 byte) data are imported into the memory cell that this is selected by data input and output zone 12, data bus 13.The 32 bit data that are transfused to a so far selecteed memory cell are stored in the memory element of memory element array into 18b and reading magnifier 18a, overall DQ line by local DQ line.

The first, element arrays controller CAC and line decoder RD are clipped in the middle memory element array CAL, CAR and mutually dispose like that to subtend on the end of line direction.Column decoder CD0～CD3 and DQ buffer DQ are clipped in the middle memory element array CAL, CAR and mutually dispose like that to subtend on the end of column direction.

That is element arrays controller CAC, line decoder RD, column decoder CD0～CD3 and DQ buffer DQ can be adjacent to be configured in one side of any one memory element array CAL, CAR.

Thereby, make composed component array control unit CAC, line decoder RD, column decoder CD0～CD3 and DQ buffer DQ element configuration and the wiring can easily carry out.

The second, in memory cell, be arranged on local DQ line that line direction extends to 18a and the overall DQ line that on column direction, extends to 18b, so that data constitute in this wise from the end input and output of the column direction of memory cell.

That is, owing to DQ buffer DQ can be arranged on the end of the column direction of memory cell, so can realize above-mentioned first characteristics.

And, as present embodiment, even the input and output of carrying out in a middle storage block of memory element array are under the situation of 8 bits, the local DQ line that also can be configured between little storage block CAL, the CAR is set at column decoder CD0 side 2 bits 18a, similarly at column decoder CD1～each 2 bit of CD3 side difference.

This is for the adjacent ground connection of column decoder CD0～CD3 and memory element array is configured on the line direction, and the input and output of data are carried out in the end of the column direction of memory component.

Thereby can reduce local DQ line to the necessary zone of 18a.

And, when overall DQ line carries out the input and output of data of 8 bits in a middle storage block to 18b, just must the quantity of transmission that can carry out the data of 32 bits in a memory cell.Thereby, owing to overall DQ line is configured on memory element array CAL, the CAR 18b, so there is no need to be re-set as the overall DQ line of the configuration zone required to 18b.

The 3rd, data bus 13 is configured in and follows the direction extension between memory cell 11-0,11-2 and 11-1, the 11-3.This is on one of in two ends that the DQ buffer DQ in the memory cell are configured in column direction.

As a result, by the skill of configuration memory units and data imput output circuit, can reduce the wiring number of composition data bus 13, thereby can dwindle the zone of the data bus 13 that occupies on the memory chip.

Figure 22 roughly represents the position of memory cell of semiconductor memory of Figure 10 first embodiment and the position of data bus.

Zone on the memory chip 10 is mainly memory cell 11-0～11-3 and data input and output zone (I/O) 12 is occupied.Data input and output zone 12 be configured in 4 limits with memory block chip 10 one side, be that one side in 2 limits of line direction is adjacent.

Memory element array in the memory cell is made of a plurality of little storage block in the column direction configuration, and constitutes a middle storage block by 2 little storage blocks.

The data line and the column selection line that in each little storage block, dispose the word line that extends at line direction respectively, extend at column direction.

Local DQ line follows on the direction between two little storage blocks 18a and extends.And overall DQ line extends at memory element array upper edge column direction 18b.Local DQ line interconnects by switch 18b 18a and overall DQ line.

Data bus 13 is configured between memory cell 11-0,11-2 and memory cell 11-1, the 11-3, follows direction and extends.Data bus 13 constitutes like that by the data that can transmit 16 bits (2 byte).

Figure 23 represents first modified example of the semiconductor memory of Figure 10 and Figure 22.

The characteristics of this variation are, data imput output circuit (I/O) 12 is configured in the middle body this point of memory chip 10 and memory cell 11-0～11-3 and data bus 13a, 13b is separately positioned on the both sides of data imput output circuit 12.

That is the zone on the memory chip 10 is mainly occupied by memory cell 11-0～11-3 and data input and output zone (I/O) 12.Data input and output zone 12 is configured in the middle body of memory chip 10 and stretches at column direction.

Memory cell 11-0,11-1 are configured in a side in data input and output zone 12, and memory cell 11-2,11-3 are configured in the opposite side in data input and output zone 12.

The memory element array of memory cell is made of a plurality of little storage block that is configured in column direction, and constitutes storage block in by two little storage blocks.Dispose respectively in each little storage block at the word line that extends on the line direction and data line that on column direction, extends and column selection line.

Local DQ line follows the long extension of direction to 18a between two little storage blocks.And overall DQ line extends at memory element array upper edge column direction 18b.Local DQ line interconnects by switch 18b 18a and overall DQ line.

Data bus 13a is configured in and follows the direction extension between memory cell 11-0 and the memory cell 11-1, is connected to data imput output circuit 12.Equally, data bus 13b is configured in and follows the direction extension between memory cell 11-2 and the memory cell 11-3, is connected to data imput output circuit 12.Data bus 13a, 13b constitute like that by the data that each self energy transmits 16 bits (2 byte).

Figure 24 represents the chip layout design of the semiconductor memory of Figure 23 in detail.

The interior layout of layout in each memory cell and each memory cell of the semiconductor memory of Figure 10 is identical.

Figure 25 represents first variation of the semiconductor memory of Figure 21.

The characteristics of this variation are, data imput output circuit (I/O) is configured in the middle body this point of memory chip 10 and memory cell 11-0～11-3 and data bus 13a, 13b is separately positioned on the both sides this point of data imput output circuit 12.

That is the zone on the memory chip 10 is mainly memory cell 11-0～11-3 and data input and output zone (I/O) 12 is occupied.Data input and output zone 12 is configured in the middle body of memory chip 10, and extends on column direction.

Memory element array in the memory cell is made of a plurality of little storage block in the column direction configuration, and constitutes storage block in two little storage blocks.Dispose word line that follows the direction extension and data line and the column selection line that extends along column direction in each little storage block respectively.

Local DQ line follows direction to 18a and extends between two little storage blocks.And overall DQ line extends at memory element array upper edge column direction 18b.Local DQ line is connected to each other by switch 18b 18a and overall DQ line.

Data bus 13a is configured in and follows the direction extension between memory component 11-0 and the memory component 11-1, and is connected to data imput output circuit 12.Equally, data bus 13b is configured in and follows the direction extension between memory cell 11-2 and the memory cell 11-3, and is connected to data imput output circuit 12.Data bus 13a, 13b constitute like that by the data that can transmit 32 bits (4 byte) separately.

The interior layout of the memory cell of each of the layout in each memory cell and the semiconductor memory of Figure 22 is identical.

Figure 26 represents second variation of chip layout of the first embodiment semiconductor memory of Figure 10 and Figure 22.Figure 27 represents the chip layout of the semiconductor memory of Figure 26 in detail.

This chip layout has compared with the chip layout of Figure 10 and Figure 22 that following some is different.

The first, one memory cell (main storage unit) is made of two sub-memory cells.

That is main storage unit 11-0,11-1,11-2 and 11-3 are made of quantum memory unit 11-0-#0 and 11-0-#1,11-1-#0 and 11-1-#1,11-2-#0 and 11-2-#1 and 11-3-#0 and 11-3-#1 respectively.

Quantum memory unit 11-0-#0,11-0-#1 select circuit to select simultaneously by memory cell.At quantum memory unit 11-0-#0, when 11-0-#1 is selected, remaining memory cell is promptly not selected.Equally, for example quantum memory unit 11-1-#0, when 11-1-#1 is selected, all the other quantum memory unit are all not selected.

And constituting one group with 4 sub-memory cell 11-0-#0,11-0-#1,11-1-#0 and 11-1-#1, the memory cell of this group is connected to data bus 13a.Equally, constitute one group with 4 sub-storage unit 11-2-#0,11-2-#1,11-3-#0 and 11-3-#1, the memory cell of this group is connected to data bus 13b.

The second, constitute like that by the data input and output of carrying out 8 bits (1 byte) in the sub-memory cell.

The layout of quantum memory unit is compared with the layout of the memory cell of Figure 10, and a column decoder CD this point is inequality only having.Because in the case of this example, owing to the input and output of carrying out the data of 8 bits in the sub-memory cell, column decoder CD is as long as one also just enough.But, column decoder CD, also with the semiconductor memory of Figure 10 in the same manner, select 2 row, so carry out the input and output of the data of 2 bits in each at middle storage block BLa, BLb, BLc and the BLd of memory element array.

Memory element array CAL, CAR in the quantum memory unit, line decoder RD, local DQ line be to 18a, and overall DQ line is to the layout of 18b and DQ buffer DQ, and be all identical with layout in the memory cell of the semiconductor memory of Figure 10.

The 3rd, data imput output circuit (I/O) 12 is done the column direction stretching, extension and is disposed like that at the middle body of memory chip 10, data bus 13a jointly is arranged among quantum memory unit 11-0-#0,11-0-#1,11-1-#0 and the 11-1-#1 in a side of data imput output circuit 12, and data bus 13b is arranged on by common land among quantum memory unit 11-2-#0,11-2-#1,11-3-#0 and the 11-3-#1 at the opposite side of data imput output circuit 12.

Data bus 13a, 13b follow on the direction between the quantum memory unit respectively and extend, and are connected on the data imput output circuit 12 of middle body of memory chip 10.Data bus 13a, 13b constitute like that by the data that can transmit 16 bits separately.

In the semiconductor memory of such chip layout, for example under quantum memory unit 11-0-#0, the selecteed situation of 11-0-#1, between quantum memory unit 11-0-#0 and data imput output circuit 12, carry out the giving and accepting of data of 8 bits by data bus 13a, similarly, between quantum memory unit 11-0-#1 and data imput output circuit 12, carry out giving and accepting of 8 bit data by data bus 13a.

Figure 28 represents second variation of chip layout of the second embodiment semiconductor memory of Figure 21.

It is different that this chip layout and the chip layout of Figure 21 have been compared following points.

The first, one memory cell (main storage unit) is made of two sub-memory cells.

Quantum memory unit 11-0-#0,11-0-#1 select circuit to select simultaneously by memory cell.At quantum memory unit 11-0-#0, when 11-0-#1 is selected, remaining quantum memory unit is all not selected.Equally, for example at quantum memory unit 11-1-#0, when 11-1-#1 is selected, remaining quantum memory unit is also not selected.

And, constituting one group by 4 sub-memory cell 11-0-#0,11-0-#1,11-1-#0 and 11-1-#1, the memory cell of this group is connected to data bus 13a.Equally, constitute one group by 4 sub-memory cell 11-2-#0,11-2-#1,11-3-#0 and 11-3-#1, the memory cell of this group is connected to data bus 13.

The second, constitute like that according to the input and output of the data of carrying out 16 bits (2 byte) in the sub-memory cell.

The layout of quantum memory unit, with the layout of the memory cell of Figure 21 relatively, column decoder CD has on two this point different.That is, the layout of quantum memory unit is identical with the layout of the storer of Figure 10.

Because in this routine situation, because a sub-memory cell carries out the input and output of the data of 16 bits, column decoder CD has two just enough.But column decoder CD similarly selects 2 row with the semiconductor memory of Figure 21, so all carry out the input and output of the data of 4 bits in each of middle storage block BLa, BLb, BLc and the BLd of memory element array.

Memory element array CAL, CAR in the quantum memory unit, line decoder RD, local DQ line be to 18a, and overall DQ line is to the layout of 18b and DQ buffer DQ, and be all identical with layout in the memory cell of the semiconductor memory of Figure 11.

The 3rd, the middle body that data imput output circuit (I/O) 12 is configured in memory chip 10 stretches along column direction, data bus 13a is arranged on by common land among quantum memory unit 11-0-#0,11-0-#1,11-1-#0 and the 11-1-#1 in a side of data imput output circuit 12, and data bus 13b then is arranged on by common land among quantum memory unit 11-2-#0,11-2-#1,11-3-#0 and the 11-3-#1 at the opposite side of data imput output circuit 12.

Follow direction between each comfortable quantum memory unit of data bus 13a, 13b and extend, be connected to the data imput output circuit 12 of the middle body of memory chip 10.Data bus 13a, 13b constitute like that by the data that can transmit 32 bits separately.

In the semiconductor memory of such chip layout, for example under the selecteed situation of quantum memory unit 11-0-#0,11-0-#1, carry out the giving and accepting of data of 16 bits between quantum memory unit 11-0-#0 and the data imput output circuit 12 by data bus 13a, equally, carry out giving and accepting of 16 bit data by data bus 13a between quantum memory unit 11-0-#1 and the data imput output circuit 12.

Figure 29 represents the 3rd variation of chip layout design of semiconductor memory of first embodiment of Figure 10 and Figure 22.Figure 30 represents the chip layout design of the semiconductor memory of Figure 29 in detail.

The first, one memory cell (main storage unit) is made of 2 sub-memory cells.

That is each free quantum memory unit 11-0-#0 of main storage unit 11-0,11-1,11-2 and 11-3 and 11-0-#1,11-1-#0 and 11-1-#1,11-2-#0 and 11-2-#1 and 11-3-#0 and 11-3-#1 constitute.

Quantum memory unit 11-0-#0,11-0-#1 are selected by the memory cell selector switch simultaneously.Under quantum memory unit 11-0-#0, the selecteed situation of 11-0-#1, all the other quantum memory unit are all not selected.Equally, for example also no longer select remaining quantum memory unit under the selecteed situation of quantum memory unit 11-1-#0,11-1-#1.

And form one group by 4 sub-memory cell 11-0-#0,11-1-#0,11-2-#0 and 11-3-#0, the memory cell of this group is connected to data imput output circuit 12a by data bus 13a, 13b.Equally, 4 sub-memory cell 11-0-#1,11-1-#1,11-2-#1 and 11-3-#1 form one group, and the memory cell of this group is summed up 13c, 13d by data and is connected to data imput output circuit 12b.

The second, constitute like that according to the input and output of the data of in a sub-memory cell, carrying out 8 bits (1 byte).

The layout of quantum memory unit, with the layout of the memory cell of Figure 10 relatively, be different only having on the column decoder this point.Because in this routine situation, owing to the input and output of carrying out the data of 8 bits in the sub-memory cell, column decoder CD one also just enough.But the semiconductor memory of this column decoder CD and Figure 10 is same, selects 2 row, so middle storage block BLa, BLb, BLc and the BLd of memory element array carry out the data input and output of 2 bits in each.

Memory element array CAL, CAR in the quantum memory unit, line decoder RD, local DQ line be to 18a, the overall DQ line layout to 18b and DQ buffer DQ, and be all almost identical with layout in the memory cell of the semiconductor memory of Figure 10.

The 3rd, data imput output circuit (I/O) 12a, 12b are configured on the memory chip 10 and along column direction and stretch, data 13a, 13b are set at the both sides of data imput output circuit 12a, and data bus 13c, 13d are set at the both sides of data imput output circuit 12b.

Data bus

13a, 13b, 13c and 13d all jointly are set on quantum memory unit 11-0-#0 and 11-1-#0,11-2-#0 and 11-3-#0,11-0-#1 and 11-1-#1 and 11-2-#1 and the 11-3-#1 separately.

Data bus 13a, 13b follow on the direction in the middle of the quantum memory unit respectively and extend, and are connected to the data imput output circuit.Equally, data bus 13c, 13d follow in the middle of the quantum memory unit respectively and extend on the direction and be connected to data imput output circuit 12b.Data bus 13a～13d all constitutes by the data that can transmit 8 bits separately like that.

In the semiconductor memory of such chip layout, for example quantum memory unit 11-0-#0, when 11-0-#1 is selected, carry out giving and accepting of 8 bit data by data bus 13a between quantum memory unit 11-0-#0 and data imput output circuit 12a, then carry out giving and accepting of 8 bit data between quantum memory unit 11-0-#1 and data input input circuit 12b by data bus 13c.

Promptly in other words, in the semiconductor memory of 16 bit types, data bus 13a～13d also can be made of the wiring of the number that can transmit 8 bit data, thereby can reduce the zone of the data bus on the memory chip.

Figure 31 represents the 3rd variation of chip layout of semiconductor memory of second embodiment of Figure 21.

This chip layout is compared with the chip layout of Figure 21 and is existed following points different.

The first, one memory cell (main storage unit) is made of two sub-memory cells.

That is each free quantum memory unit 11-0-#0 of main storage unit 11-0,11-1,11-2 and 11-3 and 11-0-#1,11-1-#0 and 11-1-#1,11-2-#0 and 11-2-#1 and 11-3-#0 and 11-3-#1 form.

Quantum memory unit 11-0-#0,11-0-#1 select circuit to select by memory cell simultaneously.At quantum memory unit 11-0-#0, when 11-0-#1 is selected, all the other quantum memory unit are all not selected.Equally, for example quantum memory unit 11-1-#0, also no longer select remaining quantum memory unit when 11-1-#1 is selected.

And form one group by 4 sub-memory cell 11-0-#0,11-1-#0,11-2-#1 and 11-3-#0, the memory cell of this group is connected to data imput output circuit 12a by data bus 13a, 13b.Equally, 4 sub-memory cell 11-0-#1,11-1-#1,11-2-#1 and 11-3-#1 form one group, and the memory cell of this group is connected to data imput output circuit 12b by data bus 13c, 13d.

The second, constitute like that by the data input and output of in a quantum memory unit, carrying out 16 bits (2 byte).

The layout of the layout of quantum memory unit and the memory cell of Figure 21 relatively has difference having on two column decoder CD this point.In other words, the layout of quantum memory unit is identical with the layout of the memory cell of Figure 10.

Because in this routine situation,, there are two column decoder CD just enough owing to the input and output of carrying out the data of 16 bits in the sub-memory cell.But the semiconductor memory of column decoder CD and Figure 21 is similarly selected 2 row, so middle storage block BLa, BLb, BLc and the BLd of memory element array carry out the input and output of the data of 4 bits separately.

The 3rd, data imput output circuit (I/O) 12a, 12b are configured to extend at memory chip 10 upper edge column directions, data bus 13a, 13b are arranged on the both sides of data imput output circuit 12a, and data bus 13c, 13d are located at the both sides of data imput output circuit 12b.

The equal respectively common land of

data bus

13a, 13b, 13c and 13d is arranged on quantum memory unit 11-0-#0 and 11-1-#0,11-2-#0 and 11-3-#0,11-0-#1 and 11-1-#1 and 11-2-#1 and the 11-3-#1.

Follow between each comfortable quantum memory unit of data bus 13a, 13b on the direction and to extend and be connected to data imput output circuit 12a, equally, follow between each comfortable quantum memory unit of data bus 13c, 13d on the direction and to extend and be connected to data imput output circuit 12b.Data bus 13a～13d all constitutes by transmitting 16 bit data separately like that.

Like this in the semiconductor memory of chip layout, for example under the situation that quantum memory unit 11-0-#0,11-0-#1 are selected, carry out giving and accepting of 16 bit data by data bus 13a between quantum memory unit 11-0-#0 and data imput output circuit 12a, then carry out giving and accepting of 16 bit data between quantum memory unit 11-0-#1 and data imput output circuit 12b by data bus 13c.

Also in other words, in the semiconductor memory of 32 bit types, data bus 13a～13d also can be made of the wiring of the quantity that can transmit 16 bit data, and can reduce the zone of data bus on the memory chip.

Figure 32 represents the 4th variation of chip layout of the first embodiment semiconductor memory of Figure 10 and Figure 22.Figure 33 shows the chip layout of the semiconductor memory of Figure 32 in detail.

This chip layout is compared with the chip layout of Figure 10 and Figure 22, and following some difference is arranged.

The first, one memory cell (main storage unit) is made of two sub-memory cells.

That is main storage unit 11-0,11-1,11-2 and 11-3 are separately by quantum memory unit 11-0-#0 and 11-0-#1,11-1-#0 and 11-1-#1,11-2-#0 and 11-2-#1 and 11-3-#0 and 11-3-#1 formation.

Quantum memory unit 11-0-#1,11-0-#1 select circuit to select simultaneously by memory cell, and under quantum memory unit 11-0-#0, the selecteed situation of 11-0-#1, all the other quantum memory unit are all not selected.Equally, at quantum memory unit 11-1-#0, when 11-1-#1 is selected, also no longer select remaining quantum memory unit.

And 4 sub-memory cell 11-0-#0,11-1-#0,11-2-#0 and 11-3-#0 form one group, and the memory cell of this group all is connected to data imput output circuit 12 by data bus 13a.Equally, 4 sub-memory cell 11-0-#1,11-1-#1,11-2-#1 and 11-3-#1 form one group, and the memory cell of this group connects data imput output circuit 12 by data bus 13b.

The second, constitute like that according to the data input and output of in a sub-memory cell, carrying out 8 bits (1 byte).

The layout of quantum memory unit is compared with the layout of Figure 10 memory cell, is different only having on the column decoder CD this point.Because in the case of this example, owing to the input and output of carrying out 8 bit data in the sub-memory cell, a column decoder CD is just enough.But, column decoder CD, same with the semiconductor memory of Figure 10, select 2 row, so middle storage block BLa, BLb, BLc and the BLd of memory element array carry out the data input and output of 2 bits separately.

Memory element array CAL, CAR in the quantum memory unit, line decoder RD, local DQ line be to 18a, the overall DQ line layout to 18b and DQ buffer DQ, and be roughly the same with the layout in the memory cell of the semiconductor memory of Figure 10.

The 3rd, data imput output circuit (I/O) 12 is configured in the middle body of memory chip 10 along stretching on the column direction, and data bus 13a, 13b then are set at the both sides of data imput output circuit 12.

Data bus 13a is arranged on the last data bus 13b of quantum memory unit 11-0-#0,11-1-#0,11-2-#0 and 11-3-#0 by common land and then is arranged on quantum memory unit 11-0-#1,11-1-#1 by common land, on 11-2-#1 and the 11-3-#1.

Follow on the direction between each comfortable quantum memory unit of data bus 13a, 13b and extend, and be connected to data imput output circuit 12.Data bus 13a, 13b all constitute by transmitting 8 bit data separately like that.

In the semiconductor memory of such chip layout, for example quantum memory unit 11-0-#0, when 11-0-#1 is selected, 12 of quantum memory unit 11-0-#0 and data imput output circuits carry out giving and accepting of 8 bit data by data bus 13a, and 12 of quantum memory unit 11-0-#1 and data imput output circuits carry out giving and accepting of 8 bit data by data bus 13b.

In other words, in the semiconductor memory of 16 bit types, data bus 13a, 13b can be made of the wiring of the quantity that can transmit 8 bit data, and can reduce the zone of the data bus on the memory chip.

Figure 34 represents the 4th variation that the chip layout of the second embodiment semiconductor memory of Figure 21 designs.

This chip layout and the chip layout of Figure 21 have that following some is different.

The first, one memory cell (main storage unit) is made of two sub-memory cells.

Quantum memory unit 11-0-#0,11-0-#1 select circuit to select simultaneously by memory cell.At quantum memory unit 11-0-#0, when 11-0-#1 is selected, remaining quantum memory unit is not selected.Equally, for example quantum memory unit 11-1-#0, when 11-1-#1 is selected, also do not select remaining memory cell.

And 4 sub-memory cell 11-0-#0,11-1-#0,11-2-#0 and 11-3-#0 form one group, and the memory cell of this group connects data imput output circuit 12 by data bus 13a.Equally, 4 sub-memory cell 11-0-#1,11-1-#1,11-2-#1 and 11-3-#1 form one group, and the memory cell of this group connects data imput output circuit 12 by data bus 13b.

The second, constitute like that by the data input and output of carrying out 16 bits (2 byte) in the sub-memory cell.

The layout of the layout of quantum memory unit and the memory cell of Figure 21 relatively has difference having on 2 column decoder CD this point.Also in other words, the layout of this quantum memory unit is identical with the layout of the memory cell of Figure 10.

Because in this routine situation,, there are two column decoder CD just enough because a sub-memory cell carries out the input and output of the data of 16 bits.But, column decoder CD, same with the semiconductor memory of Figure 21, select 2 row, so in each of middle storage block BLa, BLb, BLc and the BLd of memory element array, carry out the data input and output of 4 bits.

Memory element array CAL, CAR in the quantum memory unit, line decoder RD, local DQ line be to 18a, and overall DQ line is to the layout of 18b and DQ buffer DQ, and be identical with the layout of the memory cell of the semiconductor memory of Figure 10.

The 3rd, the middle body that data imput output circuit (I/O) 12 is configured in memory chip 10 makes it extend at column direction, and data bus 13a, 13b are arranged on the both sides of data imput output circuit 12.

Data bus 13a common land is arranged on quantum memory unit 11-0-#0,11-1-#0,11-2-#0 and the 11-3-#0, and data bus 13b common land is arranged on quantum memory unit 11-0-#1,11-1-#1,11-2-#1 and the 11-3-#1.

Data bus 13a, 13b are following the direction extension and are being connected on the data imput output circuit 12 respectively between the quantum memory unit.Data bus 13a, 13b constitute like that by the data that can transmit 16 bits separately.

The semiconductor memory of such chip layout, for example at quantum memory unit 11-0-#0, when 11-0-#1 is selected, 12 of quantum memory unit 11-0-#0 and data imput output circuits carry out the giving and accepting of data of 16 bits by data bus 13a, 12 of quantum memory unit 11-0-#1 and data imput output circuits carry out giving and accepting of 16 bit data by data bus 13b.

Also in other words, in the semiconductor memory of 32 bit types, data bus 13a, 13b also can be connected up by the quantity that can transmit 16 bit data and constitute, and the zone of the data bus on the memory chip is reduced.

Figure 35 represents data communication system of the present invention.

Each free similar elements of n (n is even numbers) individual storage block BL0～BLn constitutes.Storage block BL0～BLn is configured at column direction with extending.Be that example is illustrated its formation now with storage block BL0.

Storage block BL0 has two switch arrays 41a, 41b in the column direction configuration.Each freely is configured to a plurality of switches (MOS transistor) 46a, the 46b formation of matrix switch arrays 41a, 41b.

It is adjacent that line decoder 42a one of is configured in two ends of line direction with switch arrays 41a.It is adjacent that line decoder 42a one of is configured in two ends of line direction with switch arrays 41b.The end of word line 44a, 44b is connected to line decoder 41a, 42b, and word line 44a, 44b also are connected to a plurality of switch 46a, the 46b control end (grid) that belongs to delegation.

It is adjacent that column decoder 43 one of is configured in two ends with the column direction of switch arrays 41a.One end of column selection line 49 is connected on the column decoder 43.

Dispose register 47a, 47b and column selection row between two switch arrays 41a, the 41b and close 48a, 48b.The end of data line 45a, 45b is connected with column select switch 48a, 48 with register 47a, 47b, and data line 45a, 45b are also connected to the output terminal (drain electrode) of a plurality of switch 46a, the 46b that belong to same row.Column selection line 49 is connected with column select switch 48a, 48b.

Data are added to the input end (source electrode) of a plurality of switch 46a, 46b.

Local DQ line 50-0 is configured in and does the line direction extension between two switch matrix 41a, the 41b.Local DQ line 50-0 is connected to register 47a, 47b and column select switch 48a, 48b.

Overall situation DQ line 51-0 is configured on the switch arrays of n storage block BL0～BLn and does the column direction extension.The end of overall situation DQ line 51-0 is connected to local DQ line 50-0, and its other end is connected to data imput output circuit (I/O) 52.

Data imput output circuit 52 be configured with two ends of column direction of n storage block BL0～BLn in one of adjacent.

The characteristics of above-mentioned data communication system are, when n storage block BL0～BLn was configured to extend on column direction, for example the data by storage block BL0～BLn output promptly were led to data imput output circuit 52 by the overall DQ line 51-0～51-n on switch arrays 41a, the 41b.

Also in other words, data from storage block BL0～BLn output, when one of gathering in column direction two ends that abutted against storage block BL0～BLn the data imput output circuit 52 of ground configuration, also from then on data imput output circuit 52 outputs to the outside of LSI.

Figure 36 represents the structure of accumulator system of the present invention.

At this moment be that example to the storer system of the semiconductor memory that adopts Fig. 1～Figure 34 describes.

10 is memory chip, and its structure is configured to identical by the structure of a semiconductor memory of the selection in the semiconductor memory that illustrates among Fig. 1～Figure 34.

Be formed with memory element array 51, read/write circuit 52, input circuit 53, output circuit 54, synchronizing circuit 55 and clock buffer 56 in the memory chip 10.

Cpu chip 58 clock signal CK.This clock signal CK is supplied to memory chip 10, as internal clock signal CLK.In memory chip 10, internal clock signal CLK is supplied to read/write circuit 52, makes the latter and CLK synchronous operation.

Clock signal C K and internal clock signal CLK depart from (distortion) removed by synchronizing circuit 55.Synchronizing circuit 55 output internal clock signal CK ' also supply with input circuit 53 and output circuit 54.Input circuit 53 and output circuit 54 and interior step clock signal CK ' synchronous operation.

I/O bus 57 connected storage chips 10 and cpu chip 58.Data are come and gone between memory chip 10 and cpu chip 58 by I/O bus 57.

As explained above, according to semiconductor memory of the present invention and test macro thereof, and data communication system, can obtain effect as follows.

A plurality of memory cells are set, in each memory cell, are being provided with and are following direction local DQ line that stretches and the overall DQ line that is configured in the column direction stretching, extension of memory element array upper edge between the little storage block that is configured in memory element array.And inputoutput data is promptly by local DQ line and overall DQ line, comes and goes between the DQ buffer of the column direction end that is arranged at memory cell and memory element array.

Adopt such structure, owing to the element arrays controller in each memory cell, line decoder, column decoder, DQ buffer can be configured in and separately memory element array adjacent place on one side, just may in the semiconductor memory of many bits type, clock synchronization type, memory cell type, not increase area of chip and improve data transfer rate.

Claims

1. A semiconductor memory comprising a memory chip, a plurality of memory cells configured on the memory chip, a data input/output area configured to perform multi-bit data input/output on the memory chip, and the plurality of memory cells configured on the memory chip A data bus that is commonly provided on the memory units, extends in the column direction, and serves as a path for the multi-bit data between the plurality of memory units and the data input and output, is characterized in that,

Each of the plurality of memory units includes:

Two small memory blocks arranged in the column direction constituted by a memory element array, a sense amplifier arranged between the two small memory blocks, and word lines and data lines arranged on the memory element array a plurality of memory blocks arranged in the column direction of the line and the column selection line;

a column decoder connected to at least one of the column selection lines disposed on at least one of the two ends in the column direction;

A plurality of row decoders connected to the word line are arranged on one of the two ends in the row direction, one in each of the middle memory blocks, and connected to the word line;

A plurality of DQ buffers arranged one at each of the middle memory blocks at the other of the two ends in the row direction; and

An element array controller configured at one of the two ends of the row direction to control the multi-bit data read operation or the multi-bit data write operation,

On the other hand, the plurality of memory cells are configured to perform the multi-bit data read operation or the multi-bit data write operation independently of each other.

2. The semiconductor memory device according to claim 1, wherein

Each of the plurality of memory cells is provided with a memory cell selection circuit arranged at the other of both ends in the row direction;

The memory unit selection circuit is configured to connect one of the plurality of memory units to the data bus when performing the multi-bit data read operation or the multi-bit data write operation , while disconnecting the remaining memory cells from the data bus.

3. The semiconductor memory according to claim 1, wherein there are two memory cells in the row direction and two memory cells in the column direction, for a total of four memory cells.

4. The semiconductor memory device according to claim 1, wherein a DQ line pair extending along the row direction between the two small memory blocks is provided, and the DQ line pair connects the sense amplifier Interconnect with the DQ buffer.

5. The semiconductor memory according to claim 1, further comprising a column selection switch connected to the column selection line arranged between the two small memory blocks.

6. The semiconductor memory according to claim 1, wherein the data input/output area is arranged at one of two ends of the memory chip in the column direction.

7. The semiconductor memory according to claim 1, wherein the data input/output area has a plurality of data input/output circuits for simultaneously inputting and outputting the multi-bit data.

8. The semiconductor memory according to claim 1, wherein the data bus extends along the column direction at a central portion of the memory chip, and the plurality of memory cells are arranged on the side of the data bus. Both sides of the row direction.

9. The semiconductor memory device according to claim 1 , wherein when each of the plurality of memory cells has a plurality of column decoders, two column selection lines adjacent to each other among the column selection lines are composed of Individually different column decoder controls.

10. The semiconductor memory device according to claim 1, wherein the row decoder selects one of the two small memory blocks, and selects a word line from the word line of the selected small memory block Wire.

11. A semiconductor memory, provided with a memory chip, configured on the memory chip, a plurality of main memory chips composed of a plurality of sub-memory units, configured on the memory chip for multi-bit data input and output The data input and output area of the plurality of main memory units, and the sub-memory units that are commonly provided on two or more sub-memory units among all the sub-memory units constituting the plurality of main memory units and extended in the column direction as the plurality of main memory units A plurality of data buses for the passage of the multi-bit data between the sub-memory unit and the data input and output, characterized in that,

Each of the plurality of sub-memory units includes:

Two small memory blocks arranged in the column direction composed of a memory element array, a sense amplifier arranged between the two small memory blocks, and word lines and data lines arranged on the memory element array and a column selection line and arrange a plurality of storage blocks in the column direction;

A plurality of row decoders connected to the word line are arranged in one of the two ends of the row direction in each of the memory blocks;

One DQ buffer is arranged in each of the storage blocks in the other of the two ends of the row direction; and

an element array controller configured at one of the two ends in the row direction to control the multi-bit data read operation or the multi-bit data write operation,

Each of the plurality of sub-memory units independently performs a read operation of the multi-bit data or a write operation of the multi-bit data.

12. The semiconductor memory device according to claim 11, wherein

Each of the plurality of sub-memory cells is provided with a memory cell selection circuit arranged at the other of both ends in the row direction;

The memory cell selection circuit selects two of all the sub-memory cells constituting the plurality of main memory cells when performing the read operation of the multi-bit data or the write operation of the multi-bit data. more than one sub-memory unit, connect the selected sub-memory unit to the data bus, and disconnect the unselected sub-memory unit from the data bus.

13. The semiconductor memory device according to claim 12, wherein the data input and output in the selected sub-memory unit pass through different respective data buses, between the selected sub-memory unit and the selected sub-memory unit. exchange between the above data input and output areas.

14. The semiconductor memory device according to claim 11, characterized in that, a DQ line pair extending along the row direction arranged between the two small memory blocks is provided, and the DQ line pair connects the sense amplifier Interconnect with the DQ buffer.

15. The semiconductor memory device according to claim 11, further comprising a column selection switch connected to the column selection line arranged between the two small memory blocks.

16. The semiconductor memory according to claim 11, wherein when the number of the plurality of sub-memory units constituting each of the plurality of main memory units is n, the data input/output area has a A plurality of data input and output circuits simultaneously input and output data n times the multi-bit data.

17. The semiconductor memory according to claim 11, wherein when each of the plurality of sub-memory units constituting each of the plurality of main memory units has a plurality of column decoders, each of the column selection lines Two adjacent column select lines are controlled by different column decoders.

18. The semiconductor memory device according to claim 11, wherein the row decoder selects one of the two small memory blocks, and selects a word line from the word line of the selected small memory block. Wire.

19. The semiconductor memory according to claim 11, wherein the data input/output area is arranged at a central portion of the memory chip and extends in the row direction.

20. The semiconductor memory according to claim 19, wherein the data bus lines extend in each of the column directions on both sides of the data input/output region in the column direction.

21. The semiconductor memory according to claim 20, wherein the plurality of sub memory cells constituting the plurality of main memory cells are arranged on both sides of the data bus in the row direction.

22. The semiconductor memory according to claim 21, wherein the plurality of sub-memory units constituting the plurality of main memory units are four in the row direction and two in the column direction, for a total of 8.

23. The semiconductor memory according to claim 11, wherein the data input/output area is arranged at one of two ends in the column direction of the memory chip.

24. The semiconductor memory according to claim 23, wherein each of the data bus lines extends in the column direction on one side of the data input/output area in the column direction.

25. The semiconductor memory according to claim 24, wherein the plurality of sub memory cells constituting the plurality of main memory cells are arranged on both sides of the data bus in the row direction.

26. The semiconductor memory according to claim 25, wherein the plurality of sub-memory units constituting the plurality of main memory units are four in the row direction and two in the column direction, and there are a total of There are 8 of them.

27. A semiconductor memory, which is provided with a memory chip, a plurality of memory cells arranged on the memory chip, a data input and output area for performing multi-bit data input and output on the memory chip, and the A data bus extending along the row direction shared by the plurality of memory units as a path for the multi-bit data between the plurality of memory units and the data input and output area is characterized in that,

Each of the plurality of memory cells includes:

Two small memory blocks arranged in the column direction composed of a memory element array, a sense amplifier arranged between the two small memory blocks, and word lines, data lines, and column selection lines arranged on the memory element array and configuring a plurality of middle storage blocks in the column direction;

a column decoder connected to at least one of the column selection lines arranged at one of the two ends in the column direction;

A plurality of row decoders arranged at one of the two ends in the row direction, one for each of the middle memory blocks, connected to the word line;

a DQ buffer arranged at the other of the two ends in the column direction; and

An element array controller arranged at the other end of the two ends in the row direction to control the read operation of the multi-bit data or the write operation of the multi-bit data,

The plurality of memory units each independently perform the multi-bit data read operation or the multi-bit data write operation.

28. The semiconductor memory device according to claim 27, wherein

The plurality of memory cells are each provided with:

A pair of local DQ lines arranged between the two small memory blocks constituting each of the middle memory blocks, extending along the row direction and connected to the sense amplifier; and

A global DQ line pair extending along the column direction on the middle memory block and connecting the local DQ line pair and the DQ buffer.

29. The semiconductor memory according to claim 28, further comprising a switch arranged between the local DQ line pair and the global DQ line pair.

30. The semiconductor memory device according to claim 29, wherein said switch is formed of an N-channel MOS transistor.

31. The semiconductor memory device according to claim 27, wherein

Each of the plurality of memory cells is provided with a memory cell selection circuit arranged at the other of both ends in the column direction;

The memory cell selection circuit connects one of the plurality of memory cells to the data bus when performing the multi-bit data read operation or the multi-bit data write operation, thereby The data bus switches off the remaining memory cells.

32. The semiconductor memory according to claim 27, wherein there are two memory cells in the row direction and two memory cells in the column direction, a total of four memory cells exist.

33. The semiconductor memory device according to claim 27, further comprising a column selection switch connected to the column selection line arranged between the two small memory blocks.

34. The semiconductor memory according to claim 27, wherein the data input/output area is arranged at one of the two end portions in the row direction of the memory chip.

35. The semiconductor memory according to claim 27, wherein the data input/output area is arranged at a central portion of the memory chip and extends along the column direction.

36. The semiconductor memory according to claim 27, wherein said data input/output area has a plurality of data input/output circuits for simultaneously inputting and outputting said multi-bit data.

37. The semiconductor memory device according to claim 27, wherein the data bus line extends along the row direction at the central part of the memory chip, and the plurality of memory cells are arranged on the side of the data bus line. Both sides of the column direction.

38. The semiconductor memory according to claim 27, wherein when each of the plurality of memory cells has a plurality of column decoders, the plurality of column decoders are arranged in the row direction, so The column selection line groups controlled by the plurality of column decoders are completely separated from each other.

39. The semiconductor memory device according to claim 27, wherein the row decoder selects one of the two small memory blocks, and selects a word line from the word lines of the selected small memory block .

40. The semiconductor memory device according to claim 27, wherein said at least one column decoder has a function of selecting one of said column selection lines and selecting two or more of said column selection lines. The function of the column selection line, the two functions are switched by the control signal.

41. A semiconductor memory, provided with a memory chip, a plurality of main memory units composed of a plurality of sub-memory units arranged on the memory chip, and configured on the memory chip to perform multi-bit data The data input and output area for input and output is commonly provided on two or more sub-memory units among all the sub-memory units constituting the main memory unit, extending along the row direction, and serving as sub-memory units of the plurality of main memory units. A plurality of data buses for the passage of the multi-bit data between the memory unit and the data input/output area, characterized in that,

Each of the plurality of sub-memory units includes:

Two small memory blocks arranged in the column direction composed of a memory element array, a sense amplifier arranged between the two small memory blocks, and word lines, data lines, and column selection lines arranged on the memory element array And configure a plurality of storage blocks in the column direction;

a column decoder disposed at one of the two ends in the column direction and connected to at least one of the column selection lines;

A plurality of row decoders connected to the word line arranged at one of the two ends of the row direction and provided in each of the middle memory blocks;

The DQ buffer arranged at the other of the two ends in the column direction; and

an element array controller arranged at the other of the two ends in the row direction and controlling a read operation of the multi-bit data or a write operation of the multi-bit data,

42. The semiconductor memory device according to claim 41, wherein

The plurality of sub-memory units are each provided with:

local DQ line pairs extending along the row direction and connected to the sense amplifiers arranged between the two small memory blocks constituting the respective middle memory blocks; and

extending along the column direction on the middle memory block and connecting the local DQ line pair and the global DQ line pair of the DQ buffer.

43. The semiconductor memory according to claim 42, further comprising a switch arranged between the local DQ line pair and the global DQ line pair.

44. The semiconductor memory device according to claim 43, wherein the switch is composed of an N-channel MOS transistor.

45. The semiconductor memory device according to claim 41, wherein

Each of the plurality of sub-memory cells is provided with a memory cell selection circuit arranged at the other end portion of the column direction,

When performing the multi-bit data read operation or the multi-bit data write operation, the memory selection circuit selects two or more of all the sub-memory units constituting the plurality of main memory units. The sub-memory unit connects the selected sub-memory unit to the data bus, and disconnects the unselected sub-memory unit from the data bus.

46. The semiconductor memory as claimed in claim 45, wherein the data input and output in the selected sub-memory unit are transferred between the selected sub-memory unit and the selected sub-memory unit through different data buses. The exchange of data between input and output areas.

47. The semiconductor memory device according to claim 41, further comprising a column selection switch connected to the column selection line arranged between the two small memory blocks.

48. The semiconductor memory according to claim 41, wherein when the number of the plurality of sub-memory units constituting each of the plurality of main memory units is n, the data input/output area has A plurality of data input/output circuits for inputting and outputting n times the multi-bit data.

49. The semiconductor memory device according to claim 41, wherein when each of the plurality of sub-memory units constituting each of the plurality of main memory units has a plurality of column decoders, the plurality of column Decoders are arranged in the row direction, and the column selection line groups controlled by the plurality of column decoders are completely separated from each other.

50. The semiconductor memory device according to claim 41, wherein the row decoder selects one of the two small memory blocks, and selects a word line from the word lines of the selected small memory block .

51. The semiconductor memory according to claim 41, wherein the data input/output area is arranged at the center of the memory chip and extends in the column direction.

52. The semiconductor memory according to claim 51, wherein the data bus lines respectively extend in the row direction on both sides of the data input/output area in the row direction.

53. The semiconductor memory according to claim 52, wherein the plurality of sub memory cells constituting the plurality of main memory cells are arranged on both sides of the data bus in the column direction.

54. The semiconductor memory according to claim 53, wherein the plurality of sub-memory cells constituting the main memory cell are four in the row direction and two in the column direction for a total of eight. indivual.

55. The semiconductor memory according to claim 41, wherein the data input/output area is arranged at one of both ends of the memory chip in the row direction.

56. The semiconductor memory device according to claim 55, wherein the data bus lines each extend along the row direction on one side of the data input/output area in the row direction.

57. The semiconductor memory according to claim 56, wherein the plurality of sub memory cells constituting the plurality of main memory cells are arranged on both sides of the data bus in the column direction.

58. The semiconductor memory according to claim 57, wherein the plurality of sub-memory units constituting the plurality of main memory units are four in the row direction and two in the column direction, for a total of There are 8 of them.

59. A semiconductor memory, provided with a memory chip, a plurality of main memory units composed of a plurality of sub-memory units configured on the memory chip, and configured on the memory chip for inputting multi-bit data A plurality of data input and output areas for output, and shared among more than two sub-memory units among all the sub-memory units constituting the plurality of main memory units, extend along the row direction and serve as the plurality of main memory units A plurality of data buses for the multi-bit data path between the sub-memory unit of the unit and the data input and output area, wherein each of the plurality of sub-memory units includes:

Two small memory blocks arranged in the column direction composed of a memory element array, a sense amplifier arranged between the two small memory blocks, and word lines, data lines, and column selects arranged on the memory element array lines and are arranged in a plurality of storage blocks in the column direction;

A plurality of row decoders connected to the word line are arranged at one of the two ends in the row direction and each of the memory blocks is provided with one;

a DQ buffer disposed at the other of the two ends in the column direction; and

an element array controller disposed at the other of the two ends in the row direction and controlling a read operation of the multi-bit data or a write operation of the multi-bit data, and

The plurality of data buses are respectively arranged on both sides of the row direction of each data input and output area, and the plurality of sub-memory units constituting the plurality of main memory units are arranged on both sides of the column direction of each data bus. sides,

Each of the plurality of sub-memory cells is configured to read or read the multi-bit data independently of each other.

60. The semiconductor memory as claimed in claim 59, wherein the plurality of sub-memory units are each provided with:

A pair of local DQ lines connected to the sense amplifier, disposed between the two small memory blocks constituting the respective middle memory blocks and extending along the row direction; and

61. The semiconductor memory according to claim 60, further comprising a switch disposed between the local DQ line pair and the global DQ line pair.

62. The semiconductor memory device according to claim 61, wherein said switch is formed of an N-channel MOS transistor.

63. The semiconductor memory according to claim 59, wherein each of the plurality of sub-memory cells is provided with a memory cell selection circuit arranged at the other end of the two ends in the column direction,

The memory unit selection circuit selects two or more sub-memory units among all the sub-memory units constituting the plurality of main memory units when performing the read or write operation of the multi-bit data, and selects all the sub-memory units Selected sub-memory cells are connected to the data bus, while unselected sub-memory cells are disconnected from the data bus.

64. The semiconductor memory according to claim 63, characterized in that, in the selected sub-memory unit, input and output data pass through different data buses respectively between the selected sub-memory unit and the selected sub-memory unit. exchange between the above data input and output areas.

65. The semiconductor memory device according to claim 59, further comprising a column selection switch connected to the column selection line arranged between the two small memory blocks.

66. The semiconductor memory as claimed in claim 59, wherein when the number of said plurality of sub-memory units constituting each of said plurality of main memory units is n, the number of said data input and output areas is n, and said data Each of the input and output areas has a plurality of data input and output circuits for simultaneously inputting and outputting the multi-bit data.

67. The semiconductor memory according to claim 59, wherein when the plurality of sub-memory units constituting each of the main memories has a plurality of column decoders, the plurality of column decoders are Arranged in the row direction, the column selection line groups controlled by the plurality of column decoders are completely separated from each other.

68. The semiconductor memory device according to claim 59, wherein the row decoder selects one of the two small memory blocks, and selects a word line from the word lines of the selected small memory block .

69. The semiconductor memory according to claim 59, wherein the plurality of sub-memory units constituting the plurality of main memory units are four in the row direction and two in the column direction, a total of There are 8 of them.

70. The semiconductor memory according to claim 59, wherein each of the plurality of main memory cells performs a read or write operation of the multi-bit data in synchronization with an external clock.

71. A test circuit for writing means for a storage block provided with a storage element array composed of a plurality of storage blocks, and simultaneously writing data into storage elements in at least one storage block of the plurality of storage blocks, and A semiconductor for testing a register pre-saved with data written to said at least one memory block is characterized in that it is provided with:

A test mode writing/reading means for writing the data of the register into the storage elements of the storage element array and reading the data of the storage elements in the test mode;

Comparing the data stored in the register with the number read from the storage element by the test mode writing/reading means, judging whether the semiconductor memory is good or not based on the comparison result, and outputting a signal indicating whether it is good or not means of comparison of results; and

The data output from the comparison means is output to an output circuit for testing outside the semiconductor memory.

72. A test circuit, which is used to simultaneously write n bits of data into n (n is a natural number above 2) memory blocks in the plurality of memory blocks provided with a storage element array composed of a plurality of memory blocks. The storage block writing means of the storage element in the block, the semiconductor storage of the register of the n-bit data written in the n storage blocks are pre-saved for testing, and it is characterized in that:

When testing the mode, write the n-bit data stored in the register into the storage elements of the storage element array and read the n-bit data of the storage elements into the test mode write /read means;

comparing the n-bit data stored in the register with the n-bit data read from the storage element by the test mode writing/reading means, and judging the Describe the quality of the semiconductor memory, and output 1-bit data representing the result of comparison; and

An output circuit for testing that outputs the 1-bit data output from the comparison means to the outside of the semiconductor memory.

73. The test circuit as claimed in claim 72, characterized in that a latch means for storing n-bit data of said comparison result in said comparison means is provided, and when said judgment result is unfavorable In this case, the n-bit data of the storing means is sequentially sent to the switching means of the output circuit for testing.

74. The test circuit as claimed in claim 72, wherein said semiconductor memory is an n-bit type semiconductor memory carrying out input and output of n-bit data at the same time, and said semiconductor memory has an n bit used during a normal operation mode. output pads to which the test output circuit is connected to one of the n output pads.

75. A data transmission system characterized by,

There are a plurality of memory blocks arranged extending in the column direction, each memory block is a switch array composed of a plurality of switches arranged in a matrix, and a row for selecting the switch array is arranged adjacent to the end of the switch array in the row direction. A row decoder, a local DQ line extending along the row direction arranged adjacent to the column direction end of the switch array, and a plurality of switches connected to the switch array and directing data to the local DQ line of data lines constituted by,

and have:

a global DQ line configured to extend along the column direction on the plurality of memory blocks and connected to the local DQ line at one end,

a column decoder for selecting a column of the switch array of the plurality of memory blocks arranged adjacent to ends in the column direction of the plurality of memory blocks, and

A data input/output circuit connected to the other end of the global DQ line and connected to the other end of the global DQ line, which is arranged adjacent to the column direction ends of the plurality of memory blocks, for performing data input/output.

76. The data transmission system according to claim 75, wherein column selection lines disposed on the switch array are provided.

77. The data transfer system according to claim 76, wherein a column selection switch is provided adjacent to an end of said switch array, said column selection switch being connected to said column selection line.

78. The data transmission system of claim 75, wherein a register is provided adjacent to an end of the switch array, the register being connected between the data line and the local DQ line .

79. The data transfer system according to claim 75, wherein said data input/output circuit simultaneously performs input and output of multi-bit data.

80. A memory system comprising a memory chip, a plurality of memory cells disposed on the memory chip, and a data input/output area disposed on the memory chip for performing multi-bit data input and output synchronously with a clock signal A data bus extending along the column direction and serving as a path for multi-bit data between the plurality of memory units and the data input/output area provided by the plurality of memory units, generating the clock signal A CPU chip and an I/O line interconnecting the memory chip and the CPU chip, characterized in that,

Each of the plurality of memory units includes:

Two small memory blocks arranged in the column direction composed of a memory element array, a sense amplifier arranged between the two small memory blocks, and word lines, data lines, and column selects arranged on the memory element array line and store blocks in a plurality of arrays arranged in the column direction;

a column decoder disposed at at least one of the two ends in the column direction and connected to at least one of the column selection lines;

A plurality of row decoders, one of each of the middle memory blocks, connected to the word line, are arranged at one of the two ends in the row direction;

a plurality of DQ buffers disposed at the other of the two end portions in the row direction and provided one each in the middle memory block; and

an element array controller arranged at one of the two ends of the row direction and controlling the reading or writing operation of the multi-bit data, and

Each of the plurality of memory cells is configured to read or write the multi-bit data independently of each other.

81. A memory system, comprising a memory chip, a plurality of main memory units composed of a plurality of sub-memory units disposed on the memory chip, and multi-bit memory units disposed on the memory chip synchronously with a clock signal The data input and output area for data input and output is a sub-memory of the plurality of main memory units in which two or more sub-memory units are provided in common and extend in the column direction among all the sub-memory units of the plurality of main memory units. The data bus of the multi-bit data path between the unit and the data input and output interval, the CPU chip that generates the clock signal, and the I/O that interconnects the memory chip and the CPU chip line, characterized by,

Each of the plurality of sub-memory units includes:

Two small memory blocks arranged in the column direction constituted by a memory element array, a sense amplifier arranged between the two small memory blocks, and word lines, data lines, and columns arranged on the memory element array Selecting a line, storing blocks in a plurality of arrays arranged in the column direction;

A column decoder configured and connected to at least one of the column selection lines at least one of the two ends in the column direction;

A plurality of row decoders connected to the word lines are arranged at one of the two ends in the row direction and each of the middle memory blocks is provided with one;

a plurality of DQ buffers arranged at the other of the two end portions in the row direction and provided one each in the middle memory block; and

Each of the plurality of sub-memory units independently performs the read or write operation of the multi-bit data.

82. A memory system comprising a memory chip, a plurality of memory cells arranged on the memory chip, and a data input for inputting and outputting multi-bit data synchronously with a clock signal arranged on the memory chip In the output area, the plurality of memory units are arranged in common and extend along the row direction as the data bus of the multi-bit data between the plurality of memory units and the data input and output area, generating the The CPU chip of the clock signal, and the I/O line interconnecting the memory chip and the CPU chip, it is characterized in that,

Each of the plurality of memory units includes:

It has two small memory blocks arranged in the column direction composed of a memory element array, a sense amplifier arranged between the two small memory blocks, and word lines, data lines, and column selects arranged on the memory element array a plurality of memory blocks arranged in the column direction in a line;

a column decoder disposed at one of two ends in the column direction and connected to at least one of the column selection lines;

A plurality of row decoders connected to the word line are arranged at one of the two ends of the row direction and each of the middle memory blocks is provided with one;

a DQ buffer disposed at the other of the two ends in the column direction; and

An element array controller configured on the other side of the two ends in the row direction and controlling the reading or writing operation of the multi-bit data, and

83. A memory system, provided with a memory chip, a plurality of main memory units composed of a plurality of sub-memory units arranged on the memory chip, and a plurality of bits configured on the memory chip synchronously with a clock The data input and output area for data input and output is a sub-memory of the plurality of main memory units in which two or more sub-memory units are commonly arranged and extend in the row direction among all the sub-memory units of the plurality of main memory units. A plurality of data buses of the multi-bit data path between the unit and the data input and output area, a CPU chip generating the clock signal, and an I/O chip interconnecting the memory chip and the CPU chip O line, characterized by,

Each of the plurality of sub-memory chips includes:

It has two small memory blocks formed by a memory element array and arranged in the column direction, a sense amplifier arranged between the two small memory blocks, and word lines, data lines, and column selection arranged on the memory element array. , a plurality of storage blocks arranged in the column direction;

A column decoder configured and connected to at least one of the column selection lines at one of the two ends in the column direction;

A row decoder connected to the word line is arranged at one of the two ends in the row direction and provided in each of the middle memory blocks;

a DQ buffer disposed at the other of the two ends in the column direction; and

Each of the plurality of sub-memory cells is configured to read or write the multi-bit data independently of each other.

84. A memory system, provided with a memory chip, a plurality of main memory units composed of a plurality of sub-memory units configured on the memory chip, and configured on the memory chip to perform multi-bit data synchronously with a clock A plurality of data input and output areas for the input and output of the plurality of main memory units constitute the plurality of sub-memory units in which two or more sub-memory units are commonly arranged and extend along the row direction as the sub-memory units of the plurality of main memory units. The data bus of the multi-bit data path between the memory unit and the data input and output interval, the CPU chip that generates the clock signal, and the I/O chip that interconnects the memory chip and the CPU chip O line, characterized by,

Each of the plurality of sub-memory units includes:

There are two small memory blocks arranged in the column direction composed of a memory element array, a sense amplifier arranged between the two small memory blocks, and word lines, data lines, and column selection lines arranged on the memory element array , the middle storage block configured in the column direction;

a column decoder configured at one of the two ends in the column direction and connected to at least one of the column selection lines;

A plurality of row decoders arranged at one of the two ends in the row direction, each of the middle memory blocks is provided with one and connected to the word line;

a DQ buffer disposed at the other of the two ends in the column direction; and

The data buses are respectively arranged on both sides of the row direction of each data input and output area, and the plurality of sub-memory units constituting the plurality of main memory units are arranged on both sides of the column direction of each data bus. side,