CN115454748A - Test board, node selection method and component - Google Patents

Abstract

The application discloses a test board in the technical field of computers, a node selection method and components. The test board provided by this application can be connected to at least two computing nodes in the same server at the same time, so the USB functions of at least two computing nodes in the same server can be tested at the same time, which can save test time, reduce time costs and labor costs, Therefore, the test efficiency of the USB function of the multi-node server is improved. Among them, the test board provided by this solution is directly connected to the PCIe interface of each computing node in the same server, but not directly connected to the USB interface of each computing node, so that the test of the USB function of the node can be realized, and the test process can be reduced. communication loss, and also improves the versatility of the test board. Correspondingly, a node selection method and components provided in the present application also have the above-mentioned technical effects.

Description

A test board, a node selection method and components

technical field

The present application relates to the field of computer technology, in particular to a test board, a node selection method and components.

Background technique

At present, when testing the USB (Universal Serial Bus, Universal Serial Bus) function of each node in the multi-node server, each node in the server needs to be tested separately in turn, that is: a single connection and test the USB function of a node, This will increase the testing time multiple times, increasing time cost and labor cost.

Therefore, how to improve the test efficiency of the USB function of the multi-node server is a problem to be solved by those skilled in the art.

Contents of the invention

In view of this, the purpose of this application is to provide a test board, a node selection method and components, so as to improve the test efficiency of the USB function of the multi-node server. The specific plan is as follows:

In a first aspect, the application provides a test board, comprising: a control circuit, a USB selection chip connected to the control circuit, a USB connector connected to the USB selection chip, and N USB HUB chips (USB hub );

Wherein, the N USB HUB chips are connected to the PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) interface of N computing nodes; the N computing nodes are arranged in the same server;

Wherein, the control circuit is configured to: send selection signals of at least two computing nodes to the USB selection chip;

Correspondingly, the USB selection chip is used to: communicate the link between the PCIe interface of the currently selected computing node and the USB connector according to the selection signal, so as to use the USB connector as the currently selected computing node peripheral connectors.

Optionally, the control circuit includes: a signal input device;

Correspondingly, the control circuit is further configured to: acquire the selection signal through the signal input device.

Optionally, the signal input device is: a physical button or a touch screen.

Optionally, the N USB HUB chips are also connected to BMCs (Baseboard Management Controller, Baseboard Management Controller) of N computing nodes.

Optionally, the USB connector is provided with N USB input ports and N USB output ports.

Optionally, there are multiple USB selection chips.

Optionally, the test board further includes: a plurality of enabling switches, each enabling switch is connected between the control circuit and the USB selection chip.

Optionally, the control circuit is implemented based on CPLD (Complex Programmable Logic Device) or FPGA (Field Programmable Gate Array, field programmable logic gate array).

Optionally, after any USB output port of the USB connector is connected to a USB device, the currently selected computing node performs a management operation on the USB device.

In the second aspect, the present application provides a node selection method, which is applied to the test board described in any one of the above, and the test board includes: a control circuit, a USB selection chip connected to the control circuit, and the The USB connector connected to the USB selection chip and N USB HUB chips; the N USB HUB chips are connected to the PCIe interfaces of N computing nodes; the N computing nodes are located in the same server;

Among them, the method includes:

The control circuit sends selection signals of at least two computing nodes to the USB selection chip;

The USB selection chip connects the link between the PCIe interface of the currently selected computing node and the USB connector according to the selection signal, so as to use the USB connector as a peripheral connector of the currently selected computing node.

Optionally, the control circuit includes: a signal input device;

Correspondingly, the control circuit is further configured to: acquire the selection signal through the signal input device.

Optionally, the signal input device is: a physical button or a touch screen.

Optionally, the N USB HUB chips are also connected to BMCs of N computing nodes.

Optionally, the USB connector is provided with N USB input ports and N USB output ports.

Optionally, there are multiple USB selection chips.

Optionally, the test board further includes: a plurality of enabling switches, each enabling switch is connected between the control circuit and the USB selection chip.

Optionally, the control circuit is implemented based on CPLD or FPGA.

Optionally, after any USB output port of the USB connector is connected to a USB device, the currently selected computing node performs a management operation on the USB device.

In a third aspect, the present application provides an electronic device, including:

memory for storing computer programs;

A processor, configured to execute the computer program, so as to implement the node selection method disclosed above.

In a fourth aspect, the present application provides a readable storage medium for storing a computer program, wherein the computer program implements the node selection method disclosed above when executed by a processor.

It can be seen from the above scheme that the present application provides a test board, including: a control circuit, a USB selection chip connected to the control circuit, a USB connector connected to the USB selection chip, and N USB HUB chips; wherein , the N USB HUB chips are connected to the PCIe interfaces of N computing nodes; the N computing nodes are set in the same server; wherein the control circuit is used to: send at least two computing nodes to the USB selection chip correspondingly, the USB selection chip is used to: communicate the link between the PCIe interface of the currently selected computing node and the USB connector according to the selection signal, so as to use the USB connector as the current Peripheral connectors for selected compute nodes.

It can be seen that the test board provided by this application can be connected to at least two computing nodes in the same server at the same time, so the USB function of at least two computing nodes in the same server can be tested at the same time, that is: a single connection and test at least two The USB function of the calculation node can save test time, reduce time cost and labor cost, thereby improving the test efficiency of the USB function of the multi-node server. Among them, the communication loss of the PCIe link is smaller than that of the USB link, so the test board provided by this solution is directly connected to the PCIe interface of each computing node in the same server, but not directly connected to the USB interface of each computing node. Realizing the test of the USB function of the node can reduce the communication loss in the test process and improve the versatility of the test board.

Correspondingly, a node selection method and components provided in the present application also have the above-mentioned technical effects. A component is: a device, a device, or a readable storage medium.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present application, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

Fig. 1 is a kind of test board schematic diagram disclosed in the present application;

Fig. 2 is another kind of test board schematic diagram disclosed by the present application;

FIG. 3 is a schematic diagram of circuit connections of individual modules in the test board disclosed in the present application.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

At present, when testing the USB function of each node in a multi-node server, it is necessary to test each node in the server in turn, that is, to test the USB function of a node in a single connection, which will increase the test time multiple times and increase the time and labor costs. Therefore, the present application provides a test board, which can simultaneously test the USB functions of at least two computing nodes in the same server, and improve the test efficiency of the USB functions of the multi-node server.

Referring to Fig. 1, the embodiment of the present application discloses a test board, including: a control circuit, a USB selection chip connected to the control circuit, a USB connector connected to the USB selection chip, and N USB HUB chips; wherein, N USB HUB chips are connected to the PCIe interfaces of N computing nodes; N computing nodes are set in the same server. It can be seen that the server is a multi-node server.

Wherein, the control circuit is used to: send selection signals of at least two computing nodes to the USB selection chip; correspondingly, the USB selection chip is used to: connect the PCIe interface of the currently selected computing node to the USB connector according to the selection signal. to use the USB connector as a peripheral connector for the currently selected compute node. The currently selected computing node is: the computing node that needs to perform the USB function test. The selection signal may carry corresponding identification information of the currently selected computing node, so that the USB selection chip determines the link to be connected and the link to be disconnected according to the identification information.

As shown in Figure 1, the PCIe interface of the computing node is PCIe Gen2 standard. Certainly, the PCIe interface of the computing node may also be a PCIe standard of other specifications.

Among them, the USB HUB chip and the USB selection chip can have multiple channels, for example, the USB HUB chip is UPD720201 with four channels, and the USB selection chip is HD3SS3412 with four channels. Among them, the four-channel chip means: the chip can transmit four channels of signals.

In a specific implementation manner, the control circuit includes: a signal input device. The user can input the desired computing node through the signal input device. Correspondingly, the control circuit is also used for: obtaining the selection signal through the signal input device. Wherein, the signal input device is: a physical button or a touch screen.

In one example, the user can select a computing node that needs to test the USB function through a physical button or a touch screen. At this time, the physical button or the touch screen obtains a selection signal, and the control circuit transmits the selection signal to the USB selection chip, so that the USB selection chip follows the This selection signal connects the link between the PCIe interface of the computing node selected by the user and the USB connector, so that the USB connector in the test board is used as the peripheral connector of the computing node selected by the user. Of course, the signal input device can also be: a terminal. The terminal specifically may include, but is not limited to, a smart phone, a tablet computer, a notebook computer or a desktop computer, and the like.

Among them, the N USB HUB chips of the test board are also connected to the BMCs of N computing nodes, so that the KVM function can be realized based on the BMCs of the computing nodes.

In a specific implementation manner, the USB connector of the test board is provided with N USB input ports and N USB output ports. Among them, there are multiple USB selection chips of the test board. Correspondingly, the test board further includes: a plurality of enabling switches (EFUSE as shown in FIG. 3 ), each enabling switch is connected between the control circuit and the USB selection chip. Among them, the USB input port of the USB connector is shown in Figure 2 as two USB3.0 of the dual USB connector, and the USB output port of the USB connector is on the opposite side of the USB input port, as shown in Figure 2 A and B. The USB input port and the USB output port of the USB connector adopt the same USB standard.

In a specific implementation manner, the control circuit of the test board is implemented based on CPLD or FPGA. When the control circuit is a CPLD, the connection relationship between the CPLD and the USB selection chip, the USB selection chip, the USB HUB chip, and the USB connector can be referred to in FIG. 3 . As shown in Figure 3, the USB HUB chip converts the PCIe Gen2 x1 signal transmitted by the node into a USB signal, and the USB signal is subsequently connected to the USB selection chip. The USB Switch chip can switch a pair of USB3.0 TX signals, a pair of USB3.0 RX signals and a pair of USB2.0 signals. The USB connector is used to connect USB devices. The CPLD indirectly controls the VCC power supply of the USB selection chip through the enable switch EFUSE, which is equivalent to the output enable (OE) function. When the node is not selected, the corresponding link connection is disconnected. If a certain node is selected, the public selection pin SEL of the USB selection chip is directly controlled to select that the USB signal comes from a certain node. When OE is not enabled, the chip has no power supply, and all switches are in a high-impedance off state, which has nothing to do with the pin SEL. When OE enables EFUSE, pin SEL selects one of the two access signals (low impedance on state).

In one example, after any USB output port of the USB connector is connected to the USB device, the currently selected computing node can perform management operations on the USB device, such as: performing security configuration on the USB device (such as: setting a key), reading Data in the USB device, writing data to the USB device, etc. When the USB device is a storage device, management operations such as partitioning can be performed on the USB device. In this way, the USB function of the currently selected computing node can be tested. Wherein, for specific implementation steps of testing the USB function of the computing node, reference may be made to existing related technologies, which will not be repeated in this embodiment.

It can be seen that the test board provided by this embodiment can connect at least two computing nodes in the same server at the same time, so the USB functions of at least two computing nodes in the same server can be tested at the same time, that is: a single connection and test at least two The USB function of a computing node can save test time, reduce time cost and labor cost, thereby improving the test efficiency of the USB function of a multi-node server. Among them, the communication loss of the PCIe link is smaller than that of the USB link, so the test board provided by this solution is directly connected to the PCIe interface of each computing node in the same server, but not directly connected to the USB interface of each computing node. Realizing the test of the USB function of the node can reduce the communication loss in the test process and improve the versatility of the test board.

Please refer to Figure 2, if N is 2, then the server is a dual-node server. At this time, two USB selection chips are set in the test board, so that the USB connector can be realized: the output ports A and B are used for nodes 1 and 2 respectively, or both output ports A and B are used as the USB interface of node 1, or Both output ports A and B are used as USB ports of node 1.

As shown in Figure 2, in the dual-node server architecture, the two nodes transmit PCIe Gen2 x1 to the test board, and implement PCIe to USB3.0 through UPD720201 (a USB HUB chip), and then transfer it to USB3. Chip) strobe, so that the USB connector supports two USB3.0 interfaces for connecting USB devices. The node CPU and the test board are connected through a common PCIe, which is convenient for realization: the same test board can test different nodes.

Among them, since UPD720201 is a four-channel USB HUB chip, there are two USB signals connected to the BMC of the corresponding computing node, thereby realizing the KVM function, as shown in Figure 2. Any HD3SS3412 in Figure 2 can choose to connect the link corresponding to node 1 or connect the link corresponding to node 2, so that the two USB interfaces A and B of the dual USB connector can be used by the corresponding node. As shown in FIG. 2 , the signals on one link may include: a pair of USB3.0 TX, a pair of USB3.0 RX and a pair of USB2.0 signals.

Specifically, when the control circuit shown in FIG. 2 is a CPLD, refer to FIG. 3 for the specific connection relationship between the CPLD and HD3SS3412, HD3SS3412, UPD720201 and dual USB connectors. As shown in Figure 3, the PCIe to USB3.0 chip UPD720201 converts the PCIe Gen2 x1 signal transmitted by the node into a USB signal, and the USB signal is subsequently connected to two HD3SS3412. The USBSwitch chip HD3SS3412 is a four-channel selector, which can switch a pair of USB3.0 TX signals, a pair of USB3.0 RX signals and a pair of USB2.0 signals. The dual USB connectors are divided into upper and lower interfaces, each controlled by one HD3SS3412, and supports two USB3.0 interfaces, so it can be backward compatible with USB2.0 for connecting USB devices.

CPLD indirectly controls the VCC power supply of HD3SS3412 through the enable switch EFUSE, which is equivalent to the output enable (OE) function. When neither node is selected, the corresponding link connection is disconnected. If a certain node is selected, directly control the public selection pin SEL of HD3SS3412 to select the USB signal from node 1 or node 2. When OE is not enabled, the chip has no power supply, and all switches are in a high-impedance off state, which has nothing to do with the pin SEL. When OE enables EFUSE, pin SEL selects one of the two access signals (low impedance on state).

It can be seen that this embodiment uses two USB Switch chips to select nodes respectively. When the two SELs are set to the same level, they switch to USB normal mode (two USB ports belong to the same node at the same time). When the two SELs are set to different When the level is low, switch to the USB device mode (each node corresponds to a USB port), see Table 1 for details.

Table 1

As shown in Table 1, in the equipment mode, the two nodes correspond to different USB ports in the USB connector, so the two nodes can be tested at the same time, which reduces the test time, test cost and operation and maintenance difficulty. The dual-node, dual-USB design shown in Figure 2 can effectively realize that the same USB device is plugged into different nodes, which improves the test efficiency of the multi-node server.

It can be seen that this embodiment can select a single or multiple nodes for testing according to the requirements. The same test board can correspond to a single node or to different nodes at the same time, which saves test time, improves test flexibility, and can also reduce production. Cost and post-board repair and maintenance costs.

A node selection method provided in the embodiment of the present application is introduced below, and a node selection method described below and a test board described above may refer to each other.

The embodiment of the present application discloses a node selection method, which is applied to the test board described in any of the above embodiments. The test board includes: a control circuit, a USB selection chip connected to the control circuit, and a USB selection chip connected to the USB selection chip. Connector and N USB HUB chips; N USB HUB chips are connected to PCIe interfaces of N computing nodes; N computing nodes are set in the same server. Among them, the USB HUB chip and the USB selection chip can have multiple channels, for example, the USB HUB chip is UPD720201 with four channels, and the USB selection chip is HD3SS3412 with four channels. Among them, the four-channel chip means: the chip can transmit four channels of signals.

Among them, the node selection method provided by the embodiment of the present application includes: the control circuit sends selection signals of at least two computing nodes to the USB selection chip; the USB selection chip connects the PCIe interface of the currently selected computing node to the USB connector according to the selection signal link to use the USB connector as a peripheral connector for the currently selected compute node. The currently selected computing node is: the computing node that needs to perform the USB function test. The selection signal may carry corresponding identification information of the currently selected computing node, so that the USB selection chip determines the link to be connected and the link to be disconnected according to the identification information.

In a specific implementation manner, the control circuit includes: a signal input device; the control circuit is further configured to: acquire a selection signal through the signal input device.

In a specific implementation manner, the signal input device is: a physical button or a touch screen. In one example, the user can select a computing node that needs to test the USB function through a physical button or a touch screen. At this time, the physical button or the touch screen obtains a selection signal, and the control circuit transmits the selection signal to the USB selection chip, so that the USB selection chip follows the This selection signal connects the link between the PCIe interface of the computing node selected by the user and the USB connector, so that the USB connector in the test board is used as the peripheral connector of the computing node selected by the user.

In a specific implementation manner, N USB HUB chips are also connected to BMCs of N computing nodes.

In a specific implementation manner, the USB connector is provided with N USB input ports and N USB output ports.

In a specific implementation manner, there are multiple USB selection chips.

In a specific implementation manner, the test board further includes: a plurality of enabling switches, each enabling switch is connected between the control circuit and the USB selection chip.

In a specific implementation manner, the control circuit is realized based on CPLD or FPGA.

In a specific implementation manner, after any USB output port of the USB connector is connected to the USB device, the currently selected computing node performs management operations on the USB device. For example, perform security configuration on the USB device (such as setting a key), read data in the USB device, write data to the USB device, etc., so as to test the USB function of the currently selected computing node.

For the more specific working process of each module and unit in this embodiment, reference may be made to the corresponding content disclosed in the foregoing embodiments, and details are not repeated here.

As shown in Figure 2, in the dual-node server architecture, the two nodes transmit PCIe Gen2 x1 to the test board, and implement PCIe to USB3.0 through UPD720201 (a USB HUB chip), and then transfer it to USB3. Chip) strobe, so that the USB connector supports two USB3.0 interfaces for connecting USB devices. The node CPU and the test board are connected through a common PCIe, which is convenient for realization: the same test board can test different nodes.

Among them, since UPD720201 is a four-channel USB HUB chip, there are two USB signals connected to the BMC of the corresponding computing node, thereby realizing the KVM function, as shown in Figure 2. Any HD3SS3412 in Figure 2 can choose to connect the link corresponding to node 1 or connect the link corresponding to node 2, so that the two USB interfaces A and B of the dual USB connector can be used by the corresponding node. As shown in Table 1, in the equipment mode, the two nodes correspond to different USB ports in the USB connector, so the two nodes can be tested at the same time, which reduces the test time, test cost and operation and maintenance difficulty. The dual-node, dual-USB design shown in Figure 2 can effectively realize that the same USB device is plugged into different nodes, which improves the test efficiency of the multi-node server.

It can be seen that the test board provided by this embodiment can connect at least two computing nodes in the same server at the same time, so the USB functions of at least two computing nodes in the same server can be tested at the same time, that is: a single connection and test at least two The USB function of a computing node can save test time, reduce time cost and labor cost, thereby improving the test efficiency of the USB function of a multi-node server. Among them, the communication loss of the PCIe link is smaller than that of the USB link, so the test board provided by this solution is directly connected to the PCIe interface of each computing node in the same server, but not directly connected to the USB interface of each computing node. Realizing the test of the USB function of the node can reduce the communication loss in the test process and improve the versatility of the test board.

An electronic device provided by an embodiment of the present application is introduced below, and the electronic device described below and the method and apparatus for selecting a node described above may refer to each other.

The embodiment of this application discloses an electronic device, including:

memory for storing computer programs;

A processor, configured to execute the computer program, so as to implement the method disclosed in any of the above embodiments.

Further, the embodiment of the present application also provides a server as the above-mentioned electronic device. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input and output interface, and a communication bus. Wherein, the memory is used to store a computer program, and the computer program is loaded and executed by the processor, so as to implement relevant steps in the node selection method disclosed in any of the foregoing embodiments.

In this embodiment, the power supply is used to provide working voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows is applicable to the technical solution of this application Any communication protocol is not specifically limited here; the input/output interface is used to obtain external input data or output data to the external, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

In addition, memory, as a resource storage carrier, can be read-only memory, random access memory, magnetic disk or optical disk, etc. The resources stored on it include operating system, computer program and data, etc., and the storage method can be temporary storage or permanent storage.

Wherein, the operating system is used to manage and control various hardware devices and computer programs on the server, so as to realize the calculation and processing of the data in the memory by the processor, which may be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the node selection method disclosed in any of the foregoing embodiments, the computer program can further include a computer program that can be used to complete other specific tasks. In addition to data such as the virtual machine, the data may also include data such as developer information of the virtual machine.

Further, the embodiment of the present application also provides a terminal as the above-mentioned electronic device. The terminal specifically may include, but is not limited to, a smart phone, a tablet computer, a notebook computer or a desktop computer, and the like.

Generally, the terminal in this embodiment includes: a processor and a memory.

Wherein, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor can be realized by at least one hardware form of DSP (Digital Signal Processing, digital signal processing), FPGA (Field-Programmable Gate Array, field programmable gate array), PLA (Programmable Logic Array, programmable logic array) . The processor can also include a main processor and a coprocessor, the main processor is a processor for processing data in the wake-up state, also called a CPU (Central Processing Unit, central processing unit); Low-power processor for processing data in standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit, image processor), and the GPU is used for rendering and drawing content that needs to be displayed on the display screen. In some embodiments, the processor may further include an AI (Artificial Intelligence, artificial intelligence) processor, where the AI processor is configured to process computing operations related to machine learning.

The memory may include one or more computer-readable storage media, which may be non-transitory. Memory may also include high-speed random access memory, and non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory is at least used to store the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps in the node selection method performed by the terminal side disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Wherein, the operating system may include Windows, Unix, Linux and so on. Data may include, but is not limited to, application update information.

In some embodiments, the terminal may further include a display screen, an input/output interface, a communication interface, a sensor, a power supply, and a communication bus.

Further, the server provided by the embodiment of the present application is a multi-node server, which includes N computing nodes, and the PCIe interfaces of the N computing nodes are connected to N USB HUB chips of the test board, so that the USB connector of the test board It can be used as a peripheral connector for any node among N computing nodes. Wherein, the test board includes: a control circuit, a USB selection chip connected to the control circuit, a USB connector connected to the USB selection chip, and N USB HUB chips. Wherein, the control circuit can send selection signals of at least two computing nodes to the USB selection chip; correspondingly, the USB selection chip can connect the link between the PCIe interface of the currently selected computing node and the USB connector according to the selection signal to The USB connector serves as the peripheral connector of the currently selected computing node, that is, the USB connector can simultaneously serve as the peripheral connector of at least two computing nodes among the N computing nodes.

In a specific implementation manner, the control circuit includes: a signal input device; the control circuit is further configured to: acquire a selection signal through the signal input device.

In a specific implementation manner, the signal input device is: a physical button or a touch screen. In one example, the user can select a computing node that needs to test the USB function through a physical button or a touch screen. At this time, the physical button or the touch screen obtains a selection signal, and the control circuit transmits the selection signal to the USB selection chip, so that the USB selection chip follows the This selection signal connects the link between the PCIe interface of the computing node selected by the user and the USB connector, so that the USB connector in the test board is used as the peripheral connector of the computing node selected by the user.

In a specific implementation manner, N USB HUB chips are also connected to BMCs of N computing nodes.

In a specific implementation manner, the USB connector is provided with N USB input ports and N USB output ports.

In a specific implementation manner, there are multiple USB selection chips.

In a specific implementation manner, the test board further includes: a plurality of enabling switches, each enabling switch is connected between the control circuit and the USB selection chip.

In a specific implementation manner, the control circuit is realized based on CPLD or FPGA.

In a specific implementation manner, after any USB output port of the USB connector is connected to the USB device, the currently selected computing node performs management operations on the USB device. For example, perform security configuration on the USB device (such as setting a key), read data in the USB device, write data to the USB device, etc., so as to test the USB function of the currently selected computing node.

In an example, if N is 2, then the server is a dual-node server. As shown in Figure 2, in the dual-node server architecture, the two nodes transmit PCIe Gen2 x1 to the test board, and implement PCIe to USB3.0 through UPD720201 (a USB HUB chip), and then transfer it to USB3. Chip) strobe, so that the USB connector supports two USB3.0 interfaces for connecting USB devices. The node CPU and the test board are connected through a common PCIe, which is convenient for realization: the same test board can test different nodes.

Among them, since UPD720201 is a four-channel USB HUB chip, there are two USB signals connected to the BMC of the corresponding computing node, thereby realizing the KVM function, as shown in Figure 2. Any HD3SS3412 in Figure 2 can choose to connect the link corresponding to node 1 or connect the link corresponding to node 2, so that the two USB interfaces A and B of the dual USB connector can be used by the corresponding node. As shown in Table 1, in the equipment mode, the two nodes correspond to different USB ports in the USB connector, so the two nodes can be tested at the same time, which reduces the test time, test cost and operation and maintenance difficulty. The dual-node, dual-USB design shown in Figure 2 can effectively realize that the same USB device is plugged into different nodes, which improves the test efficiency of the multi-node server.

A readable storage medium provided by an embodiment of the present application is introduced below. The readable storage medium described below and the node selection method, device, and device described above may refer to each other.

A readable storage medium is used to store a computer program, wherein, when the computer program is executed by a processor, the node selection method disclosed in the foregoing embodiments is implemented. Wherein, the readable storage medium may be non-transitory. Memory may also include high-speed random access memory, and non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices.

In this embodiment, the readable storage medium may be a memory in the test board. The test board includes: a control circuit, a USB selection chip connected to the control circuit, a USB connector connected to the USB selection chip, and N USBHUB chips. The PCIe interfaces of the N computing nodes in the multi-node server are connected to the N USB HUB chips of the test board, so that the USB connector of the test board can be used as a peripheral connector of any node in the N computing nodes.

Specifically, the control circuit can send selection signals of at least two computing nodes to the USB selection chip; correspondingly, the USB selection chip can connect the link between the PCIe interface of the currently selected computing node and the USB connector according to the selection signal to The USB connector is used as the peripheral connector of the currently selected computing node, that is, the USB connector can be used as the peripheral connector of at least two computing nodes among the N computing nodes at the same time.

In a specific implementation manner, the control circuit includes: a signal input device; the control circuit is further configured to: acquire a selection signal through the signal input device.

In a specific implementation manner, the signal input device is: a physical button or a touch screen. In one example, the user can select a computing node that needs to test the USB function through a physical button or a touch screen. At this time, the physical button or the touch screen obtains a selection signal, and the control circuit transmits the selection signal to the USB selection chip, so that the USB selection chip follows the This selection signal connects the link between the PCIe interface of the computing node selected by the user and the USB connector, so that the USB connector in the test board is used as the peripheral connector of the computing node selected by the user.

In a specific implementation manner, N USB HUB chips are also connected to BMCs of N computing nodes.

In a specific implementation manner, the USB connector is provided with N USB input ports and N USB output ports.

In a specific implementation manner, there are multiple USB selection chips.

In a specific implementation manner, the test board further includes: a plurality of enabling switches, each enabling switch is connected between the control circuit and the USB selection chip.

In a specific implementation manner, the control circuit is realized based on CPLD or FPGA.

In a specific implementation manner, after any USB output port of the USB connector is connected to the USB device, the currently selected computing node performs management operations on the USB device. For example, perform security configuration on the USB device (such as setting a key), read data in the USB device, write data to the USB device, etc., so as to test the USB function of the currently selected computing node.

"First", "second", "third", "fourth" and the like referred to in the present application, if any, are used to distinguish similar objects and not necessarily to describe a specific order or sequence. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, e.g. a process, method or apparatus comprising a series of steps or elements is not necessarily limited to those steps or elements explicitly listed , but may include other steps or elements not explicitly listed or inherent to the process, method or apparatus.

It should be noted that the descriptions in this application involving "first", "second" and so on are for descriptive purposes only, and should not be understood as indicating or implying their relative importance or implicitly indicating the number of indicated technical features . Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In addition, the technical solutions of the various embodiments can be combined with each other, but it must be based on the realization of those skilled in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist , nor within the scope of protection required by the present application.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same or similar parts of each embodiment can be referred to each other.

The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be directly implemented by hardware, software modules executed by a processor, or a combination of both. Software modules can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other Any other known readable storage medium.

In this paper, specific examples are used to illustrate the principles and implementation methods of the application. The descriptions of the above embodiments are only used to help understand the method and core idea of the application; meanwhile, for those of ordinary skill in the art, according to the application There will be changes in the specific implementation and scope of application. In summary, the content of this specification should not be construed as limiting the application.

Claims (10)

1. a test board, is characterized in that, comprises: control circuit, the USB selection chip that is connected with described control circuit, the USB connector that is connected with described USB selection chip and N USB HUB chips; Wherein, the N USB HUB chips are connected to the PCIe interfaces of N computing nodes; the N computing nodes are arranged in the same server; Wherein, the control circuit is configured to: send selection signals of at least two computing nodes to the USB selection chip; Correspondingly, the USB selection chip is used to: connect the link between the PCIe interface of the currently selected computing node and the USB connector according to the selection signal, so as to use the USB connector as the currently selected computing node peripheral connectors. 2. test board according to claim 1, is characterized in that, The control circuit includes: a signal input device; Correspondingly, the control circuit is further configured to: acquire the selection signal through the signal input device. 3. The test board according to claim 2, wherein the signal input device is: a physical button or a touch screen. 4. The test board according to claim 1, wherein the N USB HUB chips are also connected to BMCs of N computing nodes. 5. The test board according to claim 1, wherein the USB connector is provided with N USB input ports and N USB output ports. 6. The test board according to any one of claims 1-5, wherein there are multiple USB selection chips. 7. The test board according to claim 6, wherein the test board further comprises: a plurality of enabling switches, each enabling switch being connected between the control circuit and the USB selection chip . 8. A node selection method, characterized in that it is applied to the test board as claimed in any one of claims 1 to 7, and the test board comprises: a control circuit, a USB selection chip connected to the control circuit , a USB connector connected to the USB selection chip and N USB HUB chips; the N USB HUB chips are connected to the PCIe interfaces of N computing nodes; the N computing nodes are located in the same server; Among them, the method includes: The control circuit sends selection signals of at least two computing nodes to the USB selection chip; The USB selection chip connects the link between the PCIe interface of the currently selected computing node and the USB connector according to the selection signal, so as to use the USB connector as a peripheral connector of the currently selected computing node. 9. An electronic device, characterized in that it comprises: memory for storing computer programs; A processor configured to execute the computer program to implement the method as claimed in claim 8. 10. A readable storage medium, characterized by being used to store a computer program, wherein the computer program implements the method according to claim 8 when executed by a processor.

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