CN115441874B - A 14-bit resolution two-stage circular analog-to-digital converter - Google Patents

Abstract

A 14-bit resolution two-stage circular analog-to-digital converter includes a 6-bit resolution first-stage multiplication digital-to-analog converter unit, a 9-bit resolution second-stage multiplication digital-to-analog converter unit, a redundant addition module, and a clock phase high-precision adjustable module. The present invention greatly reduces power consumption compared to a single-stage 14-bit circular analog-to-digital converter through a "6-bit + 9-bit" two-stage circular structural design, meeting the application of low-power analog-to-digital conversion.

Description

A 14-bit resolution two-stage circular analog-to-digital converter

Technical Field

The invention relates to an analog-to-digital converter, in particular to a two-stage circular analog-to-digital converter with a 14-bit resolution.

Background Art

As an important module for communication between digital and analog signals, analog-to-digital converters are often used in image processing, digital base stations and other fields. The analog-to-digital converter samples the input analog signal at a specified time interval and compares it with a series of standard digital signals. The digital signals converge one by one until the two signals are equal, and finally a binary number representing the signal is obtained. The cyclic analog-to-digital converter is a cyclic structure in the analog-to-digital converter. It has the characteristics of low power consumption and small area, and is widely used in image sensors.

The current analog-to-digital converters have high power consumption problems due to their high accuracy requirements. The realization of low power consumption has always been a difficult point in the design of analog-to-digital converters.

Summary of the invention

The problem solved by the present invention is to overcome the deficiencies in the prior art and propose a two-stage cyclic analog-to-digital converter with a 14-bit resolution. The two-stage design with a 6-bit resolution and a 9-bit resolution can significantly reduce power consumption and meet high-speed analog-to-digital conversion applications.

The present invention solves the above technical problems by the following technical solutions:

A 14-bit resolution two-stage circular analog-to-digital converter, comprising a first-stage multiplication digital-to-analog converter unit MDAC1 with a 6-bit resolution and a second-stage multiplication digital-to-analog converter unit MDAC2 with a 9-bit resolution, wherein both the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2 are circular structures;

The first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2 operate in the form of pipeline operation;

The first-stage multiplication digital-to-analog converter unit MDAC1 receives the input signal, obtains the upper 6-bit conversion result after 5 cycles of processing, and transmits the upper 6-bit conversion result to the second-stage multiplication digital-to-analog converter unit MDAC2;

The second-stage multiplication digital-to-analog converter unit MDAC2 receives the high-order 6-bit conversion result, and after 8 cycles of the same processing as the first-stage multiplication digital-to-analog converter, outputs the low-order 9-bit conversion result;

The high 6-bit conversion result and the low 9-bit conversion result are processed, and the 14-bit conversion result synthesized by offset addition is used as the output data of the entire analog-to-digital converter.

Preferably, the form of pipeline operation is: the first-stage multiplication digital-to-analog converter unit MDAC1 passes the result to the second-stage multiplication digital-to-analog converter unit MDAC2 after completing the conversion of the upper 6 bits, and while the second stage completes the lower 9-bit quantization result, the first stage completes the conversion of the upper 6 bits of the next signal; the conversion time of the first-stage multiplication digital-to-analog converter unit MDAC1 is equal to the conversion time of the second-stage multiplication digital-to-analog converter unit MDAC2 and is equal to the conversion time of the entire analog-to-digital converter.

Preferably, each processing process of the first-stage multiplication digital-to-analog converter unit MDAC1 is: sampling the input signal, which is called the sampling state; then performing data processing on the input signal, which is called the holding state, and performing the next sampling operation in the sampling state while working in the holding state; each processing obtains a 1.5-bit result, and after 5 cycles, the high 6-bit conversion result is output after staggered addition.

Preferably, the first-stage multiplication digital-to-analog converter unit MDAC1 includes a 1.5-bit analog-to-digital converter, a 1.5-bit digital-to-analog converter, switches driven by different timings, a capacitor array, and a differential operational amplifier;

The two input signals at the input end of the differential operational amplifier are sampled by the capacitor group used for sampling in the capacitor array through the switches driven by the timing sequence, and the sampling results are stored in the capacitor group to complete the sampling state operation; while sampling, the input signal is quantized by 1.5 bits through the 1.5-bit analog-to-digital converter;

After the sampling is completed, the circuit enters the holding state. Through switch control, the capacitor is connected to the output of the 1.5-bit digital-to-analog converter module. The output end of the differential operational amplifier charges the capacitor group used for the holding state in the capacitor array. The capacitor group voltage completes the multiplication and bias function operation in the process of forming a new equilibrium state. The operation result is stored in the capacitor group, and the result is sampled by the sampling capacitor of the next sampling state as the result of the holding state.

Preferably, each processing process of the second-stage multiplication digital-to-analog converter unit MDAC2 is: sampling the input signal, which is called the sampling state; then performing data processing on the input signal, which is called the holding state, and performing the next sampling operation in the sampling state while working in the holding state; each processing obtains a 1.5-bit result, and after 8 cycles, the low 9-bit conversion result is output after staggered addition.

Preferably, the second-stage multiplication digital-to-analog converter unit MDAC2 includes a 1.5-bit analog-to-digital converter, a 1.5-bit digital-to-analog converter, switches driven by different timing sequences, a capacitor array, and a differential operational amplifier;

The two input signals at the input end of the differential operational amplifier are sampled by the capacitor group used for sampling in the capacitor array through the switches driven by the timing sequence, and the sampling results are stored in the capacitor group to complete the sampling state operation; while sampling the input signal, 1.5-bit quantization is performed through the 1.5-bit analog-to-digital converter;

After the sampling is completed, the circuit enters the holding state. Through switch control, the capacitor is connected to the output of the 1.5-bit digital-to-analog converter module. The output end of the differential operational amplifier charges the capacitor group used for the holding state in the capacitor array. The capacitor group voltage completes the multiplication and bias function operation in the process of forming a new equilibrium state. The operation result is stored in the capacitor group, and the result is sampled by the sampling capacitor of the next sampling state as the result of the holding state.

Preferably, it also includes a redundant addition module, which is used to perform redundant addition operations on the upper 6-bit conversion result and the lower 9-bit conversion result, subtract one redundant bit, and synthesize a 14-bit conversion result.

Preferably, it also includes a high-precision adjustable clock phase module to drive the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2, and control the first-stage multiplication digital-to-analog converter unit MDAC2 and the second-stage multiplication digital-to-analog converter unit MDAC2 to operate in a pipelined operation mode.

Preferably, the high-precision adjustable clock phase module is composed of the output signal of the same-phase clock unit, the output signal of the two-phase non-overlapping unit and the AND operation unit. The same-phase clock signal and the different-phase clock signal are operated to obtain different timing clock signals to control the on and off of the switches of the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2.

Preferably, the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2 are both modularly designed and have the same circuit structure, which facilitates replacement.

The advantages of the present invention compared with the prior art are:

(1) Compared with a single-stage cyclic ADC, a two-stage cyclic ADC can significantly reduce power consumption at the same conversion rate, thus meeting the requirements of high-speed cyclic ADC applications.

(2) At the same conversion rate, the power consumption of the "6-bit + 9-bit" architecture is only one-third of that of the single-stage 14-bit architecture, which has a power consumption advantage. At the same time, compared with other two-stage architectures, the power consumption is the lowest at the same conversion rate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of an embodiment of a two-stage cyclic analog-to-digital converter with a 14-bit resolution according to the present invention;

FIG2 is a schematic diagram of a holding state of a cyclic analog-to-digital conversion unit, a is an integrator structure in the holding state, and b is a diagram showing the relationship between input and output signals.

Specific implementation methods

In order to facilitate the understanding of the present invention, the following will be further explained by taking specific embodiments as examples in conjunction with the drawings, and the embodiments do not constitute a limitation on the embodiments of the present invention.

The present invention conducts in-depth theoretical research and experimental verification on the analog-to-digital converter, and solves the design problem of achieving low power consumption of a 14-bit resolution analog-to-digital converter.

The cyclic analog-to-digital converter multiplication digital-to-analog converter unit MDAC is mainly based on a switched capacitor circuit, and the switch capacitor circuit is divided into a sampling state and a holding state. As shown in Figure 2a, it is an integrator structure in the holding state, the charge of the sampling capacitor _CS and the holding capacitor _Cf are redistributed, and the output voltage is established to a multiple of the input voltage to _Cf / _Cs . Figure 2b shows the input-output signal relationship diagram, the input signal is a step signal, and the output signal is limited by the gain-bandwidth product and limited gain of the operational amplifier. After a period of slow establishment, it gradually approaches the high level _Vstep of the input step signal, where the output signal approaches the input step signal as follows:

The difference between the output signal and V _step needs to be smaller than the analog-to-digital converter The single-stage 14-bit ADC usually requires the establishment of an accuracy of According to the above functional relationship, we can get:

Calculated from the above formula, we get t>10.4τ.

Under the same conversion cycle, the higher the number of quantization bits, the shorter the single quantization time of the cyclic analog-to-digital converter. To achieve the corresponding settling accuracy, the op amp needs to have a larger GBW. The relationship between the tail current of the op amp and the GBW is:

Assuming the operating voltage of the analog-to-digital converter is 3.3V, the static power consumption of the op amp is:

P＝I×3.3

Through calculation, the requirements for the establishment accuracy of various analog-to-digital converters with different bit numbers are shown in Table 1:

Table 1 List of requirements for the establishment accuracy of analog-to-digital converters with different bit numbers

For a single-stage structure, the larger the number of quantization bits, the larger the unit capacitance, and the shorter the signal establishment period. The requirements of a single-stage fourteen-bit analog-to-digital converter for the op amp are equivalent to establishing higher accuracy in a shorter time and on a larger capacitance, which will put higher requirements on the GBW of the op amp, thereby increasing the power consumption of the op amp.

In order to reduce power consumption, the present invention abandons the design of a single-stage structure and proposes a technical path of a two-stage structure with one redundant bit. The two-stage structure is composed of two multiplication digital-to-analog conversion modules with different quantization bit numbers. Through pipeline operation, the first stage can quantize the mth signal while the second stage quantizes the first-stage processing result of the m-1th signal, which relaxes the requirement for the first stage's setup time and can significantly reduce power consumption.

Based on the above technical path, different quantization combinations of the 14-bit resolution two-stage circular analog-to-digital converter were analyzed and verified, and the op amp tail current and op amp power consumption under different combinations were obtained. Table 2 gives the data of the better combinations (5+10-1), (6+9-1) and (7+8-1) among all the combinations, where the number of quantization bits refers to the number of quantization bits of the first-stage structure. The first stage needs to use a 1.75pF capacitor to achieve the corresponding noise and matching performance.

Table 2 List of requirements for the establishment accuracy of the first-stage analog-to-digital converter with different bit numbers under the two-stage structure

At the same conversion rate, based on the data in Table 1 and Table 2, a comparison test is conducted on the single-stage structure and the structure with different quantization combinations of two poles, and a total power consumption comparison table as shown in Table 3 is obtained:

Table 3 Total power consumption of 14-bit resolution analog-to-digital converters based on different structures

Architecture Choices Total power consumption Single stage 14 bits 63.7uW 6-bit + 9-bit architecture 12.6+14.7＝23.3uW 7-bit + 8-bit architecture 16.8+10.5=27.3uW 5-bit + 10-bit architecture 9+19.9=28.9uW

From Table 3, it can be concluded that the power consumption of the "6-bit + 9-bit" architecture is only one-third of that of the single-stage 14-bit architecture, which has a greater power consumption advantage. At the same time, compared with the other two combination options, the power consumption is also lower. Especially for multi-channel scenarios such as CMOS image sensor column-level readout circuits, which usually reach the scale of one thousand to ten thousand columns in parallel, the power consumption advantage of a single channel will be greatly manifested in multi-channel applications.

Based on the above system demonstration and analysis, the present invention proposes a fourteen-bit resolution two-stage cyclic analog-to-digital converter, including a first-stage multiplication digital-to-analog converter unit MDAC1 with a 6-bit resolution, a second-stage multiplication digital-to-analog converter unit MDAC2 with a 9-bit resolution, a redundant addition module, and a clock phase high-precision adjustable module. The circuit diagram is shown in Figure 1.

(1) FIG. 1 shows a differential circuit structure, which is divided into two identical upper and lower parts. The first-stage multiplication digital-to-analog converter unit MDAC1 includes capacitors C1p1, C2p1, C3p1 and C1n1, C2n1, _C3n1 with the same capacitance, _φs1p , _φaAp , φ1Ap, _φ2Ap , _φ3Ap , _φ4Ap and _φs1n , _φaAn , _φ1An , _φ2An , _φ3An , _φ4An with the same timing, and _φ3A , _φ4A across the pn parts with the same timing as _φ3Ap , _φ4Ap , _φ3An , _φ4An . The second-stage multiplication digital-to-analog converter unit MDAC2 includes capacitors C1p2, C2p2, C3p2 and C1n2, C2n2, C3n2 with the same capacitance, _φs2p , _φaBp , _φ1Bp , _φ2Bp , _φ3Bp , _φ4Bp and _φs2n , _φaBn , _φ1Bn , _φ2Bn , _φ3Bn , _φ4Bn with the same timing, and _φ3B and _φ4B across the pn parts with the same timing as _φ3Bp , _φ4Bp , _φ3Bn , _φ4Bn .

(2) Clock phase high-precision adjustable module

The clock phase high-precision adjustable module drives the first-stage multiplication digital-to-analog converter unit MDAC1, the second-stage multiplication digital-to-analog converter unit MDAC2 and the redundant addition module, and controls the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2 to work in a pipelined manner.

(3) First-stage multiplication digital-to-analog converter unit MDAC1

The first-stage multiplication digital-to-analog converter unit MDAC1 receives the input signal, and after 5 cycles of processing, it outputs a 1.5-bit result each time, which contains redundant bit information, and outputs the high 6-bit conversion result after staggered addition, and transmits it to the second-stage multiplication digital-to-analog converter unit MDAC2. Among them, the first-stage multiplication digital-to-analog converter unit MDAC1 includes a 1.5-bit comparator, a 1.5-bit digital-to-analog converter, a switch, a capacitor, and a differential operational amplifier. As shown in Figure 1:

The two signals at the input of the differential operational amplifier are sampled by capacitors C1p1 and C3p1 through the switch controlled by _φs1p . At the same time, the switch controlled by _φs1p is opened across the input and output of the differential operational amplifier, short-circuiting the differential operational amplifier. The switch controlled by _φ3Ap is opened, connecting the right ends of the capacitors C1p1 and C3p1 together and charging through the output of the differential operational amplifier. The sampling results are stored in the right ends of the capacitors C1p1 and C3p1. This process is the sampling state. The timing of the switches and the control signals of the n part of C1n1, C2n1 and C3n1 is consistent with that of the p-type circuit part.

After sampling is completed, the switch controlled by _φs1p is closed, the circuit enters the hold state, the switches controlled by _φaAp , _φ1Ap and _φ3Ap are opened, the switches controlled by _φs1p , _φ4Ap and _φ2Ap are closed, the C1p1 capacitor is connected to the output of the 1.5-bit digital-to-analog converter module, the output of the differential operational amplifier charges the left ends of C1p1 and C3p1, and the capacitor voltages of C3p1 and C1p1 complete the multiplication and bias function operation in the process of forming a new equilibrium state. The operation result is stored in the left ends of C2p1 and C3p1, and the result is sampled by the sampling capacitor of the next sampling state as the result of the hold state. The timing of the switches and the control signals of the n part of C1n1, C2n1 and C3n1 is consistent with that of the p-type circuit part.

(4) Second-stage multiplication digital-to-analog converter unit MDAC2

The second-stage multiplication digital-to-analog converter unit MDAC2 receives the high 6-bit conversion result of the first-stage multiplication digital-to-analog converter unit MDAC1, and outputs the low 9-bit conversion result after 8 cycles of the same processing as the first-stage multiplication digital-to-analog converter. The second-stage multiplication digital-to-analog converter unit MDAC2 includes a 1.5-bit analog-to-digital converter, a 1.5-bit digital-to-analog converter, switches driven by different timings, a capacitor array, and a differential operational amplifier.

The two output signals of the second-stage multiplication digital-to-analog converter unit MDAC2 are sampled by the second-stage capacitors C1p2 and C3p2 through the switch controlled by _φs2p . At the same time, the switch controlled by _φs2p is opened across the input and output terminals of the differential operational amplifier, short-circuiting the differential operational amplifier. The switch controlled by _φ3Bp is opened, connecting the right ends of the capacitors C1p2 and C3p2 together and charging through the output terminal of the differential operational amplifier. The sampling results are stored in the right ends of the capacitors C1p2 and C3p2. This process is the sampling state.

In the holding state of the fifth cycle of the first-stage multiplication digital-to-analog converter unit MDAC1, which is also the sampling state of the first cycle of the second-stage multiplication digital-to-analog converter, the switches controlled by φ _s2p , φ _2Bp , φ _3Bp , φ _aAp , φ _1Ap and φ _3Ap are turned on, and the switches controlled by φ _aBp , φ _1Bp , φ _4Bp , φ _s1p , φ _2Ap and φ _4Ap are turned off. The timing of the control signal of the n-type circuit part is consistent with that of the p-type circuit part.

After the sampling state is completed, the switch controlled by _φs2 is closed, the second-stage multiplication digital-to-analog converter unit MDAC2 circuit enters the holding state, the switches controlled by _φaBp , _φ1Bp and _φ3Bp are opened, the switches controlled by _φs2p , _φ4Bp and _φ2Bp are closed, the C1p2 capacitor is connected to the output of the 1.5-bit digital-to-analog converter module, the output of the differential operational amplifier charges the left ends of C1p2 and C3p2, and the capacitor voltages of C3p2 and C1p2 complete the multiplication and bias function operation in the process of forming a new equilibrium state, and the operation result is stored in the left ends of C2p2 and C3p2, and the result is sampled by the sampling capacitor of the next sampling state as the result of the holding state. The timing of the switches and the n-part control signals of C1n2, C2n2 and C3n2 is consistent with the p-type circuit part.

(5) Redundant addition module

The two-stage structure of the present invention contains a redundant bit. The high 6-bit conversion result of the first-stage multiplication digital-to-analog converter unit MDAC1 and the low 9-bit conversion result of the second-stage multiplication digital-to-analog converter unit MDAC2 are operated through a redundant addition module, and one redundant bit is subtracted to synthesize a 14-bit conversion result as the output data of the entire analog-to-digital converter.

The above description is only the best specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

The contents not described in detail in the specification of the present invention belong to the common knowledge of the professionals in this field.

Claims (10)

1. A 14-bit resolution two-stage cyclic analog-to-digital converter, characterized in that it comprises a first-stage multiplication digital-to-analog converter unit MDAC1 with a 6-bit resolution and a second-stage multiplication digital-to-analog converter unit MDAC2 with a 9-bit resolution, wherein both the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2 are cyclic structures; The first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2 operate in the form of pipeline operation; The first-stage multiplication digital-to-analog converter unit MDAC1 receives the input signal, obtains the upper 6-bit conversion result after 5 cycles of processing, and transmits the upper 6-bit conversion result to the second-stage multiplication digital-to-analog converter unit MDAC2; The second-stage multiplication digital-to-analog converter unit MDAC2 receives the high-order 6-bit conversion result, and after 8 cycles of the same processing as the first-stage multiplication digital-to-analog converter, outputs the low-order 9-bit conversion result; The high 6-bit conversion result and the low 9-bit conversion result are processed, and the 14-bit conversion result synthesized by offset addition is used as the output data of the entire analog-to-digital converter. 2. A 14-bit resolution two-stage cyclic analog-to-digital converter according to claim 1, characterized in that the form of pipeline operation is: the first-stage multiplication digital-to-analog converter unit MDAC1 passes the result to the second-stage multiplication digital-to-analog converter unit MDAC2 after completing the conversion of the upper 6 bits, and while the second stage completes the low 9-bit quantization result, the first stage completes the conversion of the upper 6 bits of the next signal; the conversion time of the first-stage multiplication digital-to-analog converter unit MDAC1 is equal to the conversion time of the second-stage multiplication digital-to-analog converter unit MDAC2 and is equal to the conversion time of the entire analog-to-digital converter. 3. A 14-bit resolution two-stage cyclic analog-to-digital converter according to claim 1, characterized in that each processing process of the first-stage multiplication digital-to-analog converter unit MDAC1 is: sampling the input signal, which is called the sampling state; then performing data processing on the input signal, which is called the holding state, and performing the next sampling operation in the sampling state while working in the holding state; each processing obtains a 1.5-bit result, and after 5 cycles, the high 6-bit conversion result is output after staggered addition. 4. A 14-bit resolution two-stage cyclic analog-to-digital converter according to claim 3, characterized in that the first-stage multiplication digital-to-analog converter unit MDAC1 comprises a 1.5-bit analog-to-digital converter, a 1.5-bit digital-to-analog converter, switches driven by different timings, a capacitor array, and a differential operational amplifier; The two input signals at the input end of the differential operational amplifier are sampled by the capacitor group used for sampling in the capacitor array through the switches driven by the timing sequence, and the sampling results are stored in the capacitor group to complete the sampling state operation; while sampling, the input signal is quantized by 1.5 bits through the 1.5-bit analog-to-digital converter; After the sampling is completed, the circuit enters the holding state. Through switch control, the capacitor is connected to the output of the 1.5-bit digital-to-analog converter module. The output end of the differential operational amplifier charges the capacitor group used for the holding state in the capacitor array. The capacitor group voltage completes the multiplication and bias function operation in the process of forming a new equilibrium state. The operation result is stored in the capacitor group, and the result is sampled by the sampling capacitor of the next sampling state as the result of the holding state. 5. A 14-bit resolution two-stage cyclic analog-to-digital converter according to claim 1, characterized in that each processing process of the second-stage multiplication digital-to-analog converter unit MDAC2 is: sampling the input signal, which is called the sampling state; then performing data processing on the input signal, which is called the holding state, and performing the next sampling operation in the sampling state while working in the holding state; each processing obtains a 1.5-bit result, and after 8 cycles, the lower 9-bit conversion result is output after staggered addition. 6. A 14-bit resolution two-stage cyclic analog-to-digital converter according to claim 1, characterized in that the second-stage multiplication digital-to-analog converter unit MDAC2 comprises a 1.5-bit analog-to-digital converter, a 1.5-bit digital-to-analog converter, switches driven by different timings, a capacitor array, and a differential operational amplifier; The two input signals at the input end of the differential operational amplifier are sampled by the capacitor group used for sampling in the capacitor array through the switches driven by the timing sequence, and the sampling results are stored in the capacitor group to complete the sampling state operation; while sampling the input signal, 1.5-bit quantization is performed through the 1.5-bit analog-to-digital converter; After the sampling is completed, the circuit enters the holding state. Through switch control, the capacitor is connected to the output of the 1.5-bit digital-to-analog converter module. The output end of the differential operational amplifier charges the capacitor group used for the holding state in the capacitor array. The capacitor group voltage completes the multiplication and bias function operation in the process of forming a new equilibrium state. The operation result is stored in the capacitor group, and the result is sampled by the sampling capacitor of the next sampling state as the result of the holding state. 7. A 14-bit resolution two-stage circular analog-to-digital converter according to claim 1, characterized in that it also includes a redundant addition module for performing redundant addition operations on the upper 6-bit conversion result and the lower 9-bit conversion result, subtracting one redundant bit, and synthesizing a 14-bit conversion result. 8. A 14-bit resolution two-stage circular analog-to-digital converter according to any one of claims 1-7, characterized in that it also includes a clock phase high-precision adjustable module to drive the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2, and control the first-stage multiplication digital-to-analog converter unit MDAC2 and the second-stage multiplication digital-to-analog converter unit MDAC2 to work in a pipelined operation mode. 9. A 14-bit resolution two-stage circular analog-to-digital converter according to claim 8, characterized in that: the clock phase high-precision adjustable module is composed of the output signal of the same-phase clock unit, the output signal of the two-phase non-overlapping unit and the AND operation unit, and the clock signal with the same phase and the clock signal with different phases are calculated to obtain different timing clock signals to control the on and off of the switches of the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2. 10. A 14-bit resolution two-stage cyclic analog-to-digital converter according to claim 1, characterized in that the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2 are both modularly designed with the same circuit structure, which is easy to replace.