CN115440811B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A nitride-based semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a gate electrode dielectric layer, source and drain electrodes, a nitride conductive layer, and a gate electrode. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer, and a band gap of the second nitride semiconductor layer is larger than that of the first nitride semiconductor layer. The gate electrode dielectric layer is disposed on the second nitride semiconductor layer. The source electrode and the drain electrode are arranged on the gate electrode dielectric layer, penetrate through the gate electrode dielectric layer and are in contact with the second nitride semiconductor layer. The nitride conductive layer is disposed on the gate electrode dielectric layer and contacts the gate electrode dielectric layer, and the nitride conductive layer is disposed between the source electrode and the drain electrode. The gate electrode is disposed on the nitride conductive layer.

Description

Semiconductor device and manufacturing method thereof

Technical field

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a depletion mode (D-mode) nitride-based semiconductor device having an etching stop layer.

Background technique

In recent years, intensive research on high electron mobility transistors (HEMTs) has become widespread, especially for high-power switching and high-frequency applications. Group III nitride-based HEMTs utilize the heterojunction interface between two materials with different band gaps to form a quantum well-like structure that accommodates a two-dimensional electron gas (2DEG) region to meet the requirements of high power/ Frequency device requirements. In addition to HEMTs, examples of devices with heterostructures further include heterojunction bipolar transistors (HBTs), heterojunction field effect transistors (HFETs), and modulated doped FETs (MODFETs). To meet more design requirements, HEMT devices need to become smaller. Therefore, as HEMT devices are miniaturized, there is a need to maintain the reliability of those HEMT devices.

Contents of the invention

According to one aspect of the present disclosure, a nitrogen-based semiconductor device is provided, which is characterized by including a first nitride semiconductor layer, a second nitride semiconductor layer, a gate electrode dielectric layer, a source electrode and a drain electrode, and a nitride conductive layer. and gate electrode. A second nitride semiconductor layer is disposed on the first nitride semiconductor layer, and the band gap of the second nitride semiconductor layer is larger than the band gap of the first nitride semiconductor layer. A gate electrode dielectric layer is disposed on the second nitride semiconductor layer. The source electrode and the drain electrode are disposed on the gate electrode dielectric layer, pass through the gate electrode dielectric layer and contact the second nitride semiconductor layer. A nitride conductive layer is disposed on the gate electrode dielectric layer and contacts the gate electrode dielectric layer, and the nitride conductive layer is located between the source electrode and the drain electrode. A gate electrode is provided on the nitride conductive layer.

According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes the following steps. forming a second nitride semiconductor layer on the first nitride semiconductor layer; forming a gate electrode dielectric layer on the second nitride semiconductor layer; forming a nitride conductive covering layer on the gate electrode dielectric layer; patterning oxidizing the nitride conductive covering layer to form a nitride conductive layer; forming a deposition layer, and the deposition layer covers the gate electrode dielectric layer and the nitride conductive layer; forming an opening in the deposition layer, to expose a portion of the nitride conductive layer; and form a gate electrode in the opening.

According to an aspect of the present disclosure, a nitrogen-based semiconductor device is provided, which is characterized by including a first nitride semiconductor layer, a second nitride semiconductor layer, a gate electrode dielectric layer, a nitride conductive layer, a deposition layer and a gate electrode . A second nitride semiconductor layer is disposed on the first nitride semiconductor layer, and the band gap of the second nitride semiconductor layer is larger than the band gap of the first nitride semiconductor layer. A gate electrode dielectric layer is disposed on the second nitride semiconductor layer. A nitride conductive layer is disposed on the gate electrode dielectric layer and contacts the gate electrode dielectric layer. A deposition layer is disposed on the gate electrode dielectric layer and at least covers the nitride conductive layer. A gate electrode is disposed on the nitride conductive layer and contacts the nitride conductive layer, and the gate electrode passes through the deposition layer.

Through the above configuration, the nitride conductive layer can serve as an etching stop layer, thereby preventing the gate electrode dielectric layer from being damaged during the stage of forming openings in the deposited layer, and can also help speed up the process rate of forming openings in the deposited layer. Therefore, the formed nitrogen-based semiconductor device having a D-MIS (depletion mode misfet) structure can have high reliability and high yield.

Description of drawings

Aspects of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail below with reference to the drawings, in which:

1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

2A, 2B, 2C, 2D, and 2E illustrate different stages of a method for fabricating a nitrogen-based semiconductor device according to some embodiments of the present disclosure;

3 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure; and

4 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

Detailed ways

Common reference numbers are used throughout the drawings and detailed description to refer to the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Specifies a spatial description for the orientation of the component shown in the associated diagram relative to a component or group of components, or a plane of the component or group of components, such as "above", "above", "below", " "Up", "Left", "Right", "Down", "Top", "Bottom", "Vertical", "Horizontal", "Side", "Higher", "Lower", "Upper" , "above", "below", etc. It is to be understood that the spatial description used herein is for illustrative purposes only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of embodiments of the present disclosure are not Deviation due to such arrangement.

Furthermore, it should be noted that in an actual device, due to device manufacturing conditions, the actual shape of various structures depicted as approximately rectangular may be curved, have rounded edges, have slightly uneven thicknesses, etc. Straight lines and right angles are used only for convenience in representing layers and features.

In the following description, semiconductor devices/die/packages, manufacturing methods thereof, etc. are explained as preferred examples. It will be apparent to those skilled in the art that modifications may be made, including additions and/or substitutions, without departing from the scope and spirit of the disclosure. Specific details may be omitted so as not to obscure the disclosure; however, the disclosure is prepared to enable those skilled in the art to practice the teachings herein without undue experimentation.

1 is a cross-sectional view of a semiconductor device 1A according to some embodiments of the present disclosure. The semiconductor device 1A includes a substrate 10 , nitride-based semiconductor layers 12 and 14 , a gate electrode dielectric layer 16 , electrodes 20 and 22 , a nitride conductive layer 30 , a deposition layer 32 , and a gate electrode 40 .

Substrate 10 may be a semiconductor substrate. Exemplary materials for substrate 10 may include, for example, but not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor-on-insulator (eg, silicon-on-insulator (SOI)), or Other suitable substrate materials. In some embodiments, substrate 10 may include, for example, but not limited to, Group III elements, Group IV elements, Group V elements, or combinations thereof (eg, III-V compounds). In other embodiments, substrate 10 may include, for example, but not limited to, one or more other features, such as doped regions, buried layers, epitaxial (epi) layers, or combinations thereof. In some embodiments, the material of substrate 10 may include a silicon substrate having a <111> orientation.

In some embodiments, substrate 10 may include a buffer layer. The buffer layer may be in contact with the nitride-based semiconductor layer 12 . The buffer layer may be configured to reduce lattice and thermal mismatch between the substrate 10 and the nitride-based semiconductor layer 12, thereby resolving defects caused by mismatch/disparity. The buffer layer may contain III-V compounds. III-V compounds may include, for example, but not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, exemplary materials for the buffer layer may also include, for example, but not limited to, GaN, AIN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, substrate 10 may further include a nucleation layer (not shown). A nucleation layer may be formed beneath the buffer layer. The nucleation layer may be configured to provide a transition to accommodate the mismatch/difference between the substrate 10 and the III-nitride layer of the buffer layer. Exemplary materials for the nucleation layer may include, for example, but not limited to, any of AlN or alloys thereof.

The nitride-based semiconductor layer 12 is disposed on/on/over the buffer layer. The nitride-based semiconductor layer 14 is disposed on/on/over the nitride-based semiconductor layer 12 . Exemplary materials for the nitride-based semiconductor layer 12 may include, for example, but not limited to, nitrides or III-V compounds, such as GaN, AlN, _{InN, InxAlyGa ( 1-xy)} N (where x+y≤1 ), Al _x Ga _(1-x) N (where x≤1). Exemplary materials for nitride-based semiconductor layer 14 may include, for example, but not limited to, nitrides or III-V compounds, such as GaN, AlN, _InN , _{InxAlyGa (1-xy)} N (where x+y≤1 ), Al _x Ga _(1-x) N (where x≤1).

Exemplary materials of nitride-based semiconductor layers 12 and 14 are selected such that the band gap (i.e., band gap) of nitride-based semiconductor layer 14 is larger/higher than the band gap of nitride-based semiconductor layer 12 , which causes its electrons to The affinities are different from each other and a heterojunction is formed between them. For example, when the nitride-based semiconductor layer 12 is an undoped GaN layer having a band gap of about 3.4 eV, the nitride-based semiconductor layer 14 may be selected to be an AlGaN layer having a band gap of about 4.0 eV. Thus, the nitride-based semiconductor layers 12 and 14 may function as channel layers and barrier layers, respectively. A triangular well potential is generated at the bonding interface between the channel layer and the barrier layer, causing electrons to accumulate in the triangular well, thereby creating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Therefore, the semiconductor device 1A may include at least one GaN-based high electron mobility transistor (HEMT).

Gate electrode dielectric layer 16 is provided on nitride semiconductor layer 14 . The gate electrode dielectric layer 16 covers the nitride semiconductor layer 14 . The material of the gate electrode dielectric layer 16 may include, for example, but not limited to, dielectric materials. For example, gate electrode dielectric layer 16 may include SiNx (eg, Si ₃ N ₄ ), SiOx, Si ₃ N ₄ , SiON, SiC, SiBN, SiCBN, oxide, nitride, oxide, plasma enhanced oxidation (PEOX), or a combination thereof.

Electrodes 20 and 22 may be disposed on/on/over gate electrode dielectric layer 16 . Electrodes 20 and 22 may pass through gate electrode dielectric layer 16 to contact nitride semiconductor layer 14 . In some embodiments, electrode 20 may function as a source electrode. In some embodiments, electrode 20 may function as a drain electrode. In some embodiments, electrode 22 may function as a source electrode. In some embodiments, electrode 22 may function as a drain electrode. The role of electrodes 20 and 22 depends on the device design.

In some embodiments, electrodes 20 and 22 may include, for example, but not limited to, metals, alloys, doped semiconductor materials (eg, doped crystalline silicon), compounds such as silicides and nitrides, other conductive materials, or combinations thereof. Exemplary materials for electrodes 20 and 22 may include, for example, but not limited to, Ti, AlSi, TiN, or combinations thereof. Electrodes 20 and 22 may be a single layer, or multiple layers of the same or different compositions. In some embodiments, electrodes 20 and 22 form ohmic contacts with nitride-based semiconductor layer 14 . Ohmic contact may be achieved by applying Ti, Al or other suitable materials to electrodes 20 and 22. In some embodiments, electrodes 20 and 22 are each formed from at least one conformal layer and a conductive filler. The conformal layer may encapsulate the conductive filler. Exemplary materials for the conformal layer may include, for example, but not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. Exemplary materials for conductive fillers may include, for example, but not limited to, AlSi, AlCu, or combinations thereof.

Nitride conductive layer 30 is provided on gate electrode dielectric layer 16 . The nitride conductive layer 30 may cover a portion of the gate electrode dielectric layer 16 . Nitride conductive layer 30 may contact gate electrode dielectric layer 16 . Nitride conductive layer 30 is located between electrodes 20 and 22. Exemplary materials for nitride conductive layer 30 may include metals or metal compounds. The nitride conductive layer 30 may be formed as a single layer, or as multiple layers having the same or different compositions. Exemplary materials of metals or metal compounds may include, for example, but not limited to, TiN or TaN.

Deposition layer 32 is provided on gate electrode dielectric layer 16 . Deposition layer 32 may cover nitride conductive layer 30 and electrodes 20 and 22 . Deposition layer 32 may cover sidewalls of nitride conductive layer 30 . Deposited layer 32 may be a single layer, or multiple layers of the same or different compositions. Deposited layer 32 may function as an interlayer dielectric (ILD) or intermetal dielectric (IMD). Deposited layer 32 may also serve as a protective layer. The material of deposited layer 32 may include, for example, but not limited to, dielectric materials. For example, deposition _{layer 32 may include SiNx (eg, Si3N4), SiOx, Si3N4 , SiON , SiC} , SiBN, SiCBN, oxides, nitrides, oxides, plasma enhanced _oxides (PEOX) or combinations thereof. In some embodiments, gate electrode dielectric layer 16 and deposition layer 32 may be of the same material. In some embodiments, the nitride conductive layer 30 and the deposition layer 32 have different materials. For example, the nitride conductive layer 30 includes titanium nitride, while the deposition layer 32 has a dielectric material that does not include titanium. Since the nitride conductive layer 30 and the deposition layer 32 are made of different materials, they may exhibit different etching rates when facing the same etchant. For example, when an etching process is performed, the deposition layer 32 may be removed due to a chemical reaction with the etchant. However, the nitride conductive layer 30 can hardly react with the same etchant, and therefore acts as an etching process. The etching passivation layer or etching stop layer in the process.

Gate electrode 40 is provided on nitride conductive layer 30 and deposition layer 32 . Gate electrode 40 passes through deposition layer 32 and contacts nitride conductive layer 30 . Gate electrode 40 may be separated from gate electrode dielectric layer 16 by nitride conductive layer 30 . Gate electrode 40 is located between electrodes 20 and 22. Gate electrode 40 may be a back gate. Gate electrode 40 may be formed later than electrodes 20 and 22 . The position of the gate electrode 40 relative to the nitride semiconductor layer 14 is higher than the positions of the electrodes 20 and 22 relative to the nitride semiconductor layer 14 . Furthermore, the position of the top surface of the gate electrode 40 relative to the nitride semiconductor layer 14 is completely higher than the position of the entire electrodes 20 and 22 relative to the nitride semiconductor layer 14 . In addition, as a back gate, the top surface of the gate electrode 40 is also positioned higher than the deposition layer 32 , and at least a part of the gate electrode 40 will cover the deposition layer 32 .

Before performing the manufacturing process of the gate electrode 40 , a portion of the deposition layer 32 may be removed first to form an opening in the deposition layer 32 , which is used to fill the space of the gate electrode 40 . In some embodiments, removing a portion of the deposited layer 32 may be accomplished by an etching process. During the etching process, the nitride conductive layer 30 as an etching stop layer can prevent the gate electrode dielectric layer 16 from being affected by etching. That is, since the nitride conductive layer 30 is used as the etching stop layer, the process of forming the opening in the deposition layer 32 can be more easily controlled.

Specifically, if the nitride conductive layer is not used as the etching stop layer, the process parameters will need to be precisely controlled to avoid damage to the gate electrode dielectric layer. Under the demand for mass production, precise control of process parameters will slow down production speed. In addition, even with precise control, there is still the possibility of damage to the gate electrode dielectric layer. Therefore, using the nitride conductive layer 30 as the etching stop layer can make the process of forming openings in the deposition layer 32 more flexible. For example, the process used may be a parameter with a faster etching speed for the deposition layer 32 .

After the gate electrode 40 is fabricated, the sidewalls of the gate electrode 40 may contact the inner sidewalls of the deposition layer 32 to form an interface. In the exemplary drawing shown in FIG. 1 , the interface is vertical with respect to the nitride semiconductor layer 14 . In addition, since a faster etching speed parameter can be used for forming the openings of the deposition layer 32 , the surface roughness of the inner sidewall of the deposition layer 32 can be relatively large. For example, the surface roughness of the inner sidewall of the deposition layer 32 may be greater than the surface roughness of the top surface of the deposition layer 32 .

On the other hand, the width of the opening formed in the deposition layer 32 will be smaller than the width of the nitride conductive layer 30 , which will make the width of the bottom surface of the gate electrode 40 smaller than the width of the nitride conductive layer 30 . Since the gate electrode 40 serves as a back gate, the width of its top surface can be formed larger than the width of the nitride conductive layer 30 .

Through the structure as shown in FIG. 1 , damage to the gate electrode dielectric layer 16 can be avoided, and the process speed of forming openings in the deposited layer can also be accelerated. Therefore, the formed nitrogen-based semiconductor device having a D-MIS (depletion mode misfet) structure can have high reliability and high yield.

The different stages of the method for manufacturing the nitrogen-based semiconductor device 1A are illustrated in Figures 2A, 2B, 2C, 2D and 2E, as described below. In the following, deposition techniques may include, for example, but not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth or other suitable processes.

Referring to Figure 2A, a substrate 10 is provided. Nitride-based semiconductor layers 12 and 14 may be sequentially formed over substrate 10 using the above-mentioned deposition techniques. Gate electrode dielectric layer 16 may be formed over nitride-based semiconductor layer 14 using the deposition techniques mentioned above. Nitride conductive capping layer 50 may be formed over gate electrode dielectric layer 16 using the deposition techniques mentioned above.

Referring to FIG. 2B , a shielding layer 52 may be formed over the nitride conductive capping layer 50 using the deposition techniques mentioned above. The shielding layer 52 can be used as a shielding layer in subsequent patterning processes and can define the outline or shape of the layer beneath it.

Referring to FIG. 2C , the nitride conductive capping layer 50 may be patterned using the shielding layer 52 to form the nitride conductive layer 30 . The contour or shape of nitride conductive layer 30 may be transferred from shielding layer 52 .

Referring to FIG. 2D , electrodes 20 and 22 may be formed sequentially using deposition techniques and a series of patterning processes. In some embodiments, the patterning process may include photolithography, exposure and development, etching, other suitable processes, or combinations thereof. The deposition layer 32 may be formed using a deposition technology, and the deposition layer 32 covers the gate electrode dielectric layer 16 , the electrodes 20 and 22 , and the nitride conductive layer 30 . Next, a shielding layer 54 may be formed on the deposition layer 32 using a deposition technique. The shielding layer 54 has an opening, and the position of the opening of the shielding layer 54 is aligned with the nitride conductive layer 30 .

Referring to FIG. 2E , the shielding layer 54 may be used to form an opening 322 in the deposition layer 32 to expose a portion of the nitride conductive layer 30 . In some embodiments, forming the opening 322 in the deposited layer 32 includes etching the deposited layer 32 with the nitride conductive layer 30 serving as an etch stop layer. After the opening 322 is formed, the gate electrode can be formed in the opening 322 ; wherein, the step of forming the gate electrode in the opening 322 includes enabling the gate electrode to completely fill the opening 322 . After filling, the gate electrode is made higher than the deposition layer 32 to obtain the structure of FIG. 1 .

3 is a cross-sectional view of semiconductor device 1B according to some embodiments of the present disclosure. The semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1 , except that the nitride conductive layer 30 is replaced by a nitride conductive layer 30B. Nitride conductive layer 30B has grooves at its top surface. The grooves in nitride conductive layer 30B may be created during etching of deposited layer 32 . In some embodiments, during etching of the deposition layer 32 , the etchant used not only has a fast etching rate for the deposition layer 32 but also has a slow etching rate for the nitride conductive layer 30B, so that A portion of the nitride conductive layer 30B is also removed during etching, thereby forming grooves. Gate electrode 40 passes through deposition layer 32 and has its bottom located within the groove. Through the grooves, the contact area between the nitride conductive layer 30B and the gate electrode 40 can be increased to meet different electrical requirements. For example, the contact area between the nitride conductive layer 30B and the gate electrode 40 can be adjusted to correspondingly adjust the threshold voltage of the device.

4 is a cross-sectional view of a semiconductor device 1C according to some embodiments of the present disclosure. The semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1 , except that the deposition layer 32 and the gate electrode 40 are replaced by the deposition layer 32C and the gate electrode 40C. The sidewalls of the gate electrode 40C may contact the inner sidewalls of the deposition layer 32C and form an interface. In the exemplary drawing shown in FIG. 4 , the interface is inclined relative to the nitride semiconductor layer 14 . Since faster etching speed parameters can be used to form openings in the deposition layer 32C, the inner sidewall of the deposition layer 32C can be slightly inclined in response to the faster etching speed parameters.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure of the various embodiments and with various modifications as are suited to the particular use contemplated. .

As used herein and not otherwise defined, the terms "substantially," "substantially," "approximately" and "approximately" are used to describe and account for minor variations. When used in connection with an event or situation, the terms may cover situations in which the event or situation clearly occurs as well as situations in which the event or situation approximates the occurrence. For example, when used in conjunction with a numerical value, the term may encompass a variation of less than or equal to ±10% of the stated numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than Or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces located along the same plane within a few microns, for example two surfaces located along the same plane within 40 μm, within 30 μm, within 20 μm, within 10 μm or within 1 μm.

As used herein, the singular terms "a/an" and "the" may include plural references unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass situations where the former component is directly on (e.g., in physical contact with) the latter component, as well as one or The situation where multiple intermediate components are located between the previous component and the following component.

While the disclosure has been described and illustrated with reference to specific embodiments of the disclosure, these descriptions and illustrations are not limiting. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. Illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproductions in this disclosure and actual devices. Furthermore, it is to be understood that actual devices and layers may deviate from the rectangular layer depictions of the drawings and may contain corner surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, and the like. There may be other embodiments of the disclosure not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objectives, spirit and scope of the disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Accordingly, the order and grouping of operations is not limiting unless specifically indicated herein.

Claims (22)

1. A nitrogen-based semiconductor device, characterized by comprising: first nitride semiconductor layer; a second nitride semiconductor layer disposed on the first nitride semiconductor layer, the band gap of the second nitride semiconductor layer being greater than the band gap of the first nitride semiconductor layer; a gate electrode dielectric layer disposed on the second nitride semiconductor layer; Source electrodes and drain electrodes, which are disposed on the gate electrode dielectric layer, pass through the gate electrode dielectric layer and contact the second nitride semiconductor layer; a nitride conductive layer, which is disposed on the gate electrode dielectric layer and contacts the gate electrode dielectric layer, and the nitride conductive layer is located between the source electrode and the drain electrode; A deposition layer, which is disposed on the gate electrode dielectric layer and covers the nitride conductive layer, the source electrode and the drain electrode; the gate electrode dielectric layer and the deposition layer have the same material; as well as A gate electrode is provided on the nitride conductive layer. 2. The nitrogen-based semiconductor device according to claim 1, wherein the gate electrode is positioned closer to the second nitride semiconductor layer than the source electrode and the drain electrode are to the second nitride layer. The position of the semiconductor layer is still high. 3. The nitrogen-based semiconductor device according to claim 1, wherein the width of the bottom surface of the gate electrode is smaller than the width of the nitride conductive layer. 4. The nitrogen-based semiconductor device according to claim 3, wherein the width of the top surface of the gate electrode is greater than the width of the nitride conductive layer. 5. The nitrogen-based semiconductor device according to claim 1, wherein the position of the top surface of the gate electrode relative to the second nitride semiconductor layer is completely higher than that of the source electrode and the drain electrode. The overall position relative to the second nitride semiconductor layer. 6. The nitrogen-based semiconductor device according to claim 1, wherein the gate electrode passes through the deposition layer to contact the nitride conductive layer. 7. The nitrogen-based semiconductor device according to claim 6, wherein at least a portion of the gate electrode covers the deposition layer. 8. The nitrogen-based semiconductor device according to claim 6, wherein the sidewalls of the gate electrode are in contact with the deposition layer and form an interface. 9. The nitrogen-based semiconductor device according to claim 8, wherein the interface is vertical with respect to the second nitride semiconductor layer. 10. The nitrogen-based semiconductor device according to claim 8, wherein the interface is inclined relative to the second nitride semiconductor layer. 11. The nitrogen-based semiconductor device according to claim 1, wherein the nitride conductive layer includes titanium nitride. 12. The nitrogen-based semiconductor device according to claim 1, wherein the nitride conductive layer has grooves at a top surface thereof. 13. The nitrogen-based semiconductor device according to claim 12, wherein a bottom of the gate electrode is located in the groove. 14. A method of manufacturing a nitrogen-based semiconductor device, comprising: forming a second nitride semiconductor layer on the first nitride semiconductor layer; forming a gate electrode dielectric layer on the second nitride semiconductor layer; forming a nitride conductive covering layer on the gate electrode dielectric layer; Patterning the nitride conductive capping layer to form a nitride conductive layer; A deposition layer is formed, and the deposition layer covers the gate electrode dielectric layer and the nitride conductive layer; the gate electrode dielectric layer and the deposition layer have the same material; forming an opening in the deposited layer to expose a portion of the nitride conductive layer; and A gate electrode is formed in the opening. 15. The manufacturing method according to claim 14, wherein the step of forming the opening in the deposited layer includes performing etching on the deposited layer, and the nitride conductive layer serves as an etching stop layer . 16. The manufacturing method according to claim 14, wherein the step of forming the gate electrode in the opening includes completely filling the opening with the gate electrode, and the gate electrode is higher than the gate electrode. Describe the sedimentary layer. 17. The manufacturing method of claim 14, wherein the nitride conductive layer includes titanium nitride. 18. A nitrogen-based semiconductor device, characterized by comprising: first nitride semiconductor layer; a second nitride semiconductor layer disposed on the first nitride semiconductor layer, the band gap of the second nitride semiconductor layer being greater than the band gap of the first nitride semiconductor layer; a gate electrode dielectric layer disposed on the second nitride semiconductor layer; a nitride conductive layer, which is disposed on the gate electrode dielectric layer and contacts the gate electrode dielectric layer; a deposition layer disposed on the gate electrode dielectric layer and covering at least the nitride conductive layer; the gate electrode dielectric layer and the deposition layer have the same material; and A gate electrode is disposed on the nitride conductive layer and contacts the nitride conductive layer, and the gate electrode passes through the deposition layer. 19. The nitrogen-based semiconductor device according to claim 18, wherein at least a portion of the gate electrode covers the deposition layer. 20. The nitrogen-based semiconductor device according to claim 18, wherein the sidewalls of the gate electrode are in contact with the deposition layer and form an interface. 21. The nitrogen-based semiconductor device according to claim 20, wherein the interface is vertical with respect to the second nitride semiconductor layer. 22. The nitrogen-based semiconductor device according to claim 20, wherein the interface is inclined relative to the second nitride semiconductor layer.