CN115440703A - Semiconductor structure and preparation method thereof - Google Patents

Abstract

The application provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductor storage, and is used for solving the technical problem of low arrangement density of storage units of a magnetic random access memory. The semiconductor structure comprises a substrate, a plurality of memory cells and a common source end; each storage unit comprises an active column, a magnetic tunnel junction and a control switch electrically connected with the magnetic tunnel junction, wherein the active column is vertically arranged on the substrate; the control switch comprises a source electrode, a vertical surrounding grid electrode and a drain electrode which are sequentially arranged on the active column along the extension direction of the active column; the drain electrode is electrically connected with the magnetic tunnel junction, and the source electrode is positioned on one side of the vertical surrounding grid electrode facing the substrate; the common source end is formed on the substrate, and the common source end is arranged on the outer peripheral wall of the bottom end of each active column in a surrounding mode and is electrically connected with each active column. In the embodiment of the application, the source electrode of each storage unit is connected to the common source end, so that the reserved process manufacturing space of two adjacent source lines can be eliminated, and the arrangement density of the storage units is further improved.

Description

Semiconductor structure and preparation method thereof

Technical Field

The present disclosure relates to the field of semiconductor memory technologies, and in particular, to a semiconductor structure and a method for fabricating the same.

Background

A magnetic Random Access Memory (mram) is a nonvolatile mram, and has the advantages of high-speed read and write capabilities, high integration level, and the like, so that the mram is widely used.

The magnetic random access memory comprises a plurality of memory cells, each memory cell comprises a magnetic tunnel junction and a control switch for controlling writing and reading of data, the magnetic tunnel junction generally comprises a free layer, a barrier layer and a reference layer which are sequentially arranged, the control switch comprises a source electrode, a grid electrode and a drain electrode, the free layer is connected with a selection bit line corresponding to the memory cell, the reference layer is connected with the drain electrode, the grid electrode is connected with a word line corresponding to the memory cell, and the source electrode is connected with a source line corresponding to the memory cell.

However, in the above magnetic random access memory, the layout space occupied by the source line corresponding to each memory cell is large, which causes the arrangement density of the memory cells to be reduced, and affects the storage performance of the magnetic random access memory.

Disclosure of Invention

In view of the foregoing problems, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which can improve the arrangement density of memory cells and improve the storage performance of a magnetic random access memory.

A first aspect of an embodiment of the present application provides a semiconductor structure including a substrate, a plurality of memory cells, and a common source; each storage unit comprises an active column, a magnetic tunnel junction and a control switch electrically connected with the magnetic tunnel junction, wherein the active column is vertically arranged on the substrate; the control switch comprises a source electrode, a vertical surrounding grid electrode and a drain electrode which are sequentially arranged on the active column along the extension direction of the active column; wherein the drain is electrically connected to the magnetic tunnel junction and the source is located on a side of the vertical surrounding gate facing the substrate; the common source end is formed on the substrate, and the common source end is arranged on the outer peripheral wall of the bottom end of each active column in a surrounding mode and is electrically connected with each active column.

The semiconductor structure provided by the embodiment of the application has at least the following advantages:

the semiconductor structure provided by the embodiment of the application can be a magnetic random access memory, and the storage unit of the semiconductor structure comprises a drain electrode, a vertical surrounding gate electrode and a source electrode which are sequentially arranged on an active column, wherein the drain electrode is connected with a magnetic tunnel junction of the magnetic random access memory, and the source electrode of each storage unit is respectively connected with a common source end positioned on a substrate.

Compared with the scheme that in the related art, each memory cell is provided with a source line connected with the source electrode of the memory cell, and a larger process manufacturing space is formed between the source lines of two adjacent memory cells, the source lines connected with the source electrodes of the memory cells in the magnetic random access memory provided by the embodiment of the application do not need to be selected in a distinguishing manner, and a plurality of source lines can be integrated at a common source end, namely the source electrode of each memory cell is connected to the common source end. By the arrangement, the reserved process manufacturing space of two adjacent source lines can be eliminated, and the arrangement density of the storage units is improved.

In some embodiments, the common source terminal is configured as a common conductive bump formed within the substrate; the common conductive block is electrically connected to a source of each of the memory cells.

In some embodiments, an ohmic contact layer is disposed on a contact surface between the common conductive bump and the substrate. By the arrangement, the transmission resistance between the common conductive block and the active column can be reduced.

In some embodiments, the common conductive block comprises a conductive core and a barrier layer; the barrier layer is disposed between the conductive core and the ohmic contact layer.

In some embodiments, the semiconductor structure comprises a plurality of the active pillars; the active columns are arranged on the substrate in an array mode, and an accommodating space is formed between two adjacent rows or two adjacent columns of the active columns; the public conducting block comprises a plurality of strip-shaped sub-conducting blocks, each sub-conducting block is arranged in the containing space respectively, and the sub-conducting blocks are electrically connected together.

In some embodiments, the semiconductor structure further comprises a select bit line; the magnetic tunnel junction includes a free layer, a barrier layer, and a reference layer disposed in sequence, wherein the reference layer is electrically connected to the drain, and the free layer is electrically connected to the select bit line. In this way, the selected bit line is connected to the magnetic tunnel junction of the memory cell, and reading or storing of the stored data can be realized by the selected bit line and the control switch.

In some embodiments, the semiconductor structure further comprises a word line; the memory units are arranged on the substrate in an array mode, and the vertical surrounding gates located in the same row or the same column are connected to one word line in common. By such arrangement, the vertical surrounding grid can be formed in the process of forming the word line, namely the word line directly forms the vertical surrounding grid, and the manufacturing process can be simplified.

In some embodiments, the substrate includes a storage region and a peripheral region; the memory units are arranged in the memory area, the peripheral area is provided with a control circuit and a conductive plug, and the control circuit is electrically connected with the common power supply end through the conductive plug.

A second aspect of the embodiments of the present application provides a method for manufacturing a semiconductor structure, including the following steps:

providing a substrate;

synchronously forming a plurality of first trenches, second trenches and active pillars arranged in an array in the substrate, wherein the active pillars are surrounded by the first trenches and the second trenches;

forming a protective layer on the surfaces of the first groove and the second groove;

etching the bottom of the protective layer and a part of the substrate opposite to the bottom of the protective layer to form a first filling groove;

and forming a common source end in the first filling groove.

The advantages of the method for fabricating a semiconductor structure provided by the second aspect of the embodiment of the present invention and the semiconductor structure formed by the method for fabricating the semiconductor structure are described in the foregoing, and are not described again here.

In some embodiments, before the step of forming a common source terminal in the first filling groove, the method further includes: and forming an ohmic contact layer on the surface of the first filling groove.

In some embodiments, the step of forming an ohmic contact layer on the surface of the first filled trench includes:

depositing a metal material into the first filling groove to form a first conductive block;

fire-treating the first conductive block to form an ohmic contact layer on the surface of the first conductive block contacted with the substrate;

and etching a part of the first conductive block which does not participate in forming the ohmic contact layer by using the first groove and the second groove as etching channels, and exposing the ohmic contact layer.

In some embodiments, one of cobalt, palladium, and titanium metal is deposited into the first filling trench to form a first conductive block.

In some embodiments, the step of forming a common source terminal in the first filled trench comprises:

sequentially forming a barrier layer and a conductive core in the first groove and the second groove;

and etching to remove part of the barrier layer and the conductive core, wherein part of the barrier layer and the conductive core in the first filling groove form the common source end.

In some embodiments, the step of sequentially forming a barrier layer and a conductive core within the first trench and the second trench comprises:

and sequentially depositing titanium nitride and metal tungsten by using the first groove and the second groove as deposition channels to form the barrier layer and the conductive core.

In some embodiments, the step of forming a common source terminal in the first filled trench further comprises:

and forming an insulating layer in the first groove and the second groove, wherein the insulating layer covers the common source end.

In some embodiments, further comprising:

etching and removing the insulating layer and the protective layer in the first groove and the second groove to expose the active column;

forming a source electrode, a vertical surrounding grid electrode and a drain electrode on the active column, wherein the source electrode is positioned on one side of the vertical surrounding grid electrode facing the common source end along the direction of the active column, and the drain electrode is positioned on one side of the vertical surrounding grid electrode deviating from the common source end;

and forming a word line in the first groove, wherein the word line is connected with each vertical surrounding gate.

In some embodiments, further comprising:

forming a magnetic tunnel junction on the active pillar, wherein the magnetic tunnel junction is positioned on one side of the drain electrode, which is far away from the vertical surrounding gate;

and forming a bit line in the second groove, wherein the bit line is electrically connected with the active column.

In addition to the technical problems solved by the embodiments of the present disclosure, the technical features constituting the technical solutions, and the advantages brought by the technical features of the technical solutions, other technical problems solved by the semiconductor structure and the method for manufacturing the same provided by the embodiments of the present disclosure, other technical features included in the technical solutions, and advantages brought by the technical features will be further described in detail in the detailed description.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of an overall structure of a magnetic random access memory according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of an arrangement of active pillars on a substrate according to an embodiment of the present application;

fig. 3 is a schematic diagram of an arrangement of a common source terminal on a substrate according to an embodiment of the present application;

fig. 4 is a first flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 5 is a second flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 6 to 11 are schematic structural diagrams corresponding to steps of a method for manufacturing a semiconductor structure according to an embodiment of the present application;

fig. 12 is a schematic flow chart illustrating a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 13 to 16 are schematic structural diagrams corresponding to steps of a method for manufacturing a semiconductor structure according to another embodiment of the present application.

Description of reference numerals:

10-a substrate;

101-a first trench; 102-a protective layer; 103-a first filled trench; 104-a first conductive block;

20-a common conductive block;

21-a conductive core;

22-a barrier layer;

30-an active column;

40-a control switch;

41-source electrode; 42-vertical surrounding gate; 43-a drain electrode;

50-a magnetic tunnel junction;

51-free layer; 52-barrier layer; 53-reference layer;

60-select bit line;

70-word line;

80-ohmic contact layer;

90-an insulating layer;

100-magnetic random access memory;

110-peripheral circuitry; 120-conductive plug.

Detailed Description

As described in the background art, the conventional magnetic random access memory has the problem that the memory cell arrangement density is low, which affects the memory performance of the magnetic random access memory. The inventor finds that the reason for such a problem is that the magnetic random access memory includes source lines corresponding to the memory cells, the source lines are formed in a substrate of the magnetic random access memory, and a large process manufacturing space needs to be reserved between two adjacent source lines, so that the layout space occupied by the source lines in each memory cell is large, and the arrangement density of the memory cells is reduced.

In view of the foregoing technical problems, an embodiment of the present application provides a semiconductor structure and a method for manufacturing the same, where the semiconductor structure may be a magnetic random access memory, and a storage unit of the semiconductor structure includes a drain, a vertical surrounding gate, and a source sequentially disposed on an active pillar, where the drain is connected to a magnetic tunnel junction of the magnetic random access memory, and the sources of the storage units are respectively connected to a common source located on a substrate.

In this way, compared with the scheme that each storage unit is provided with a source line corresponding to the source electrode of the storage unit and a large process manufacturing space is formed between the source lines of two adjacent storage units in the related art, the source lines connected with the source electrodes of the storage units of the magnetic random access memory provided by the embodiment of the application do not need to be selected in a distinguishing manner, and a plurality of source lines can be integrated at a common source end, so that the reserved process manufacturing space of two adjacent source lines can be eliminated, and the arrangement density of the storage units is further improved.

In order to make the aforementioned objects, features and advantages of the embodiments of the present application more comprehensible, embodiments of the present application are described in detail below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a few embodiments of the present application and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.

As shown in fig. 1 to 3, the semiconductor structure provided in the embodiment of the present application may be a magnetic random access memory 100, where the magnetic random access memory 100 includes a substrate 10, a plurality of memory cells, and a common source terminal. For example, the substrate 10 is a silicon substrate, the substrate 10 includes a storage region where a plurality of memory cells are disposed and a peripheral region where a control circuit is disposed, and the control circuit controls reading or writing of data of the memory cells.

Each memory cell includes an active pillar 30, a control switch 40 and a magnetic tunnel junction 50, the active pillar 30 is a semiconductor pillar, i.e., the active pillar 30 may be a silicon pillar, and the active pillar 30 may be made of the same material as the substrate 10 and formed by etching the substrate 10.

The active pillars 30 are arranged in an array on the substrate 10, and each active pillar 30 is vertically disposed on the substrate 10. The active pillars 30 include first and second opposite ends in a direction perpendicular to the substrate 10, and the first ends of the active pillars 30 are disposed adjacent to the substrate 10 and configured for electrical connection with a common source terminal.

A common source terminal is formed on the substrate 10 and in the gap between the active pillars 30, i.e., the common source terminal is formed on the substrate 10, which is enclosed on the outer circumferential sidewall of the first end of each active pillar 30, and the common source terminal is electrically connected with the first ends of the active pillars 30. Further, in this embodiment, a common source terminal is used to connect each of the active pillars 30 and the peripheral circuit 110 to be able to supply a source current or a source signal to each of the control switches 40.

The control switch 40 includes a drain electrode 43, a vertical surrounding gate electrode 42 and a source electrode 41, wherein the drain electrode 43, the vertical surrounding gate electrode 42 and the source electrode 41 are sequentially disposed on the active pillar 30 along the extending direction of the active pillar 30, and the drain electrode 43 is located on a side of the vertical surrounding gate electrode 42 facing away from the common source terminal.

The source 41 is located on one side of the vertical surrounding gate 42 close to the common source terminal, that is, as shown in fig. 1, the drain 43 is located above the vertical surrounding gate 42, the source 41 is located below the vertical surrounding gate 42, and further, the source 41 is located closer to the common source terminal, and the sources 41 of the memory cells are respectively connected to the common source terminal.

Further, the magnetic tunnel junction 50 of the memory cell is disposed on a side of the control switch 40 facing away from the common source terminal, that is, as shown in fig. 1, the magnetic tunnel junction 50 is disposed above the control switch 40, and the magnetic tunnel junction 50 is located above the drain 43 and electrically connected to the drain 43, so that data writing or reading of the magnetic tunnel junction 50 can be controlled by the control switch 40.

Compared with the prior art in which each memory cell is provided with a source line connected to the source 41 thereof, and a larger process manufacturing space exists between the source lines of two adjacent memory cells, the magnetic random access memory 100 provided in the embodiment of the present application does not need to distinguish and select the source lines connected to the sources 41 of the memory cells, and can integrate a plurality of source lines into a common source terminal, that is, the source 41 of each memory cell is connected to the common source terminal. By the arrangement, the reserved process manufacturing space of two adjacent source lines can be eliminated, and the arrangement density of the storage units is improved.

Further, the magnetic random access memory 100 in the embodiment of the present application further includes a selection bit line 60 and a word line 70, where the selection bit line 60 may be a read bit line, and the word line 70 may be a write word line, which is not limited in the embodiment of the present application. The select bit line 60 is connected to the magnetic tunnel junction 50 and the word line 70 is connected to the vertical surrounding gate 42 of each memory cell.

Specifically, the magnetic tunnel junction 50 in the embodiment of the present application includes a free layer 51, a barrier layer 52, and a reference layer 53, which are sequentially disposed, wherein the free layer 51 is located on a side of the barrier layer 52 facing away from the control switch 40, and the reference layer 53 is located on a side of the barrier layer 52 facing toward the control switch 40. The free layer 51 is electrically connected to a select bit line 60, the reference layer 53 is connected to the drain 43 of the control switch 40, the source 41 of the control switch 40 is electrically connected to a common source, and the word line 70 is connected to the vertical surrounding gate 42 of the control switch 40.

In some embodiments, a plurality of memory cells are arranged in an array on the substrate 10. For example, a plurality of memory cells are arranged on the substrate 10 in a plurality of rows and columns, the vertical surrounding gates 42 in the same row or column may be connected to the same word line 70, i.e., the plurality of vertical surrounding gates 42 in the same row or column are connected together by the word line 70.

For example, the vertical surrounding gates 42 formed over each active pillar 30 may be formed by a word line 70, i.e., a portion of the word line 70 acts as a vertical surrounding gate 42, and a portion of the word line 70 connects adjacent vertical surrounding gates 42 together in series. With this arrangement, the vertical surrounding gate 42 can be formed during the process of forming the word line 70, which simplifies the manufacturing process.

It should be noted that the source 41 and the drain 43 disposed on the active pillar 30 and the vertical surrounding gate 42 form a control switch, and the control switch connects the magnetic tunnel junction with the word line and the bit line to control the write and read paths of the magnetic memory, so as to store data into the magnetic tunnel junction or read data in the magnetic tunnel junction.

On the basis of the above embodiments, the common source terminal provided by the embodiments of the present application may be the common conductive block 20 formed in the substrate 10, and the common conductive block 20 is electrically connected to the source 41 of each memory cell.

Specifically, the active pillars 30 of the plurality of memory cells are arranged in an array on the substrate 10; for example, the substrate 10 has a plurality of active pillars 30 thereon, and the plurality of active pillars 30 are arranged on the substrate 10 in a plurality of rows and a plurality of columns, and a receiving space is formed between two adjacent rows or two columns of active pillars 30.

Accordingly, the common conductive block 20 in the embodiment of the present application may include a plurality of sub conductive blocks connected together; the plurality of sub-conductive blocks can be respectively arranged in the accommodating spaces. For example, one sub-conductive block is disposed between two adjacent rows of the active pillars 30, and the sub-conductive block is attached to and in contact with the outer peripheral wall of the first end of the row of the active pillars 30, i.e., the sub-conductive block is electrically connected to the active pillars 30.

In some embodiments, the contact surface of the common conductive bump 20 and the substrate 10 forms an ohmic contact layer 80 to reduce the transfer resistance between the active pillars 30 and the common conductive bump 20. The ohmic contact layer 80 is a metal silicide layer, which may be formed on the contact surface between molybdenum and the silicon substrate 10 by annealing or the like, and is located on the silicon substrate 10.

The common conductive bump 20 is made of a material different from that of the ohmic contact layer 80. The common conductive block 20 in the embodiment of the present application includes a conductive core 21 and a barrier layer 22, the conductive core 21 is made of metal tungsten, the barrier layer 22 is a titanium nitride layer formed on a surface of the metal tungsten, and the barrier layer 22 is located between the metal tungsten and the ohmic contact layer 80. With this arrangement, the barrier layer 22 is disposed between the conductive core 21 and the ohmic contact layer 80, and the barrier layer 22 can prevent the metal tungsten from diffusing into the substrate 10, thereby preventing the substrate 10 from being contaminated by tungsten.

In the embodiment of the present application, each memory cell and the common source terminal are located in a storage area, and in order to implement electrical connection among a control circuit, each memory cell, the common source terminal, the word line 70, and the bit line in the peripheral area, the semiconductor structure provided in the embodiment of the present application further includes a plurality of conductive plugs 120, a part of the conductive plugs 120 is disposed in the peripheral area, one end of the conductive plug 120 is electrically connected to the peripheral circuit 110, and the other end of the conductive plug 120 is connected to the common source terminal; the conductive plugs 120 are used to connect the word lines 70 and the peripheral circuits 110, and the conductive plugs 120 are used to connect the bit lines and the magnetic tunnel junctions 50.

As shown in fig. 4 and 5, a method for manufacturing a semiconductor structure provided by an embodiment of the present application, which is used for manufacturing a common source terminal formed on a substrate 10, includes the following steps:

step S100: a substrate 10 is provided, the substrate 10 may be a silicon substrate, and the substrate 10 includes a memory region for arranging memory cells and a peripheral region for arranging a control circuit.

Step S200: synchronously forming a plurality of first grooves 101, second grooves and active columns 30 which are arranged in an array in the substrate 10, wherein each active column 30 is surrounded by the first grooves 101 and the second grooves; this structure is shown in fig. 2 and 6.

Specifically, the top of the substrate 10 hasbase:Sub>A mask havingbase:Sub>A grid-shaped opening, the substrate 10 is etched along the thickness direction of the substrate 10 to formbase:Sub>A plurality of first trenches 101,base:Sub>A plurality of second trenches, andbase:Sub>A plurality of active pillars 30 on the substrate 10, the plurality of first trenches 101 and the plurality of second trenches are arranged in an array on the substrate 10, wherein the extending direction of the first trenches 101 is the same as thebase:Sub>A-base:Sub>A direction, and the first trenches 101 are used for forming word lines, so the first trenches can also be referred to as word line trenches.

The extending direction of the second groove is vertical to the extending direction of the first groove, and the second groove is used for forming a bit line subsequently, so that the second groove is also called a bit line groove; the plurality of first trenches 101 and the plurality of second trenches are arranged crosswise, and the plurality of active pillars 30 are arranged in an array on the substrate 10.

It should be noted that, while the substrate 10 is etched to form the first trench 101 and the second trench, a plurality of active pillars 30 are formed, and each active pillar 30 is surrounded by the first trench 101 and the second trench.

Further, the depths of the first trench 101 and the second trench may be the same, and the depths of the first trench 101 and the second trench may be 1600A, and structures corresponding to the steps of the manufacturing method provided by the embodiment of the present application are formed, and the description is given by taking structural changes in the first trench as an example.

Step S300: a protective layer 102 is formed on the surfaces of the first trench 101 and the second trench, and the structure is shown in fig. 7.

Specifically, an oxide is deposited on the inner surfaces of the first trench 101 and the second trench to form the protective layer 102, using the first trench 101 and the second trench as deposition channels. The protective layer 102 covers the sidewalls and the bottom walls of the first trench 101 and the second trench, and the protective layer 102 is used for preventing the active pillars 30 from being etched when the bottoms of the first trench 101 and the second trench are subsequently etched.

Step S400: the bottom of the protective layer 102 and the portion of the substrate 10 opposite to the bottom of the protective layer 102 are etched to form a first filled trench 103, which is shown in fig. 8.

Specifically, after the protective layer 102 is formed on the inner surfaces of the first trench 101 and the second trench, the protective layer 102 at the bottom of the first trench 101 and the second trench may be etched to form an etching opening, so as to expose a portion of the substrate 10 opposite to the etching opening.

The etching opening of the first trench 101 and the etching opening of the second trench are used as channels, dry etching is performed on the substrate 10 to form first filling grooves 103 around the active pillars 30, the depth of the first filling grooves 103 relative to the etching openings may be 8nm, and two adjacent first filling grooves 103 are not through.

Step S600: a common source terminal is formed in the first filled trench 103 and the structure is shown in fig. 11.

Specifically, step S600 includes step S610: after the first filled trench 103 is formed, the barrier layer 22 and the conductive core 21 are sequentially formed in the first trench 101 and the second trench.

For example, after forming the first filling trench 103, titanium nitride is deposited into the first trench 101 and the second trench to form the barrier layer 22 by using the first trench 101 and the second trench as deposition channels, and the barrier layer 22 is formed on the surface of the protection layer 102, and the barrier layer 22 encloses a filling cavity in each trench, as shown in fig. 9.

The deposition of metal tungsten into the first trench 101 and the second trench is continued to fill the filling cavity with metal tungsten, so that the barrier layer 22 and the conductive core 21 are formed in the first trench 101 and the second trench, and the structure is shown in fig. 10. It should be noted that the tops of the conductive core 21 and the barrier layer 22 may be further mechanically polished to be flush with the protective layer 102 at the second end of the active pillar 30.

Step S600 further includes step S620: part of the barrier layer 22 and the conductive core 21 are removed by etching, and part of the barrier layer 22 and the conductive core 21 in the first filled trench 103 form a common source terminal, and the structure is shown in fig. 11.

Specifically, after forming the barrier layer 22 and the conductive core 21 in the first trench 101 and the second trench, the barrier layer 22 and the conductive core 21 may be etched along the extending direction of the active pillar 30 to remove a portion of the barrier layer 22 and a portion of the conductive core 21, so as to expose the protective layer 102 on the surfaces of the first trench 101 and the second trench; the barrier layer 22 and the conductive core 21, which partially remain in the first filled trench 103, form a common conductive block 20, i.e. a common source terminal.

Compared with the scheme that in the related magnetic memory in the prior art, each memory cell is provided with a source line connected with the source electrode of the memory cell, and a large process manufacturing space is formed between the source lines of two adjacent memory cells, the source lines connected with the source electrodes of the memory cells of the semiconductor structure manufactured by the manufacturing method of the semiconductor structure provided by the embodiment of the application do not need to be selected in a distinguishing mode, and a plurality of source lines can be integrated at a common source end, namely the source electrode 41 of each memory cell is connected to the common source end respectively. By the arrangement, the reserved process manufacturing space of two adjacent source lines can be eliminated, and the arrangement density of the storage units is improved.

As shown in fig. 12, the embodiment of the present application further includes a step S500 of forming an ohmic contact layer 80 on the surface of the first filled trench 103 before performing the step S600 of forming the common source terminal in the first filled trench 103.

For example, a metal silicide is formed on the surface of the first filled trench 103, and the metal silicide can reduce the transmission resistance between the common source terminal and the active pillars 30, which are formed in the first filled trench 103, so that the metal silicide is the ohmic contact layer 80.

Specifically, step S500 includes step S510 of depositing a metal material into the first filling groove 103 to form a first conductive block 104, which is shown in fig. 13. For example, based on the etching channel for forming the first filling groove 103 in the step S400, which is the deposition channel of the step S510, in other words, after the first filling groove 103 is formed, one of cobalt, palladium and titanium is deposited into the first filling groove 103, and the metal material fills the entire first filling groove 103 to form the first conductive block 104, and the first conductive block 104 is in contact with the surface of the first filling groove 103.

Step S500 includes a step S520 of annealing the first conductive bump 104 to form an ohmic contact layer 80 on a surface of the first conductive bump 104 contacting the substrate 10, as shown in fig. 14.

Specifically, after the first conductive block 104 is formed in the first filling groove 103, the first conductive block 104 is subjected to a fire treatment, and under a high-temperature environment, a metal silicide layer is formed on a surface of the first conductive block 104, where a metal material is in contact with the silicon substrate, and the conductivity of the metal silicide is between that of the first conductive block 104 and the silicon substrate 10, so that compared with the case where the first conductive block 104 is directly in contact with the silicon substrate 10, the metal silicide layer can reduce the transmission resistance between the active pillar 30 and the first conductive block 104, thereby improving the storage and reading efficiency of the magnetic memory.

Step S500 includes a step S530 of etching and removing a portion of the first conductive bump 104 not participating in forming the ohmic contact layer 80 by using the first trench 101 and the second trench as an etching channel, and exposing the ohmic contact layer 80, wherein the ohmic contact layer 80 forms a receiving groove, and the structure is as shown in fig. 15.

Specifically, after the ohmic contact layer 80 is formed on the surface of the first filling groove 103, the first trench 101 and the second trench may be used as etching channels, and a portion of the first conductive bump 104 not participating in forming the ohmic contact layer 80 is etched and removed, and only the ohmic contact layer 80 is remained. This allows the ohmic contact layer 80 to remain in the first filled trench 103, and the ohmic contact layer 80 forms a receiving trench for receiving a subsequently formed common source.

A common source terminal is formed in the receiving slot, the common source terminal includes a barrier layer 22 and a conductive core 21 located in the receiving slot, and the barrier layer 22 is located between the conductive core 21 and the ohmic contact layer 80. This step can refer to the step S600, and the structure formed thereby is shown in fig. 3, which is not described herein again.

On the basis of the second and third embodiments, after the step of forming the common source terminal in the first filled trench 103, the method for manufacturing a semiconductor structure according to the embodiment of the present application further includes: an insulating layer 90 is formed in the first trench 101 and the second trench, and the insulating layer 90 covers the common source terminal, and this structure is shown in fig. 16.

Specifically, after forming the common source terminal, an insulating material may be deposited in the first trench 101 and the second trench to form the insulating layer 90, and the insulating layer 90 fills the first trench 101 and the second trench and covers the common source terminal. The insulating material may be silicon nitride, for example.

Further, after the insulating layer 90 is formed in the first trench 101 and the second trench, the method for manufacturing a semiconductor structure according to the embodiment of the present application further includes:

the insulating layer 90 and the protective layer 102 in the first trench 101 and the second trench are etched to remove, so as to expose a portion of the active pillars 30.

Specifically, the insulating layer 90 and the protective layer 102 in the first trench 101 and the second trench are partially etched and removed along the extending direction of the active pillar 30, so that a part of the active pillar 30 is exposed in the first trench 101 and the second trench, and the remaining part of the insulating layer 90 and the protective layer 102 are located above the common source end, so that the common source end is not in contact with a source electrode, a drain electrode and the like which are subsequently formed on the active pillar 30, and the common source end is electrically connected with the source electrode, the drain electrode and the like through the active pillar 30.

Referring to fig. 1, after a portion of the active pillar 30 is exposed in the first trench 101 and the second trench, a portion of the active pillar 30 may be doped to form a source 41 by using the first trench 101 and the second trench as a doping channel, and the source 41 is disposed near the common source.

After the source 41 is formed on the active pillar 30, a gate dielectric layer and a gate electrode surrounding the gate dielectric layer are sequentially deposited on a portion of the peripheral surface of the active pillar 30 using the first trench 101 and the second trench as deposition channels, so as to form a vertical surrounding gate electrode on the active pillar 30. It should be noted that the gate structure located at the periphery of the gate dielectric layer may be formed together with the gate in the process of forming the word line, that is, the word line 70 is formed in the first trench 101, and the word line 70 is connected to each vertical surrounding gate 42.

After the vertical surrounding gate 42 is formed on the active pillar 30, or after the word line 70 is formed in the first trench 101, the active pillar 30 may be doped by using the first trench 101 and the second trench, so as to form the drain 43 on the active pillar 30, and the drain 43 is located on a side of the vertical surrounding gate 42 away from the common source terminal.

It should be noted that, in the embodiment of the present invention, the source 41 and the drain 43 formed on the active pillar 30 may be formed by doping a part of the substrate 10, forming a source region at a certain thickness position of the substrate 10, and forming a drain region above the source region, that is, the substrate 10 provided in step S100 is a doped substrate, and further etching the substrate 10 in step S200 to simultaneously form the first trench 101, the second trench, and the active pillar 30, where the active pillar 30 formed at this time has the source 41 and the drain 43, and the drain 43 is located above the source 41, which is not limited in the embodiment of the present invention.

On the basis of the above embodiments, after forming the source 41, the drain 43 and the vertical surrounding gate 42 on the active pillar 30, the method for manufacturing a semiconductor structure according to the embodiment of the present application further includes: a magnetic tunnel junction 50 is formed over the active pillar 30 and the magnetic tunnel junction 50 is located on a side of the drain 43 facing away from the vertical surrounding gate 42.

Specifically, after the drain electrode 43 is formed on the active pillars 30, the first trench 101 and the second trench may be used as a deposition channel, and the magnetic tunnel junction 50 is formed on the active pillars 30. The magnetic tunnel junction 50 includes a free layer 51, a barrier layer 52, and a reference layer 53 sequentially disposed from top to bottom along the extension direction of the active pillar 30, wherein the reference layer 53 is electrically connected to the drain electrode 43 of the active pillar 30.

For example, the magnetic tunnel junction 50 is generally cylindrical and is formed over the drain 43. The free layer 51 and the reference layer 53 of the magnetic tunnel junction 50 are made of ferromagnetic material; such as Fe, feCo, feCoB. The barrier layer 52 is more commonly made of MgO. In the embodiment of the present application, a ferromagnetic material, mgO, and a ferromagnetic material may be sequentially deposited on the active pillar 30 to form each layer of the thin film structure of the magnetic tunnel junction 50, and then the above layers of the thin film structure are processed into the magnetic tunnel junction 50 by photolithography and etching.

The method for manufacturing a semiconductor structure according to the embodiment of the present application, after forming the magnetic tunnel junction 50 on the active pillar 30, further includes: a bit line is formed in the second trench and electrically connected to the active pillars 30, that is, a bit line is formed in the second trench, the extending direction of the bit line is the same as the extending direction of the second trench, and the bit line is electrically connected to each active pillar 30 located in the extending direction, which is not described herein again.

In the present specification, each embodiment or implementation mode is described in a progressive manner, and the emphasis of each embodiment is on the difference from other embodiments, and the same and similar parts between the embodiments may be referred to each other.

In the description of the present specification, references to "one embodiment", "some embodiments", "an illustrative embodiment", "an example", "a specific example", or "some examples" and the like mean that a specific feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims (17)

1. A semiconductor structure is characterized by comprising a substrate, a plurality of memory cells and a common source end;

each storage unit comprises an active column, a magnetic tunnel junction and a control switch electrically connected with the magnetic tunnel junction, wherein the active column is vertically arranged on the substrate;

the control switch comprises a source electrode, a vertical surrounding grid electrode and a drain electrode which are sequentially arranged on the active column along the extension direction of the active column; wherein the drain is electrically connected to the magnetic tunnel junction and the source is located on a side of the vertical surrounding gate facing the substrate;

the common source end is formed on the substrate, and the common source end is arranged on the outer peripheral wall of the bottom end of each active column in a surrounding mode and is electrically connected with each active column.

2. The semiconductor structure of claim 1, wherein the common source terminal is configured as a common conductive block formed within the substrate;

the common conductive block is electrically connected to the source of each of the memory cells.

3. The semiconductor structure of claim 2, wherein an ohmic contact layer is disposed on a contact surface between the common conductive bump and the substrate.

4. The semiconductor structure of claim 3, wherein the common conductive block comprises a conductive core and a barrier layer;

the barrier layer is disposed between the conductive core and the ohmic contact layer.

5. The semiconductor structure of any one of claims 2 to 4, wherein the semiconductor structure comprises a plurality of the active pillars;

the active columns are arranged on the substrate in an array mode, and an accommodating space is formed between two adjacent rows or two adjacent columns of the active columns;

the public conducting block comprises a plurality of strip-shaped sub-conducting blocks, each sub-conducting block is arranged in the containing space respectively, and the sub-conducting blocks are electrically connected together.

6. The semiconductor structure of claim 1, further comprising a select bit line;

the magnetic tunnel junction includes a free layer, a barrier layer, and a reference layer disposed in sequence, wherein the reference layer is electrically connected to the drain, and the free layer is electrically connected to the select bit line.

7. The semiconductor structure of claim 6, further comprising a word line;

the memory units are arranged on the substrate in an array, and the vertical surrounding gates positioned on the same row or the same column are commonly connected to one word line.

8. The semiconductor structure of claim 1, wherein the substrate comprises a storage region and a peripheral region;

the memory units are arranged in the memory area, the peripheral area is provided with a control circuit and a conductive plug, and the control circuit is electrically connected with the common power supply end through the conductive plug.

9. A method for fabricating a semiconductor structure, comprising:

providing a substrate;

synchronously forming a plurality of first grooves, second grooves and active columns which are arranged in an array in the substrate, wherein each active column is surrounded by the first grooves and the second grooves;

forming a protective layer on the surfaces of the first groove and the second groove;

etching the bottom of the protective layer and a part of the substrate opposite to the bottom of the protective layer to form a first filling groove;

and forming a common source end in the first filling groove.

10. The method of claim 9, further comprising, before the step of forming a common source terminal in the first filled trench:

and forming an ohmic contact layer on the surface of the first filling groove.

11. The method of claim 10, wherein the step of forming an ohmic contact layer on the surface of the first filled trench comprises:

depositing a metal material into the first filling groove to form a first conductive block;

fire-treating the first conductive block to form an ohmic contact layer on the surface of the first conductive block contacted with the substrate;

and etching and removing part of the first conductive block which does not participate in forming the ohmic contact layer by using the first groove and the second groove as etching channels, and exposing the ohmic contact layer.

12. The method of claim 11, wherein one of cobalt, palladium and titanium is deposited into the first trench to form a first conductive bump.

13. The method of claim 11, wherein forming a common source terminal in the first filled trench comprises:

sequentially forming a barrier layer and a conductive core in the first groove and the second groove;

and etching to remove part of the barrier layer and the conductive core, wherein part of the barrier layer and the conductive core which are positioned in the first filling groove form the common source end.

14. The method of claim 13, wherein the step of sequentially forming a barrier layer and a conductive core in the first trench and the second trench comprises:

and sequentially depositing titanium nitride and metal tungsten by using the first groove and the second groove as deposition channels to form the barrier layer and the conductive core.

15. The method of fabricating a semiconductor structure according to any of claims 9 to 14, further comprising, after the step of forming a common source terminal in the first filled trench:

and forming an insulating layer in the first groove and the second groove, wherein the insulating layer covers the common source end.

16. The method of claim 15, further comprising:

etching and removing the insulating layer and the protective layer in the first groove and the second groove to expose part of the active column;

forming a source electrode, a vertical surrounding grid electrode and a drain electrode on the active column, wherein the source electrode is positioned on one side of the vertical surrounding grid electrode facing the common source end along the direction of the active column, and the drain electrode is positioned on one side of the vertical surrounding grid electrode deviating from the common source end;

and forming a word line in the first groove, wherein the word line is connected with each vertical surrounding gate.

17. The method of claim 16, further comprising:

forming a magnetic tunnel junction on the active pillar, wherein the magnetic tunnel junction is positioned on one side of the drain electrode, which is far away from the vertical surrounding gate;

and forming a bit line in the second groove, wherein the bit line is electrically connected with the active column.

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