CN115422876A - High-Level Synthesis Process Layout Method - Google Patents

Abstract

The invention provides a high-level comprehensive process layout method, which comprises the following steps: obtaining a circuit description of a target circuit, and constructing and obtaining a control data flow diagram corresponding to the target circuit according to the circuit description; the control data flow graph is a directed graph representing the operation of a target circuit; dividing the control data flow graph through a plane planning algorithm to obtain layout constraint; scheduling the control data flow graph, and binding a scheduling result to obtain register transmission level description; obtaining a target netlist according to the transfer level description of the register by the layout constraint, and determining the flow layout of the target circuit according to the target netlist; the method reduces the congestion situation of the layout and the wiring through high-level synthesis, and can also reduce the delay increase caused by crossing an FPGA block boundary in the wiring process; the method can be widely applied to the technical field of circuit simulation.

Description

High-Level Synthesis Process Layout Method

technical field

The invention relates to the technical field of circuit simulation, in particular to a high-level integrated flow layout method.

Background technique

High-level synthesis (High-level Synthesis, HLS) refers to the process of automatically converting the logical structure described in a high-level language into a circuit model described in a low-level language. HLS tools are efficient and fast, which can reduce the design time of hardware engineers and allow software engineers to complete hardware design.

However, in related technical solutions, a major reason for the quality gap between HLS design and manual design is that it is difficult to accurately estimate the interconnection delay at the HLS level, and it is difficult to obtain a better global physical layout. Especially in Field Programmable Gate Array (Field Programmable Gate Array, FPGA) layout and routing, physical synthesizers often use resources that are relatively close to each other, which brings congestion in layout and routing, increases the overall wiring length, and then reduces the cost of the circuit. throughput. In addition, FPGA resources are arranged in the form of Configurable Logic Blocks (CLBs). The resources of different Blocks may be different. When interconnection across Blocks is ignored, longer wiring and delays are likely to result.

Contents of the invention

In view of this, in order to at least partially solve one of the above-mentioned technical problems or defects, the purpose of the embodiments of the present invention is to provide a high-level integrated process layout method that can effectively reduce routing congestion and delay.

The technical solution of this application provides a high-level comprehensive process layout method, including the following steps:

Obtaining a circuit description of the target circuit, and constructing a control data flow graph corresponding to the target circuit according to the circuit description; the control data flow graph is a directed graph representing the operation of the target circuit;

Segmenting the control data flow graph through a plane planning algorithm to obtain layout constraints;

Scheduling the control data flow graph, and binding the scheduling results to obtain a register transmission level description;

A target netlist is obtained by describing the register transfer level according to the layout constraints, and a flow layout of the target circuit is determined according to the target netlist.

In a feasible embodiment of the solution of the present application, the planar planning algorithm is used to segment the control data flow graph to obtain layout constraints, including:

Obtain the FPGA architecture of the target circuit described in the circuit description;

Compiling according to the function corresponding to the data flow process in the control data flow diagram to obtain the circuit module of the register conversion stage;

Partition the FPGA architecture according to the circuit modules, and determine the cost function of the partition results;

By segmenting and iterating the partition results of the FPGA architecture, it is determined that the cost function is a minimum value or the resource in the partition reaches a critical value of the resource constraint, and the layout constraint is obtained as an output.

In a feasible embodiment of the solution of the present application, the scheduling of the control data flow graph, and binding the scheduling results to obtain a register transmission level description include:

Scheduling the subgraphs of the control dataflow graph;

performing delay balancing on the connection line insertion pipeline between the nodes in the control data flow graph;

Mathematically integrating the scheduling results and the delay-balanced results, and binding the mathematically integrated results with the target circuit to obtain the register transfer level description.

In a feasible embodiment of the solution of the present application, the placement constraints include at least one of timing constraints or physical constraints; the target netlist includes at least one of a synthesis netlist or a place-and-route netlist; Describe the register transfer level according to the layout constraints to obtain a target netlist, and determine the flow layout of the target circuit according to the target netlist, including:

constructing a first input according to the timing constraints and/or the physical constraints;

Constructing according to the register transfer level description to obtain a second input;

Through the FPGA physical synthesizer, the first input and the second input are integrated and processed to output to obtain a comprehensive netlist;

Through the FPGA physical synthesizer, according to the first input and the second input, the layout and routing processing output is obtained to obtain the layout and routing netlist;

The flow layout of the target circuit is determined according to the integrated netlist and the place-and-route netlist.

In a feasible embodiment of the scheme of the present application, the cost function is used to characterize the number of wires of the partition boundary of the FPGA architecture; the cost function is:

Wherein, C is a cost value, v _i and v _j represent nodes in the control data flow graph, i=1,2,3,...n, j=1,2,3,...n, n is a positive integer, E represents the collection of FIFO channels between nodes, e _ij is the connecting line between v _i and v _j , row represents the number of rows, col represents the number of columns, and width represents the data bit width.

In a feasible embodiment of the solution of this application, the expression of the resource constraint is as follows:

Among them, v _d represents the partition space allocated by node v, v _area represents the required resources of the node, r _v represents the set of nodes accommodated by the current partition r, and (r _child ) _area represents the number of resources in each partition.

In a feasible embodiment of the solution of the present application, by performing segmentation iteration on the partition result of the FPGA architecture, it is determined that the cost function is the minimum value or the resource in the partition reaches the critical value of the resource constraint, and the output is obtained The layout constraints include:

Obtaining the first coordinates of the nodes in the control data flow graph before the segmentation iteration, determining the coordinate transformation relationship according to the segmentation method, and transforming the first coordinates to obtain the second coordinates according to the coordinate transformation relationship;

The division manner includes horizontal division or vertical division.

In a feasible embodiment of the scheme of the present application, the expression of the coordinate transformation relationship is as follows:

Among them, v.row represents the row coordinate in the second coordinate, v.col represents the column coordinate in the second coordinate, (v.row) _prev represents the row coordinate in the first coordinate, (v.col) _prev represents the first The column coordinates in the coordinates, v _d indicates the partition space allocated by node v, vertical partition indicates horizontal partition, and horizontal partition indicates vertical partition.

In a feasible embodiment of the solution of the present application, when inserting the connection lines between the nodes in the control data flow graph into the pipeline for delay balance, the delay balance expression is as follows:

e _ij.balance ＝(S _i -S _j -e _ij.lat )

Among them, S _i represents the time step of node v _i , S _j represents the time step of node v _j , S _i -S _j represents the maximum delay between all paths between node v _i and node v _j ; e _ij.lat Indicates the additional delay before inserting into the pipeline; e _ij.balance indicates the balance delay after inserting into the pipeline.

In a feasible embodiment of the solution of the present application, the step of performing delay balancing on the connection line insertion pipeline between nodes in the control data flow graph includes:

Constructing an objective function of area overhead according to the balanced time delay, the objective function is:

Wherein, e _ij.width is the maximum data bit width of the pipeline between node v _i and node v _j .

The advantages and beneficial effects of the present invention will be partially provided in the following description, and other parts can be understood through the specific implementation of the present invention:

The technical solution of this application proposes a full-process layout method based on a high-level comprehensive guidance of FPGA physical layout constraints based on a plane planning algorithm. The method obtains a control data flow graph through the circuit description of the target circuit, and controls the control data flow through the plane planning algorithm. Segment the data flow diagram to obtain the layout constraints; on the basis of the layout constraints, schedule and bind the corresponding resources of the target circuit to obtain the register transmission level description, and further perform comprehensive processing, layout and routing to obtain the netlist of the target circuit; through high-level synthesis Reduce the congestion of layout and routing, and at the same time reduce the delay increase caused by crossing the FPGA block boundary during the routing process.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

Fig. 1 is a flow chart of the steps of the high-level comprehensive process layout method provided in the technical solution of the present application;

Fig. 2 is a schematic diagram of the control data flow diagram in the technical solution of the present application;

Fig. 3 is a schematic diagram of the iterative partitioning process in the technical solution of the present application;

Figure 4(a) is one of the schematic diagrams of the balance delay in the technical solution of the present application;

Figure 4(b) is the second schematic diagram of the balance delay in the technical solution of the present application;

FIG. 5 is a schematic diagram of a FIFO pipeline in the technical solution of the present application.

detailed description

Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention. For the step numbers in the following embodiments, it is only set for the convenience of illustration and description, and the order between the steps is not limited in any way. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art sexual adjustment.

Based on the current related technical solutions, especially in FPGA layout and routing, the physical synthesizer often uses resources that are relatively close, which easily causes layout and routing congestion, increases the overall wiring length, and reduces the throughput of the circuit. In view of the technical defects in the related technical solutions, the technical solution of this application proposes a full-process layout method based on a plane planning algorithm-based high-level synthesis tool to guide FPGA physical layout constraints.

In the first aspect, as shown in Figure 1, the technical solution of the present application provides a high-level comprehensive process layout method; the method includes steps S100-S400:

S100. Obtain a circuit description of the target circuit, and construct a control data flow diagram corresponding to the target circuit according to the circuit description;

Among them, as shown in Figure 2, the control data flow graph is a directed graph representing the operation of the target circuit. The solid line in Figure 2 represents the data dependency, the dotted line represents the control dependency, and the triangle symbol represents the branch operation. The circuit description in the embodiment includes, but is not limited to, the description of signal input, components, and logical operations performed by the components in the target circuit through VHDL language or Verilog language; the target circuit may refer to a hardware circuit in a real scene. Specifically, in the embodiment, the input circuit description is first obtained, and the control data flow graph is constructed. In the embodiment, the control data flow graph (Control Data Flow Graph, CDFG) is a directed graph G=<V, E>, Among them, V represents the set of all nodes in the control data flow graph, and each node in the control data flow graph represents an operation in the target circuit; E represents the set of all directed connection lines in the control data flow graph, and the control data flow graph Each directed edge connecting two nodes in represents a data or control dependency between the two corresponding operations. The control relationship dependency side of the control data flow graph reflects the control dependency of the circuit description, and the data relationship dependency side reflects the data dependency of the circuit description. Based on the nature of the control data flow graph, in the process of constructing the control data flow graph in the embodiment, first, the embodiment uses the front end of the compiler to generate an intermediate code from the high-level language code of the behavior-level description in the circuit description according to the source code; Then, the embodiments map the variables in the circuit description into nodes, map the control and data dependencies into directed edges through the backend of the compiler, and construct the control flow data flow graph.

S200. Segment the control data flow graph by using a plane planning algorithm to obtain layout constraints;

Wherein, the planar programming algorithm in the embodiment can use the cutting plane algorithm to solve the plan; the layout in the embodiment can be defined as a set of physical constraints, which are used to control the placement of the logic in the model. Specifically in the embodiment, first, according to the FPGA architecture corresponding to the target circuit, determine the number of partitions, resources, and maximum utilization of the resources corresponding to the target circuit; then, compile the function corresponding to the data flow process in the control data flow diagram into a register conversion stage The circuit (RegisterTransfer Level, RTL) module is placed in the initial partition; based on the cutting plane algorithm, the current partition is divided into two horizontally or vertically, and the scheme with the smallest cost function is calculated and selected. Based on the obtained scheme, the target is determined Circuits correspond to placement constraints in the FPGA fabric.

In some feasible implementation manners, the step S200 of segmenting the control data flow graph through a plane planning algorithm to obtain layout constraints may include steps S210-S240:

S210. Obtain the FPGA architecture of the target circuit in the circuit description;

S220. Compile according to the function corresponding to the data flow process in the control data flow graph to obtain a circuit module of the register conversion stage;

S230. Partition the FPGA architecture according to the circuit modules, and determine a cost function of the partition result;

S240. By segmenting and iterating the partition result of the FPGA architecture, it is determined that the cost function is a minimum value or the resources in the partition reach the critical value of the resource constraint, and output to obtain the layout constraint;

Specifically, in the embodiment, there are multiple Blocks in the FPGA architecture, and resources of different Blocks may be different. Good layout helps to reduce routing congestion and improve the quality of timing results (QoR) achievable in the design; and in the embodiment, the layout constraints use Pblock instructions to specify resource partitions, and Pblock boundaries allow the use of clock region boundaries To define the size of the pblock, instead of using SLICE, BRAM, DSP, etc. range, helps limit clock skew and helps the overall clock placement of the design. And based on the control data flow graph, the basis for partitioning the HLS design in the embodiment is the data flow programming style, that is, the HLS design is stream-like, and the design structure is described as a directed graph; nodes in the directed graph represent operations that need to be performed The unit of processing, the connection line between the nodes describes the data transmission path; in the directed graph, the adjacent nodes transmit data through the volume line, the node consumes the data for calculation, and outputs the generated data to the input and output sequence as the next input to the computing unit.

Exemplarily, the HLS design in the example adopts a data flow programming model, wherein each function corresponds to a data flow process, each function corresponds to an RTL module, and FIFO is used for communication between modules. Then construct a graph G=<V, E>, where V represents a collection of data streams, and each node represents a function; E represents a collection of FIFO channels between vertices.

S300. Scheduling the control data flow graph, and binding the scheduling results to obtain a register transmission level description;

Specifically, in the embodiment, corresponding scheduling needs to be performed on the subgraphs of the control data flow graph; delay balancing is performed on the control data flow graph; furthermore, in some feasible implementations, step S300 may include steps S310-S330:

S310. Scheduling the subgraphs of the control data flow graph;

S320. Perform delay balancing on connecting lines between nodes in the control data flow graph into the pipeline;

S330. Mathematically integrate the scheduling result and the delay-balanced result, and bind the mathematically integrated result to the target circuit to obtain the register transfer level description.

Specifically, in the embodiment, the subgraph of the control data flow graph is scheduled using the default mode of the high-level synthesis tool; then, the edge cutting of the control data flow graph is inserted into the pipeline, and the delay is balanced; the obtained in steps S310-S320 After the scheduling results are mathematically integrated, the comprehensive scheduling result is obtained; the comprehensive scheduling result is bound to the resources in the FPGA architecture corresponding to the target circuit, and the register transfer level description is obtained.

S400. Describe the register transfer level according to the layout constraints to obtain a target netlist, and determine the flow layout of the target circuit according to the target netlist;

Specifically, in the embodiment, according to the layout constraints obtained in step S200 and the register transfer level description obtained in step S300; the resources in the FPGA architecture are integrated and placed and routed to obtain the corresponding target netlist, thereby determining the target The corresponding control flow layout of the circuit.

In some feasible implementation manners, the placement constraints in the embodiments include at least one of timing constraints or physical constraints; the target netlist includes at least one of a synthesis netlist or a place-and-route netlist; and in the embodiments, according to the The layout constraint describes the register transfer level to obtain a target netlist, and the step S400 of determining the flow layout of the target circuit according to the target netlist may include steps S410-S450:

S410. Construct and obtain a first input according to the timing constraint and/or the physical constraint;

S420. Construct and obtain a second input according to the register transfer level description;

S430. Using the FPGA physical synthesizer, integrate the first input and the second input to output an integrated netlist;

S440. Using the FPGA physical synthesizer, perform placement and routing processing and output according to the first input and the second input to obtain a placement and routing netlist;

S450. Determine the flow layout of the target circuit according to the integrated netlist and the place-and-route netlist.

Specifically, in the embodiment, first, the layout constraints obtained in step S200 and the timing constraints and physical constraints obtained by the high-level synthesis tool itself are input as a set of constraints for synthesis implementation, which is the first input; the obtained in step S300 The register transfer level description is the RTL input implemented as synthesis, i.e. the second input; then the embodiment runs the FPGA physical synthesizer, performs synthesis, placement and routing operations, and obtains the netlist after synthesis and the netlist after placement and routing, and according to the obtained netlist The table determines the flow layout of the target circuit.

In an embodiment, in step S230, the FPGA architecture is partitioned according to the circuit modules, and a cost function of the partition result is determined, wherein the physical meaning of the cost function is the sum of the number of wires passing through the partition boundary. Furthermore, the cost function in the embodiment is:

Wherein, C is a cost value, v _i and v _j represent nodes in the control data flow graph, i=1,2,3,...n, j=1,2,3,...n, n is a positive integer, E represents the collection of FIFO channels between nodes, e _ij is the connecting line between v _i and v _j , row represents the number of rows, col represents the number of columns, and width represents the data bit width.

In an embodiment, step S240 performs segmentation iteration on the partition result of the FPGA architecture, determines that the cost function is the minimum value or the resource in the partition reaches the critical value of the resource constraint, and outputs the layout constraint; wherein, the resource The expression of the constraint is as follows:

Among them, v _d represents the partition space allocated by node v, v _area represents the required resources of the node, r _v represents the set of nodes accommodated by the current partition r, and (r _child ) _area represents the number of resources in each partition.

In an embodiment, the partitioning result of the FPGA architecture is divided and iterated, the cost function is determined to be the minimum value or the resource in the partition reaches the critical value of the resource constraint, and the step S240 of obtaining the layout constraint is output, which may include Steps S241-S242:

S241. Obtain the first coordinates of the nodes in the control data flow graph before the segmentation iteration, determine a coordinate transformation relationship according to the segmentation method, and transform the first coordinates to obtain second coordinates according to the coordinate transformation relationship;

S242. The division method includes horizontal division or vertical division;

Specifically in the embodiment, as shown in Figure 3, the process of partitioning can be regarded as iteratively dividing into two parts again and again, until the cost function is minimum or no longer meets the constraint conditions, and finally the pipeline FIFO is added; the first step is to All functions are mapped into RTL modules and placed in one partition, called the initialization partition, where the dependency relationship is 1 points to 2, 3, 4, 2, 3, 4 points to 5, and the resource occupation of 2 and 3 is relatively small; the second The first step is to divide into two vertically, 123 is placed at the top, and 45 is placed at the bottom; the third step is to divide each partition into two horizontally, and the result is that 2 and 3 are at the upper left, and 1 is at the upper right. 4 is at the bottom left and 5 is at the bottom right; the last step is to add FIFO pipelines for the traces that cross the block boundary to ensure the throughput of the circuit design.

Further, the expression of the coordinate transformation relation in the embodiment is as follows:

Among them, v.row represents the row coordinate in the second coordinate, v.col represents the column coordinate in the second coordinate, (v.row) _prev represents the row coordinate in the first coordinate, (v.col) _prev represents the first The column coordinates in the coordinates, v _d indicates the partition space allocated by node v, vertical partition indicates horizontal partition, and horizontal partition indicates vertical partition.

In an embodiment, step S320 performs delay balancing on the connection line insertion pipeline between nodes in the control data flow graph.

Specifically, in the embodiment, given a partitioned and pipelined data flow graph G<V, E>, each vertex v∈V represents a function in the data flow design, and each edge e∈E represents the relationship between functions The FIFO channel, the width e.width represents the bit width of the edge, the delay e.lat represents the additional delay inserted in the previous pipeline step, and the balance delay e.balance represents the balance delay in the current step. For each edge e∈E, the total delay of each path can be expressed as:

Among them, {p ₁ ,p ₂ } represent a pair of reconverged paths. Further, for each edge (connection line) e in delay balance, it can be considered that S _i ≥ S _j +e _ij.lat , and the additional balance delay can be expressed as:

e _ij.balance ＝(S _i -S _j -e _ij.lat )

Among them, S _i represents the time step of node v _i , S _j represents the time step of node v _j , S _i -S _j represents the maximum delay between all paths between node v _i and node v _j ; e _ij.lat Represents the extra delay inserted in the longest path between vertices v _i and v _j by the previous pipeline step; e _ij.balance represents the extra delay inserted by the current pipeline step in the longest path between vertices v _i and v _j .

Exemplarily, as shown in Figure 4, Figure 4 (a) represents the cut-set1 cut set in the balance delay process; Figure 4 (b) represents the cut-set2 and cut-set3 cut sets in the balance delay process, Among them, edges e13, e37, and e27 are pipelined according to the floor plan partition, and then each edge carries 1 unit of insertion delay. Also assume that e14 has a bit width of 2 and all other sides are 1. In the delay balancing step, the optimal solution is to add 2 units of delay to each edge of e47, e57, and e67, and add 1 unit of delay to each of e12. Note that e27 and e37 can exist in the same cut-set.

As shown in Figure 5, after the partitions are divided, they are connected based on FIFO, so that they can be pipelined. With the FIFO, the matching interface signals can be directly scheduled without affecting the function, and the parallelism of the circuit function is provided.

In some feasible implementation manners, the step S320 of delay balancing the connection line insertion pipeline between the nodes in the control data flow graph may also include step S321:

S321. Construct an objective function of area cost according to the balanced time delay;

Specifically, in an embodiment, the optimization goal of balanced delay is to minimize the total area overhead, and take into account the bit width overhead of each edge. The objective function in the embodiment is:

Among them, e _ij.width is the maximum data bit width of the pipeline between node v _i and node v _j

From the above specific implementation process, it can be concluded that the technical solution provided by the present invention has the following advantages or advantages compared with the prior art:

The present invention can be applied in the high-level comprehensive design of medium and large-scale data flow programming models, utilizes the characteristics of high-level comprehensive tools capable of rapid prototyping, and at the same time extends the design process, from high-level language to hardware description language, and then to physical layout. The high-level synthesis tool guides the whole-process design method of physical layout, which can further improve the layout and routing of high-level synthesis design, reduce layout congestion, and ensure the overall throughput of the circuit.

As an example, using the default HLS and the application layout constraints HLS for the RISCV CPU design, it can be clearly determined that the HLS design with the application layout constraints performs partition pipeline processing on the CPU module, FFT module, USB1 module, and USB2 module with the highest resource occupancy. At the same time, they are distributed in adjacent but different blocks. In the case of meeting the timing constraints, the timing margin is basically unchanged, but the congestion situation is greatly improved, and the running time of physical synthesis is also reduced.

In some alternative implementations, the functions/operations noted in the block diagrams may occur out of the order noted in the operational diagrams. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/operations involved. Furthermore, the embodiments presented and described in the flowcharts of the present invention are provided by way of example in order to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logical flow presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and in which sub-operations described as part of larger operations are performed independently.

Furthermore, although the invention has been described in the context of functional modules, it should be understood that one or more of the functions and/or features may be integrated into a single physical device and/or software module unless stated to the contrary. or one or more functions and/or features may be implemented in separate physical devices or software modules. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary to understand the present invention. Rather, given the attributes, functions and internal relationships of the various functional blocks in the devices disclosed herein, the actual implementation of the blocks will be within the ordinary skill of the engineer. Accordingly, those skilled in the art can implement the present invention set forth in the claims without undue experimentation using ordinary techniques. It is also to be understood that the particular concepts disclosed are illustrative only and are not intended to limit the scope of the invention which is to be determined by the appended claims and their full scope of equivalents.

The logic and/or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium, For use with instruction execution systems, devices, or devices (such as computer-based systems, systems including processors, or other systems that can fetch instructions from instruction execution systems, devices, or devices and execute instructions), or in conjunction with these instruction execution systems, devices or equipment used.

In the description of this specification, descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described, those skilled in the art can understand that various changes, modifications, substitutions and modifications can be made to these embodiments without departing from the principle and spirit of the present invention. The scope of the invention is defined by the claims and their equivalents.

The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above-mentioned embodiments, and those skilled in the art can also make various equivalent deformations or replacements without violating the spirit of the present invention. Equivalent modifications or replacements are all within the scope defined by the claims of the present application.

Claims (10)

1. The high-level comprehensive process layout method is characterized by comprising the following steps of:

obtaining a circuit description of a target circuit, and constructing and obtaining a control data flow diagram corresponding to the target circuit according to the circuit description; the control data flow graph is a directed graph representing the operation of a target circuit;

dividing the control data flow graph through a plane planning algorithm to obtain layout constraint;

scheduling the control data flow graph, and binding a scheduling result to obtain register transmission level description;

and describing the register transmission level according to the layout constraint to obtain a target netlist, and determining the flow layout of the target circuit according to the target netlist.

2. The high-level integrated process layout method of claim 1, wherein the segmenting the control data flow graph by a floor planning algorithm to obtain layout constraints comprises:

acquiring an FPGA framework of the target circuit in the circuit description;

compiling according to a function corresponding to a data flow process in the control data flow graph to obtain a register conversion level circuit module;

partitioning the FPGA framework according to the circuit module, and determining a cost function of a partitioning result;

and performing segmentation iteration on the partition result of the FPGA framework, determining that the cost function is the minimum value or the resource in the partition reaches the critical value of the resource constraint, and outputting to obtain the layout constraint.

3. The high-level integrated process layout method of claim 1, wherein the scheduling the control data flow graph and binding the scheduling result to obtain a register transfer level description comprises:

scheduling subgraphs of the control data flow graph;

inserting connecting lines between nodes in the control data flow graph into a production line for delay balance;

and mathematically integrating the scheduling result and the result after delay balance, and binding the result after mathematical integration with the target circuit to obtain the register transmission level description.

4. The high-level integrated process layout method of claim 1, wherein the layout constraints comprise at least one of timing constraints or physical constraints; the target netlist comprises at least one of a synthesized netlist or a place and route netlist; the obtaining a target netlist by describing the register transfer level according to the layout constraint, and determining the process layout of the target circuit according to the target netlist, includes:

constructing and obtaining a first input according to the time sequence constraint and/or the physical constraint;

constructing according to the register transmission level description to obtain a second input;

integrating, processing and outputting the first input and the second input through an FPGA physical synthesizer to obtain a synthesized netlist;

performing layout and wiring processing output according to the first input and the second input through an FPGA physical synthesizer to obtain a layout and wiring netlist;

and determining the flow layout of the target circuit according to the comprehensive netlist and the layout and routing netlist.

5. The method of high-level synthesis flow layout of claim 2, wherein the cost function is used to characterize the number of wires at the partition boundaries of the FPGA architecture; the cost function is:

wherein C is a cost value, v _i And v _j Characterizing nodes in the control dataflow graph, i =1,2,3, … n, j =1,2,3, … n, n being positive integers, E characterizing a set of FIFO lanes between nodes, E _ij Is v is _i And v _j The connecting line between, row, col, and width represent the number of rows, columns, and data bits.

6. The high-level integrated process layout method of claim 2, wherein the resource constraints are expressed as follows:

wherein v is _d Representing the partition space allocated by node v, v _area Representing the required resources of the node, r _v Represents the set of nodes held by the current partition r, (r) _child ) _area Indicating the number of resources in each partition.

7. The method of claim 2, wherein the determining that the cost function is a minimum value or a threshold value of resource constraints is reached by resources in a partition by performing segmentation iteration on partition results of the FPGA architecture and outputting the layout constraints comprises:

acquiring a first coordinate of a node in the control data flow graph before segmentation iteration, determining a coordinate transformation relation according to a segmentation mode, and transforming the first coordinate to obtain a second coordinate according to the coordinate transformation relation;

the dividing mode comprises horizontal direction dividing or vertical direction dividing.

8. The process layout method of high-level synthesis according to claim 7, wherein the expression of the coordinate transformation relationship is as follows:

wherein v.row represents a row coordinate in the second coordinate, v.col represents a column coordinate in the second coordinate, (v.row) _prev Indicates the line coordinate in the first coordinate, (v _prev Representing column coordinates in a first coordinate, v _d The partition space allocated by the node v is represented, the vertical part represents the horizontal direction division, and the horizontal part represents the vertical direction division.

9. The method of claim 3, wherein the delay balancing is performed for the connection lines between the nodes in the control data flow graph inserted into the pipeline, and the expression of the delay balancing is as follows:

e _ij. balance＝(S _i -S _j -e _ij.lat )

wherein S is _i Representing a node v _i Time step of S _j Representing a node v _j Time step of S _i -S _j Representing a node v _i And node v _j Maximum delay between all paths in between; e.g. of the type _ij.lat Indicating an extra delay that exists before insertion into the pipeline; e.g. of the type _ij.balance Representing the resulting equilibrium delay after insertion into the pipeline.

10. The method of claim 9, wherein the step of balancing delay for the connecting line insertion pipelines between nodes in the control data flow graph comprises:

constructing an objective function of the area overhead according to the balance time delay, wherein the objective function is as follows:

wherein e is _ij.width At node v for the pipeline _i And node v _j The maximum data bit width therebetween.

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