CN115421864A - Universal virtual simulation method for instruction set of PowerPC architecture processor - Google Patents
Universal virtual simulation method for instruction set of PowerPC architecture processor Download PDFInfo
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Abstract
The invention relates to a universal virtual simulation method for an instruction set of a PowerPC architecture processor, and belongs to the field of virtual simulation. The invention designs a general processor simulation framework aiming at 32-bit microprocessor cores e300, e500 and e600 of FreeScale (FreeScale) based on Power Architecture, and simultaneously supports the simulation operation of processors with various architectures. The operating environment of the PowerPC processor embedded processor software is provided, and support is provided for the development of the PowerPC processor embedded processor software. The scheme provided by the invention can realize the instruction set simulation of the PowerPC instruction architecture processor, and has high simulation precision; the invention adopts arrays, linked lists and the like to realize the simulation of the register and the memory, and can complete the simulation of the processor with the PowerPC instruction architecture.
Description
Technical Field
The invention belongs to the field of virtual simulation, and particularly relates to a universal virtual simulation method for an instruction set of a PowerPC architecture processor.
Background
Instruction set emulation is the most important support for processor virtualization technology, allowing software on a particular instruction set to run on another heterogeneous class of instruction sets. Virtualization is implemented at the instruction set level, which is actually to convert binary code on one hardware platform into binary code on another hardware platform, so as to implement compatibility between different instruction sets, and this technology is also called binary translation. Virtualization technology has 2 main ways: interpretive execution, dynamic binary translation.
The interpreter analyzes the source binary codes one by one and decomposes corresponding interpretation routine execution according to the decoding result, namely the type of the instruction. The interpreter routine simulates the execution of the source instruction with equivalent target instruction(s) on a source architecture (including various architectural registers, memory states, etc.) maintained by software, achieving the same execution effect as the source instruction. The working process of the interpreter mainly comprises the steps of fetching instructions, analyzing the instructions, completing the operations required by the instructions, modifying the state of the processor and the like, and the steps are circulated.
The simulator based on interpretation execution maintains an accurate processor data structure in the host, has high simulation precision, can realize accurate registers, memories and pipelines, and can obtain accurate performance indexes such as clock period of each instruction in the pipeline, stack simulation and the like besides the function of a simulation source program.
PowerPC (English: performance Optimized With Enhanced RISC-Performance Computing, sometimes abbreviated PPC) is a Reduced Instruction Set (RISC) architecture Central Processing Unit (CPU), the basic design of which is derived from IBM's POWER (Performance Optimized With Enhanced RISC, 8 th month of IBM Connect, 2007, translated as "Enhanced RISC Performance Optimized") architecture.
The PowerPC processor has a very strong embedded behavior because it has excellent performance, low power consumption, and low heat dissipation. In addition to integrated I/O like serial and ethernet controllers, the embedded processor is very significantly different from a desktop CPU. The PowerPC processor has 32 (32-bit or 64-bit) GPRs (general purpose registers) and various other registers such as a PC (program counter, also known as IAR/instruction address register or NIP/Next instruction pointer), LR (link register), CR (condition register), etc.
Disclosure of Invention
Technical problem to be solved
The invention provides a universal virtual simulation method for an instruction set of a PowerPC (personal computer) architecture processor, which aims to solve the problem of virtual simulation of the instruction set of the PowerPC architecture processor.
(II) technical scheme
In order to solve the above technical problem, the present invention provides a general virtual simulation method for processor instruction sets with a PowerPC architecture, which comprises the following steps:
s1, target file analysis of PowerPC instruction architecture
Opening an executable file compiled by the PowerPC instruction architecture, exe, and acquiring a code segment corresponding to a Program Header;
s2, memory emulation and code loading of PowerPC instruction architecture
Simulating the memory of the PowerPC instruction architecture processor by adopting a linked list structure, recording the memory as PowerPC-VMemory, loading code segments corresponding to Program headers, and simulating the memory read-write operation of the PowerPC instruction architecture;
s3, powerPC instruction architecture register emulation
Simulating the read-write operation of the register through an array simulation register and array operation to realize the simulation of the register;
s4, powerPC instruction architecture instruction description
Each instruction has a unique representation, each instruction is divided into different segments; describing by adopting a mode of segmenting an Instruction, acquiring operation code opcode information of an Instruction Instruction, constructing an Instruction operation code information array PowerPC-InstructionDesp [425], describing 425 instructions of a POWERPC architecture Instruction set architecture, and storing the instructions into the Instruction operation code information array PowerPC-InstructionDesp [425 ];
s5, powerPC instruction architecture fetch instruction
Reading an Instruction from a simulation memory PowerPC-VMemory according to the value of a program counter PC, and acquiring an Instruction PC-Instruction corresponding to the current PC;
s6, powerPC instruction architecture instruction decode
According to Instruction description of a PowerPC Instruction architecture, whether corresponding bits of a PC-Instruction and a PowerPC-Instruction Desp [425] are the same or not is calculated one by one, if the positions corresponding to kth Instruction descriptions in the PC-Instruction and the PowerPC-Instruction Desp [425] are the same, instruction decoding is completed and marked as Instruction _ k;
s7, powerPC instruction architecture instruction translation
Performing function translation on a PowerPC instruction architecture instruction set, designing a function which is operated by a virtual simulation processor and performs operation simulation on each instruction, and ensuring that the memory and the register of a hardware processor and the virtual simulation processor are consistent after each instruction and the function are processed; storing the function pointer into the array of PowerPC-InstructionInterp [425], wherein the storage sequence is consistent with the instruction sequence of the PowerPC-InstructionDesp [425 ];
s8, implementation of Linux system call of PowerPC instruction architecture
Analyzing the system call, carrying out corresponding processing on the system call according to the type of the system call, and carrying out setting operation on a corresponding register;
s9, powerPC instruction set architecture instruction execution
According to the instruction number, carrying out cyclic instruction fetching, decoding and instruction translation, and executing instruction operation according to the function pointer; and continuously simulating until all the instructions are executed and the system call is processed, so that the simulation of the processor instruction set aiming at the PowerPC instruction architecture is realized.
Further, the step S1 specifically includes:
s11, opening an executable file which is compiled by a PowerPC instruction architecture, exe, and reading file information;
s12, reading File Header, section Header and Program Header information in the File information according to the format of the executable File compiled by the PowerPC instruction architecture, and acquiring a code segment corresponding to the Program Header.
Further, the step S2 specifically includes:
s21, simulating the memory of the PowerPC instruction architecture processor by adopting a linked list structure, wherein the size of the linked list structure PowerPC-MemoryPage is 256 words;
s22, recording the PowerPC instruction architecture memory as PowerPC-VMemory; and writing the code segment corresponding to the Program Header acquired in the S1 into a PowerPC-VMemory of a PowerPC instruction architecture chip simulation memory, and maintaining the whole simulation memory structure according to the size of the code segment.
Further, the linked list structure includes: a starting virtual address memorypagebeginnardress, an ending virtual address MemoryPageEndAddress, a memory block MemoryPage, a NEXT memory node pointer NEXT, and a previous memory node pointer PRE.
Further, in step S22, if the code segment is not larger than the size 256 of a MemoryPage, a MemoryPage is created and the code segment is written into the MemoryPage array for pairing; and if the code segment is larger than 256, creating a plurality of MemoryPage, writing the code segment into the corresponding MemoryPage array in sequence, and maintaining the MemoryPage BeginAdddress and the MemoryPage EndAddress information of each node to ensure the correctness of the linked list structure information.
Further, the step S3 specifically includes:
s31, simulating 197 registers in total on chips of PowerPC instruction architectures e300, e500 and e600, and simulating the registers through an array PowerPC-Register simulation Register;
and S32, operating and simulating Register operation of the PowerPC instruction architecture on the elements in the corresponding array by accessing the PowerPC-Register, and realizing the Register simulation of the PowerPC instruction architecture.
Further, the step S4 specifically includes: the structure of the instruction operation code information array PowerPC-InstructionDesp comprises the following steps: name, content number and content, wherein, the name is the instruction name, the content number of instruction segment, the content is used to store the decode information of the opcode instruction.
Further, the step S5 specifically includes:
s51, reading an instruction from the PowerPC-VMemory maintained in the S2 according to the value of the program counter PC;
s52, according to the values of MemoryPageBeginAddreress and MemoryPageEndAddress in the PowerPC-MemoryPage, calculating that the PC belongs to the PowerPC-MemoryPage and is recorded as PowerPC-MemoryPage-i, the address offset is PC-MemoryPageBeginAddreress, the Instruction content is MemoryPage [ PC-MemoryPageBeginAddreress ] corresponding to the PowerPC-MemoryPage-i, and is recorded as PC-Instruction.
Further, the step S7 specifically includes:
s71, performing function translation on the instructions in the PowerPC instruction architecture instruction set, designing a function which is operated by the virtual simulation processor and is used for performing operation simulation on each instruction, and ensuring that the memories and registers of the hardware processor and the virtual simulation processor are kept consistent after each instruction and the function are processed;
s72: translating 425 instructions of a PowerPC instruction architecture, and storing a function pointer into an instruction translation decoding array PowerPC-InstructionInterp [425] array, wherein the storage sequence is consistent with the instruction sequence of a PowerPC-InstructionDesp [425 ];
and S73, acquiring a pointer in the function corresponding to the Instruction according to the Instruction _ k calculated in S6.
Further, the step S9 specifically includes:
s91, constructing a simulation framework of a PowerPC instruction architecture, performing cyclic instruction fetching, decoding and instruction translation according to the number of instructions, and executing instruction operation according to a function pointer;
and S92, continuously simulating until all the instructions are executed and the system call is processed, so that the processor instruction set simulation aiming at the PowerPC instruction architecture is realized.
(III) advantageous effects
The invention provides a universal PowerPC instruction set virtualization simulation method, which provides a virtualization operating environment for embedded processing software, provides a PowerPC instruction set virtualization simulation technical scheme based on interpretation execution, and designs a universal processor simulation frame aiming at 32-bit microprocessor cores e300, e500 and e600 of Power Architecture in Freescale (Freescale), and simultaneously supports the simulation operation of processors with various architectures. The operating environment of the PowerPC processor embedded processor software is provided, and support is provided for the development of the PowerPC processor embedded processor software.
The scheme provided by the invention can realize the instruction set simulation of the PowerPC instruction architecture processor, and has high simulation precision; the invention realizes the simulation of the register and the memory by adopting the array, the linked list and the like, and can finish the simulation of the PowerPC instruction architecture processor.
Drawings
FIG. 1 is a schematic diagram for explaining an implementation technique;
FIG. 2 is a schematic diagram of instruction information.
Detailed Description
In order to make the objects, contents and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
The invention provides a virtualization running environment for embedded processing software, and provides a technical scheme for virtualizing and simulating a processor based on a PowerPC instruction Architecture for interpretation and execution. The operating environment of the PowerPC processor embedded processor software is provided, and support is provided for development of the PowerPC processor embedded processor software.
S1, target file analysis of PowerPC instruction architecture
Opening an executable file compiled by a PowerPC instruction architecture, namely exe, and acquiring a code segment corresponding to a Program Header;
the File format of the PowerPC processor is ELF, and according to File information of the ELF File format, information such as File Header, section Header, program Header and the like in the File information is read to obtain a code segment corresponding to the Program Header;
s2, powerPC instruction architecture memory emulation and code loading
In order to improve the expandability of memory simulation, a linked list structure is adopted to simulate the memory of the processor with the PowerPC instruction architecture, the memory is marked as PowerPC-VMemory, code segments corresponding to Program headers are loaded, and the memory read-write operation of the PowerPC instruction architecture is simulated.
S3, powerPC instruction architecture register emulation
The simulation method is characterized in that 197 registers in total of chips of PowerPC instruction architectures e300, e500 and e600 are simulated, the registers are divided into 32 GPR general registers, 32 FPR floating point processing registers, 51 special registers, 41 e600 special registers and 41 e500 special registers, and the registers are 197 in total.
S4, powerPC instruction architecture instruction description
Each instruction has a unique representation, each instruction is divided into different segments; in order to accurately describe the Instruction structure, the invention adopts a mode of segmenting instructions, obtains the opcode information of Instruction, constructs an Instruction opcode information array PowerPC-Instruction desp [425], describes 425 instructions of the POWERPC architecture Instruction set architecture, and stores the 425 instructions into an Instruction opcode information array PowerPC-Instruction desp [425 ].
S5, powerPC instruction architecture fetch instruction
Reading an Instruction from a simulation memory PowerPC-VMemory according to the value of a Program counter PC (Program Count) to obtain an Instruction PC-Instruction corresponding to the current PC;
s6, powerPC instruction architecture instruction decode
The POWERPC architecture Instruction architecture comprises 425 Instruction sets in total, whether corresponding bit positions of the PC-Instructions and the PowerPC-Instructions Desp [425] are the same or not is calculated one by one according to the Instruction description of the PowerPC Instruction architecture, if the corresponding positions of the kth Instruction descriptions in the PC-Instructions and the PowerPC-Instructions Desp [425] are the same, instruction decoding is completed and recorded as Instructions _ k.
S7, powerPC instruction architecture instruction translation
Performing function translation on a PowerPC instruction architecture instruction set, designing a function which is operated by a virtual simulation processor and performs operation simulation on each instruction, and ensuring that the memory and the register of a hardware processor and the virtual simulation processor are consistent after each instruction and the function are processed; storing the function pointer into the array of PowerPC-InstructionInterp [425], wherein the storage sequence is consistent with the instruction sequence of the PowerPC-InstructionDesp [425 ];
s8, implementation of Linux system call of PowerPC instruction architecture
Analyzing the system call, performing corresponding processing on the system call according to the type of the system call, and performing setting operation on a corresponding register;
s9, powerPC instruction architecture instruction execution
According to the instruction number, carrying out cyclic instruction fetching, decoding and instruction translation, and executing instruction operation according to the function pointer; and continuously simulating until all the instructions are executed and the system call is processed, so that the simulation of the processor instruction set aiming at the PowerPC instruction architecture is realized.
Example 1:
the invention provides a virtual simulation technical scheme of a PowerPC instruction architecture processor based on interpretation and execution, which simulates through an instruction set
S1, target file analysis of PowerPC instruction architecture
S11, opening an executable file which is compiled by a PowerPC instruction architecture, exe, and reading file information;
s12, reading information such as File Header, section Header, program Header and the like in File information according to the format of the executable File compiled by the PowerPC instruction architecture, and acquiring a code segment corresponding to the Program Header;
s2, memory emulation and code loading of PowerPC instruction architecture
S21, in order to improve the expandability of memory simulation, a linked list structure is adopted to simulate the memory of the PowerPC instruction architecture processor, wherein the size of the PowerPC-MemoryPage of the linked list structure is 256 words, and the linked list structure comprises: a starting virtual address memorypagebeginnardress, an ending virtual address MemoryPageEndAddress, a memory block MemoryPage, a NEXT memory node pointer NEXT and a previous memory node pointer PRE;
s22, recording the PowerPC instruction architecture memory as PowerPC-VMemory; writing the code segment corresponding to the Program Header acquired in the step S1 into a PowerPC-VMemory of a PowerPC instruction architecture chip, and maintaining the whole simulation memory structure according to the size of the code segment
If the code section is not larger than 256 (the size of a MemoryPage), creating a MemoryPage and writing the code section to the MemoryPage array for use;
and if the code segment is larger than 256 (the size of one MemoryPage), creating a plurality of MemoryPages, writing the code segment into a corresponding MemoryPage array in sequence, and maintaining the information of the MemoryPageBeginAdddress, the MemoryPageEndAddress and the like of each node to ensure the correctness of the linked list structure information.
S3, powerPC instruction architecture register emulation
S31, simulating 197 registers in total on chips of PowerPC instruction architectures e300, e500 and e600, wherein the registers are divided into 32 GPR general registers, 32 FPR floating point processing registers, 51 special registers, 41 e600 special registers and 41 e500 special registers, and the registers are 197 in total, simulating the registers by simulating the read-write operation of the registers through array PowerPC-Register, and realizing the simulation of the registers, wherein the main simulation results are as follows:
and S32, operating and simulating the Register operation of the PowerPC instruction architecture on the elements in the corresponding array by accessing the PowerPC-Register, and realizing the Register simulation of the PowerPC instruction architecture.
S4, powerPC instruction architecture instruction description
S41, all 425 instructions of processors of PowerPC instruction architectures e300, e500 and e600, wherein each instruction has a unique representation and is divided into different sections; in order to accurately describe the Instruction structure, the invention describes the Instruction by adopting a mode of segmenting the Instruction, obtains the operation code opcode information of the Instruction, and designs the structure of an Instruction operation code information array PowerPC-Instruction Desp, which comprises the following steps: name, contentNumber, and content. The structure is described as follows:
wherein, name is the instruction name, the number of the segments of the contentNumber instruction, and the content is used for storing the decode information of the opcode instruction.
The instruction structure is described using the addx instruction as an example, where the ABS instruction information is shown in FIG. 2 (from the instruction set reference Manual)
Name is "addx"; the instruction opcode (bit with fixed and unchangeable bit in the instruction) is divided into two sections, the first section is bit0-bit5 bit, the second section is bit22-bit30 bit, the contentNumber is '2'; content [21] stores opcode information, and content [21] is "0, 5, 0x1f, 22, 30, 0x10A". Three numbers represent a segment, (2, 11, 0x 05) represent bit0-bit5 bits, with a value of 0x1f; (22, 30, 0x 10A) represents bit22-bit30 bits, the value is 0x10A.
S42, constructing an instruction operation code information array PowerPC-InstructionDesp [425], describing 425 instructions of the POWERPC architecture instruction set architecture, and storing the instructions into the instruction operation code information array PowerPC-InstructionDesp [425 ].
S5, reading instruction of PowerPC instruction architecture
S51, reading an instruction from the PowerPC-VMemory maintained in S2 according to the value of a Program counter PC (Program Count);
s52, according to the values of MemoryPageBeginAddreress and MemoryPageEndAddress in the PowerPC-MemoryPage, calculating that the PC belongs to the PowerPC-MemoryPage and is recorded as PowerPC-MemoryPage-i, the address offset is PC-MemoryPageBeginAddreress, the Instruction content is MemoryPage [ PC-MemoryPageBeginAddreress ] corresponding to the PowerPC-MemoryPage-i, and is recorded as PC-Instruction.
S6, powerPC instruction architecture instruction decoding
S61, according to the PC-Instruction read in S5, whether the corresponding bits of the PC-Instruction and the corresponding bits of the PowerPC-Instruction Desp [425] are the same or not are calculated one by one, and if the corresponding positions of the kth Instruction descriptions in the PC-Instruction and the corresponding positions of the Kth Instruction descriptions in the PowerPC-Instruction Desp [425] are the same, the Instruction is marked as Instruction _ k.
S7, powerPC instruction architecture instruction translation
S71, performing function translation on the instructions in the PowerPC instruction architecture instruction set, designing a function which is operated by the virtual simulation processor and is used for performing operation simulation on each instruction, and ensuring that the memories and registers of the hardware processor and the virtual simulation processor are kept consistent after each instruction and the function are processed;
s72: translating 425 instructions of a PowerPC instruction architecture, and storing a function pointer into an instruction translation decoding array PowerPC-InstructionInterp [425] array, wherein the storage sequence is consistent with the instruction sequence of a PowerPC-InstructionDesp [425 ];
s73, according to the Instruction _ k calculated in S6, a pointer in a function corresponding to the Instruction can be obtained;
s8, implementation of Linux system call of PowerPC instruction architecture
S81, defining 318 types of system calls of the Linux system, and marking the names of the system calls according to the sequence of the Linux system calls, wherein the definition is as follows:
#define SYSCALL_restart_system 0
……
#define SYSCALL_dup2 63
……
#define SYSCALL_inotify_init1 318
and S82, analyzing the system call, carrying out corresponding processing on the system call according to the type of the system call, and carrying out setting operation on a corresponding register.
S9, powerPC instruction set architecture instruction execution
S91, constructing a simulation framework of a PowerPC instruction architecture, performing cyclic instruction fetching, decoding and instruction translation according to the number of instructions, and executing instruction operation according to a function pointer;
and S92, continuously simulating until all instructions are executed, processing system call, and realizing processor instruction set simulation aiming at the PowerPC instruction architecture.
The scheme provided by the invention can realize the instruction set simulation of the PowerPC instruction architecture processor, and has high simulation precision; the invention realizes the simulation of the register and the memory by adopting the array, the linked list and the like, and can finish the simulation of the PowerPC instruction architecture processor.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A virtualization emulation method for a general PowerPC architecture processor instruction set is characterized by comprising the following steps:
s1, target file analysis of PowerPC instruction architecture
Opening an executable file compiled by the PowerPC instruction architecture, exe, and acquiring a code segment corresponding to a Program Header;
s2, memory emulation and code loading of PowerPC instruction architecture
Simulating the memory of the PowerPC instruction architecture processor by adopting a linked list structure, recording the memory as PowerPC-VMemory, loading code segments corresponding to Program headers, and simulating the memory read-write operation of the PowerPC instruction architecture;
s3, powerPC instruction architecture register emulation
Simulating the read-write operation of the register through an array simulation register and array operation to realize the simulation of the register;
s4, powerPC instruction architecture instruction description
Each instruction has a unique representation, each instruction is divided into different segments; describing by adopting a mode of segmenting an Instruction, acquiring operation code opcode information of an Instruction Instruction, constructing an Instruction operation code information array PowerPC-InstructionDesp [425], describing 425 instructions of a POWERPC architecture Instruction set architecture, and storing the instructions into the Instruction operation code information array PowerPC-InstructionDesp [425 ];
s5, powerPC instruction architecture fetch instruction
Reading an Instruction from a simulation memory PowerPC-VMemory according to the value of a program counter PC, and acquiring an Instruction PC-Instruction corresponding to the current PC;
s6, powerPC instruction architecture instruction decoding
Calculating whether corresponding bit positions of the PC-Instructions and the PowerPC-Instructions Desp [425] are the same one by one according to Instruction descriptions of a PowerPC Instruction architecture, and finishing Instruction decoding and marking as Instructions _ k if corresponding positions of the Kth Instruction descriptions in the PC-Instructions and the PowerPC-Instructions Desp [425] are the same;
s7, powerPC instruction architecture instruction translation
Performing function translation on a PowerPC instruction architecture instruction set, designing a function which is operated by a virtual simulation processor and performs operation simulation on each instruction, and ensuring that the memory and the register of a hardware processor and the virtual simulation processor are consistent after each instruction and the function are processed; storing the function pointer into the array of PowerPC-InstructionInterp [425], wherein the storage sequence is consistent with the instruction sequence of PowerPC-InstructionDesp [425 ];
s8, implementation of Linux system call of PowerPC instruction architecture
Analyzing the system call, carrying out corresponding processing on the system call according to the type of the system call, and carrying out setting operation on a corresponding register;
s9, powerPC instruction architecture instruction execution
According to the instruction number, carrying out cyclic instruction fetching, decoding and instruction translation, and executing instruction operation according to the function pointer; and continuously simulating until all the instructions are executed and the system call is processed, so that the simulation of the processor instruction set aiming at the PowerPC instruction architecture is realized.
2. The method of claim 1, wherein the step S1 specifically comprises:
s11, opening an executable file which is compiled by a PowerPC instruction architecture, exe, and reading file information;
s12, reading File Header, section Header and Program Header information in the File information according to the format of the executable File compiled by the PowerPC instruction architecture, and acquiring a code segment corresponding to the Program Header.
3. The method of claim 2, wherein the step S2 comprises:
s21, simulating the memory of the PowerPC instruction architecture processor by adopting a linked list structure, wherein the size of the PowerPC-MemoryPage of the linked list structure is 256 words;
s22, recording the PowerPC instruction architecture memory as PowerPC-VMemory; and writing the code segment corresponding to the Program Header acquired in the step S1 into a PowerPC-VMemory of a PowerPC instruction architecture chip, and maintaining the whole simulation memory structure according to the size of the code segment.
4. The generalized PowerPC architecture processor instruction set virtualization emulation method of claim 3, wherein the linked list structure comprises: a starting virtual address memorypagebeginnardress, an ending virtual address MemoryPageEndAddress, a memory block MemoryPage, a NEXT memory node pointer NEXT, and a previous memory node pointer PRE.
5. The universal PowerPC architecture processor instruction set virtualization emulation method of claim 1 wherein in step S22, if a code section is not larger than a MemoryPage size of 256, a MemoryPage is created and written to the MemoryPage array for use; and if the code segment is larger than 256, creating a plurality of MemoryPage, writing the code segment into the corresponding MemoryPage array in sequence, and maintaining the MemoryPage BeginAdddress and the MemoryPage EndAddress information of each node to ensure the correctness of the linked list structure information.
6. The method for virtualizing and emulating the general purpose PowerPC architecture processor instruction set according to any of claims 2 to 5, wherein the step S3 specifically comprises:
s31, simulating 197 registers in total of chips e300, e500 and e600 of the PowerPC instruction architecture, and simulating the registers through an array PowerPC-Register simulation Register;
and S32, operating and simulating the Register operation of the PowerPC instruction architecture on the elements in the corresponding array by accessing the PowerPC-Register, and realizing the Register simulation of the PowerPC instruction architecture.
7. The method of claim 6, wherein the step S4 comprises: the structure of the instruction operation code information array PowerPC-InstructionDesp comprises the following steps: name, content number and content, wherein, the name is an instruction name, the number of the content number instruction segments, and the content is used for storing the decode information of the opcode instruction.
8. The method of claim 7, wherein the step S5 comprises:
s51, reading an instruction from the PowerPC-VMemory maintained in S2 according to the value of the program counter PC;
s52, according to the values of the MemoryPageBeginAddreress and the MemoryPageEndAddress in the PowerPC-MemoryPage, the PC is calculated to belong to the PowerPC-MemoryPage and is recorded as PowerPC-MemoryPage-i, the address offset is PC-MemoryPageBeginAddreress, the Instruction content is MemoryPage [ PC-MemoryPageBeginAddreress ] corresponding to the PowerPC-MemoryPage-i and is recorded as PC-Instruction.
9. The method of claim 1, wherein step S7 specifically includes:
s71, performing function translation on the instructions in the PowerPC instruction architecture instruction set, designing a function which is operated by the virtual simulation processor and is used for performing operation simulation on each instruction, and ensuring that the memories and registers of the hardware processor and the virtual simulation processor are kept consistent after each instruction and the function are processed;
s72: translating 425 instructions of a PowerPC instruction architecture, and storing a function pointer into an instruction translation decoding array PowerPC-InstructionInterp [425] array, wherein the storage sequence is consistent with the instruction sequence of a PowerPC-InstructionDesp [425 ];
and S73, acquiring a pointer in the function corresponding to the Instruction according to the Instruction _ k calculated in S6.
10. The method of claim 9, wherein step S9 comprises:
s91, constructing a simulation framework of a PowerPC instruction architecture, performing cyclic instruction fetching, decoding and instruction translation according to the number of instructions, and executing instruction operation according to a function pointer;
and S92, continuously simulating until all instructions are executed, processing system call, and realizing processor instruction set simulation aiming at the PowerPC instruction architecture.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6212614B1 (en) * | 1998-01-05 | 2001-04-03 | Trw Inc. | Legacy MIL-STD-1750A software emulator address translation using power PC memory management hardware |
| US20050076186A1 (en) * | 2003-10-03 | 2005-04-07 | Microsoft Corporation | Systems and methods for improving the x86 architecture for processor virtualization, and software systems and methods for utilizing the improvements |
| US20060026563A1 (en) * | 2004-07-27 | 2006-02-02 | Texas Instruments Incorporated | Method and system for managing virtual memory |
| US20080222384A1 (en) * | 2007-02-12 | 2008-09-11 | Hua Yong Wang | Apparatus and method for executing rapid memory management unit emulation and full-system simulator |
| CN111026504A (en) * | 2019-12-06 | 2020-04-17 | 海光信息技术有限公司 | Processing method and device for configuring instruction for acquiring processor information in virtual machine, CPU chip, system on chip and computer |
| WO2021249193A1 (en) * | 2020-06-12 | 2021-12-16 | 华为技术有限公司 | Method and apparatus for processing exception or interrupt under heterogeneous instruction set architecture |
-
2022
- 2022-09-14 CN CN202211114604.XA patent/CN115421864B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6212614B1 (en) * | 1998-01-05 | 2001-04-03 | Trw Inc. | Legacy MIL-STD-1750A software emulator address translation using power PC memory management hardware |
| US20050076186A1 (en) * | 2003-10-03 | 2005-04-07 | Microsoft Corporation | Systems and methods for improving the x86 architecture for processor virtualization, and software systems and methods for utilizing the improvements |
| US20060026563A1 (en) * | 2004-07-27 | 2006-02-02 | Texas Instruments Incorporated | Method and system for managing virtual memory |
| US20080222384A1 (en) * | 2007-02-12 | 2008-09-11 | Hua Yong Wang | Apparatus and method for executing rapid memory management unit emulation and full-system simulator |
| CN111026504A (en) * | 2019-12-06 | 2020-04-17 | 海光信息技术有限公司 | Processing method and device for configuring instruction for acquiring processor information in virtual machine, CPU chip, system on chip and computer |
| WO2021249193A1 (en) * | 2020-06-12 | 2021-12-16 | 华为技术有限公司 | Method and apparatus for processing exception or interrupt under heterogeneous instruction set architecture |
Non-Patent Citations (1)
| Title |
|---|
| 邸强: "基于TTA可配置处理器的指令集仿真器及集成开发环境的设计" * |
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