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CN115410929B - 倒装芯片与底层芯片的堆叠结构的制备方法 - Google Patents

倒装芯片与底层芯片的堆叠结构的制备方法 Download PDF

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CN115410929B
CN115410929B CN202211225874.8A CN202211225874A CN115410929B CN 115410929 B CN115410929 B CN 115410929B CN 202211225874 A CN202211225874 A CN 202211225874A CN 115410929 B CN115410929 B CN 115410929B
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CN115410929A (zh
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殷炯
林叶
张韬
何国强
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Jiangsu Huachuang Micro System Co ltd
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Abstract

本发明公开了一种倒装芯片与底层芯片的堆叠结构的制备方法，包括以下步骤：S1、采用框架材料制备基板层；S2、在基板层的基岛的正面基岛上装底层芯片；S3、底层芯片与基板层焊线进行电气连接；S4、安装金属片；S5、倒装芯片装在相邻两个金属片上；S6、塑封料包覆所述倒装芯片与底层芯片的堆叠结构。优点，本发明方法，满足倒装芯片尺寸与底层芯片尺寸相差不大，甚至倒装芯片尺寸比底层芯片尺寸更小的情况，且结构为倒装芯片在上，底层芯片在下的堆叠结构；满足此类产品封装需求，且能提高封装利用率降低封装成本。

Description

倒装芯片与底层芯片的堆叠结构的制备方法
技术领域
本发明涉及倒装芯片与底层芯片的堆叠结构的制备方法。
背景技术
倒装芯片在上，通过连接基板两端的铜柱实现与底层芯片大堆叠，只能满足倒装芯片比底层芯片大很多的情况；既要满足倒装芯片在上，底层芯片在下，又要满足两者尺寸相差不大，甚至上层倒装芯片尺寸更小的情况，目前已有封装技术无法实现。
现有技术无法在下层是大的球焊芯片上层堆叠小的倒装芯片，因为大的下层芯片基岛相应也设计的较大，通过焊线连接至管脚上，管脚也要有更大的距离。
发明内容
本发明提出一种倒装芯片与底层芯片的堆叠结构的制备方法，能有效地避让焊接，可以满足倒装芯片或元器件尺寸与底层芯片尺寸相差不大，甚至倒装芯片或元器件尺寸比底层芯片尺寸更小的情况，结构为倒装芯片或元器件在上，底层芯片在下的堆叠结构；满足此类产品封装需求，且能提高封装利用率降低封装成本。
采取的技术方案如下：一种倒装芯片与底层芯片的堆叠结构的制备方法，包括如下步骤：
S1、采用框架材料制备基板层；
S2、在基板层的基岛的正面基岛上装底层芯片；
S3、底层芯片与基板层焊线进行电气连接；
S4、安装金属片，金属片避让焊线;
S5、倒装芯片装在多个金属片上；
S6、塑封料包覆所述倒装芯片与底层芯片的堆叠结构。
对本发明技术方案的进一步优选，金属片的两端之间存在高度差，金属片的低端设置在功能管脚上，金属片的高端悬于底层芯片的正上方，每相邻两个金属片的高端之间留有间隔。
对本发明技术方案的进一步优选，基板层包括基岛和功能管脚，底层芯片与基岛和功能管脚均焊线进行电气连接。
对本发明技术方案的进一步优选，金属片的板面上竖直开设多个通孔。
本发明与现有技术相比的有益效果是：
本发明方法，满足倒装芯片尺寸与底层芯片尺寸相差不大，甚至倒装芯片尺寸比底层芯片尺寸更小的情况，且结构为倒装芯片在上，底层芯片在下的堆叠结构；满足此类产品封装需求，且能提高封装利用率降低封装成本。
附图说明
图1为实施例1方法的步骤S1的基板层的示意图。
图2为实施例1方法的步骤S2的底层芯片安装到基板层的示意图。
图3为实施例1方法的步骤S3的焊线进行电气连接的示意图。
图4为实施例1方法的步骤S4的金属片的示意图。
图5为实施例1方法的步骤S5的安装倒装芯片的示意图。
图6为实施例1方法的步骤S6的塑封料封装后的示意图。
图7为金属片的俯视图。
具体实施方式
下面对本发明技术方案进行详细说明，但是本发明的保护范围不局限于所述实施例。
为使本发明的内容更加明显易懂，以下结合附图1-图7和具体实施方式做进一步的描述。
实施例1
如图1所示，本实施例一种倒装芯片与底层芯片的堆叠结构的制备方法，包括以下步骤：
S1、采用框架材料制备基板层，基板层包括基岛1和功能管脚2。
S2、在基板层的基岛1的正面基岛上装底层芯片3；底层芯片3通过装片胶8安装在基岛1的正面基岛上。
S3、底层芯片3与基板层焊线4进行电气连接，底层芯片3的芯片功能区与基岛1和功能管脚2均焊线4进行电气连接；
S4、安装金属片7，金属片7避让焊线4; 金属片7用锡膏或装片胶8或焊接将金属片7安装在功能管脚2上；
S5、倒装芯片5装在多个金属片7上；
S6、塑封料6包覆倒装芯片与底层芯片的堆叠结构。
本实施例中，金属片7的两端之间存在高度差，目的是为了有效地避让焊线4。金属片7的低端通过锡膏或装片胶8设置在功能管脚2上，金属片7的高端悬于底层芯片3的正上方，每相邻两个金属片7的高端之间留有间隔。
本实施例中，金属片7为定制加工的金属片，此金属片具备如下优点：
1.定制化批量加工，表面可以进行电镀及粗化（粗化可以改善后期与塑封料的结合）处理，对于球焊芯片可以进行打线。
2.定制金属片可以按上层芯片尺寸进行定制化作“通孔”设计，利于塑封时塑封料填充整个结构。
本实施例的中，金属片7可以设计成"Z"字型，可以避让焊线，同时可以和倒装芯片的Bumping进行连接导通。金属片7可以在特定区域进行电镀，举例：例如倒装芯片Bumping下方或元器件两端焊盘位置进行电镀。如图5所示，金属片7高端，在倒装芯片Bumping下方进行电镀。
本实施例中，金属片7的板面上竖直开设多个通孔，通孔的设置，利于塑封时塑封料填充整个结构。
本实施例中，金属片7表面粗化处理，粗化可以改善后期与塑封料的结合。
本实施例中提出的一种倒装芯片与底层芯片的堆叠结构，适用于如图3所示的底层结构，并在上层增加芯片进行堆叠，尤其是上层芯片比底层芯片小很多的情况。
如图5和6所示，本实施例的一种倒装芯片与底层芯片的堆叠结构，包括基板层、底层芯片3、金属片7、倒装芯片5和塑封料6，底层芯片3通过装片胶8装在基岛1的正面基岛上，底层芯片3与基岛1以及功能管脚2之间焊线4进行电气连接，其焊线4为本领域已知技术，本领域技术人员已知。安装金属片7，金属片7的低端通过装片胶8设置在功能管脚2上，金属片7的高端悬于底层芯片3的正上方，每相邻两个金属片7的高端之间留有间隔；金属片7两端之间存在高度差， 目的是为了有效地避让焊线4。倒装芯片5装在多个金属片7的高端的水平面上，塑封料6包覆倒装芯片与底层芯片的堆叠结构。
本实施例的一种倒装芯片与底层芯片的堆叠结构，适用于如图2所示的底层结构，并在上层增加芯片进行堆叠，尤其是上层芯片比底层芯片小很多的情况。
实施例2
基于实施例1的堆叠结构，也适用于如图2所示的底层结构，并在上层增加元器件进行堆叠，尤其是上层的元器件比底层芯片小很多的情况。
基于实施例1，将实施例1中的倒装芯片5替换成元器件，堆叠结构相同，此种结构解决了元器件在上，底层芯片在下，又要满足两者尺寸相差不大，甚至上层元器件尺寸更小的情况。
本实施例，金属片7定制化批量加工，表面可以进行电镀及粗化（粗化可以改善后期与塑封料的结合）处理，对于元器件防止锡扩散。进一步，金属片7可以在特定区域进行电镀，例如元器件两端焊盘位置进行电镀。
本实施例的提出一种元器件与底层芯片的堆叠结构的制备方法，与实施例1的倒装芯片与底层芯片的堆叠结构的制备方法，完全相同。
以上实施例仅为说明本发明的技术思想，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在技术方案基础上所做的任何改动，均落入本发明保护范围之内。

Claims (3)

1.一种倒装芯片与底层芯片的堆叠结构的制备方法，其特征在于：包括以下步骤：
S1、采用框架材料制备基板层；
S2、在基板层的基岛（1）的正面基岛上装底层芯片（3）；
S3、底层芯片（3）与基板层焊线（4）进行电气连接；
S4、安装金属片（7），金属片（7）避让焊线（4）;
S5、倒装芯片（5）装在多个金属片（7）上；
S6、塑封料（6）包覆所述倒装芯片与底层芯片的堆叠结构；
其中，金属片（7）的两端之间存在高度差，金属片（7）的低端设置在功能管脚（2）上，金属片（7）的高端悬于底层芯片（3）的正上方，每相邻两个金属片（7）的高端之间留有间隔。
2.根据权利要求1所述的一种倒装芯片与底层芯片的堆叠结构，其特征在于：基板层包括基岛（1）和功能管脚（2），底层芯片（3）与基岛（1）和功能管脚（2）均焊线（4）进行电气连接。
3.根据权利要求1所述的一种倒装芯片与底层芯片的堆叠结构，其特征在于：金属片（7）的板面上竖直开设多个通孔。
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