CN115395774B - A charge pump circuit structure for low power consumption PWM modulation of AMOLED - Google Patents
A charge pump circuit structure for low power consumption PWM modulation of AMOLED Download PDFInfo
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- CN115395774B CN115395774B CN202210894969.2A CN202210894969A CN115395774B CN 115395774 B CN115395774 B CN 115395774B CN 202210894969 A CN202210894969 A CN 202210894969A CN 115395774 B CN115395774 B CN 115395774B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0012—Control circuits using digital or numerical techniques
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention provides an AMOLED low-power consumption PWM modulated charge pump circuit structure, which comprises five modules, namely a charge pump module, a pulse width modulation module, a slope generation module, a logic module and a driving module, wherein the charge pump module consists of four Pmos tubes, namely Pmos2, pmos3, pmos4 and Pmos5, a flying capacitor C2 and a capacitor C3, the pulse width modulation module consists of a voltage dividing resistor R2, a resistor R3, an error amplifier EA and a comparator COMP, the slope signal slope is generated by the slope generation module, the logic module consists of a D trigger, a rising edge grabbing module, an RS trigger and a NAND gate, and the driving module consists of two driving devices and a group of misphase clock generator, so that the AMOLED low-power consumption PWM charge pump circuit structure has the advantages of low power consumption, high precision, high efficiency and small area.
Description
Technical Field
The invention relates to the technical field of charge pumps, in particular to a charge pump circuit structure for AMOLED low-power PWM modulation.
Background
AMOLED is an active matrix organic light emitting device display. Advantages of such displays over conventional liquid crystal displays include low power consumption, flexible manufacturing, and faster refresh rates. In contrast to conventional liquid crystal displays, AMOLED displays are backlight-free, and thus each pixel consists of an OLED of a different color that emits light independently. The OLED emits light based on a current supplied through a driving transistor controlled by a programming voltage.
The transistor is a nonlinear device, a certain resistance effect is shown in the circuit, the resistance value of the resistance is nonlinear, and according to the difference of the passing current, the research shows that the MOSFET with lower on-Resistance (RDSON) replaces a diode, the forward voltage drop is far lower than the forward voltage drop of a diode rectifier, and therefore the conduction loss of the rectifier is greatly reduced.
Since the PWM modulator is used to generate an adjustment signal to adjust the brightness of each OLED light emitting unit, a charge pump circuit is required to supply a high voltage or a negative voltage higher than an external power supply voltage when the load is heavy. However, according to the charge pump characteristics, when the duty ratio of the charge pump is from 0 to 50%, the output voltage is from low to high, and when the duty ratio of the charge pump is from 50% to 100%, the output voltage is from high to low, even if the charge pump reaches the maximum output energy, the load requirement cannot be met, and the output energy of the charge pump is reduced. Both of the above causes may lead to unstable performance and high power consumption of the PWM modulation circuit.
The invention designs an AMOLED low-power consumption PWM modulated charge pump circuit structure, which can enable the duty ratio to be fixed at 50% when the PH1 duty ratio is higher than 50% through logic control, and the load is changed from heavy load to light load at the moment, so that the energy loss on rdson pipes can be effectively avoided.
Disclosure of Invention
The invention aims to solve the technical problem of providing an AMOLED low-power consumption PWM modulated charge pump circuit structure, which comprises five modules, namely a charge pump module, a pulse width modulation module, a slope generation module, a logic module and a driving module.
The charge pump module is composed of four Pmos tubes, namely Pmos2, pmos3, pmos4 and Pmos5, a capacitor C2 and a capacitor C3, wherein the positive end of the capacitor C2 is connected with the dry end of the Pmos2 and the source end of the Pmos3, the negative end of the capacitor C2 is connected with the dry end of the Pmos5 and the source end of the Pmos4, a driving signal PH1 is connected with the gate end of the Pmos2 and the gate end of the Pmos5, a driving signal PH2 is connected with the gate end of the Pmos3 and the gate end of the Pmos4, an input signal AVDD is connected with the source end of the Pmos2, an input signal vicb is connected with the dry end of the Pmos4, a ground signal gnd is connected with the source end of the Pmos5, an output signal vgh is connected with the dry end of the Pmos3 and the positive end of the filter capacitor C3, and a negative ground signal gnd of the filter capacitor C3 is connected with the ground signal gnd.
The pulse width modulation module is composed of a voltage dividing resistor R2, a resistor R3, an error amplifier EA and a comparator COMP, wherein an output signal vgh of the charge pump module is connected with one end of the voltage dividing resistor R2, the other end of the voltage dividing resistor R2 is connected with an input signal FB and one end of the voltage dividing resistor R3, the other end of the voltage dividing resistor R3 is grounded to a signal gnd, a positive end input of the error amplifier EA is connected with an input signal vref irrelevant to temperature, a negative end input of the error amplifier EA is connected with the input signal FB, an output VC of the error amplifier EA is connected with a negative end input of the comparator COMP, a positive end input of the comparator COMP is connected with a ramp signal slope, and an output end of the comparator COMP is connected with an input end R of the RS trigger to provide an R signal for the RS trigger.
The ramp signal slope is generated by a ramp generating module, the ramp generating module is composed of an inverter inv, an nmos tube nmos1, a Pmos tube Pmos1, a resistor R1 and a capacitor C1, a clock signal CK2_A with 50% duty ratio is connected to the input end of the inverter, the output end of the inverter is connected with the gate end of the Pmos1 and the gate end of the nmos1, the output end of the inverter outputs a signal CK2_B, the source of the Pmos1 is connected with a power supply signal, the drain of the Pmos1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the positive end of the capacitor C1 and the drain end of the nmos1, a node signal at the connection part is the ramp signal slope with 50% duty ratio input to the positive end of the comparator COMP, the negative end of the capacitor C1 is grounded, and the source of the nmos1 is grounded.
The logic module is composed of a D trigger, a rising edge grabbing module, an RS trigger and a NAND gate, wherein a clock input signal CLK is connected with an input CLK end of the D trigger, an input D end and an output QB end of the D trigger are in short circuit, an output Q end outputs a frequency division clock signal CK2_A with a duty ratio of 50%, the frequency division clock signal CK2_A is used as an input signal of the rising edge grabbing module, the rising edge grabbing module outputs a rising edge signal CK2 of the frequency division clock signal CK2_A, an input S end of the RS trigger is connected with an output end of a comparator COMP in the pulse width modulation module, an output end R end of the RS trigger is connected with one input end PH1_ii of the NAND gate, the other input end PH1_i signal of the NAND gate is used as an input end of the driving module.
The driving module consists of two driving devices and a group of misphase clock generator, wherein the output end PH1_i signal of the NAND gate is connected with the input end of the misphase clock generator to generate two groups of misphase clock signals which are not overlapped with each other, the two groups of signals are respectively connected with the input ends of the two driving devices, and the output ends of the two driving devices respectively output driving signals PH1 and PH2.
Drawings
FIG. 1 is a circuit diagram of the present invention;
fig. 2 is a timing diagram illustrating the operation of the PWM modulation of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present invention provides a charge pump circuit structure with AMOLED low-power PWM modulation, which includes five modules, namely a charge pump module, a pulse width modulation module, a ramp generation module, a logic module and a driving module.
The charge pump module is composed of four Pmos tubes, namely Pmos2, pmos3, pmos4 and Pmos5, a capacitor C2 and a capacitor C3, wherein the positive end of the capacitor C2 is connected with the dry end of the Pmos2 and the source end of the Pmos3, the negative end of the capacitor C2 is connected with the dry end of the Pmos5 and the source end of the Pmos4, a driving signal PH1 is connected with the gate end of the Pmos2 and the gate end of the Pmos5, a driving signal PH2 is connected with the gate end of the Pmos3 and the gate end of the Pmos4, an input signal AVDD is connected with the source end of the Pmos2, an input signal vicb is connected with the dry end of the Pmos4, a ground signal gnd is connected with the source end of the Pmos5, an output signal vgh is connected with the dry end of the Pmos3 and the positive end of the filter capacitor C3, and a negative ground signal gnd of the filter capacitor C3 is connected with the ground signal gnd.
The pulse width modulation module is composed of a voltage dividing resistor R2, a resistor R3, an error amplifier EA and a comparator COMP, wherein an output signal vgh of the charge pump module is connected with one end of the voltage dividing resistor R2, the other end of the voltage dividing resistor R2 is connected with an input signal FB and one end of the voltage dividing resistor R3, the other end of the voltage dividing resistor R3 is grounded to a signal gnd, a positive end input of the error amplifier EA is connected with an input signal vref irrelevant to temperature, a negative end input of the error amplifier EA is connected with the input signal FB, an output VC of the error amplifier EA is connected with a negative end input of the comparator COMP, a positive end input of the comparator COMP is connected with a ramp signal slope, and an output end of the comparator COMP is connected with an input end R of the RS trigger to provide an R signal for the RS trigger.
The ramp signal slope is generated by a ramp generating module, the ramp generating module is composed of an inverter inv, an nmos tube nmos1, a Pmos tube Pmos1, a resistor R1 and a capacitor C1, a clock signal CK2_A with 50% duty ratio is connected to the input end of the inverter, the output end of the inverter is connected with the gate end of the Pmos1 and the gate end of the nmos1, the output end of the inverter outputs a signal CK2_B, the source of the Pmos1 is connected with a power supply signal, the drain of the Pmos1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the positive end of the capacitor C1 and the drain end of the nmos1, a node signal at the connection part is the ramp signal slope with 50% duty ratio input to the positive end of the comparator COMP, the negative end of the capacitor C1 is grounded, and the source of the nmos1 is grounded.
The logic module is composed of a D trigger, a rising edge grabbing module, an RS trigger and a NAND gate, wherein a clock input signal CLK is connected with an input CLK end of the D trigger, an input D end and an output QB end of the D trigger are in short circuit, an output Q end outputs a frequency division clock signal CK2_A with a duty ratio of 50%, the frequency division clock signal CK2_A is used as an input signal of the rising edge grabbing module, the rising edge grabbing module outputs a rising edge signal CK2 of the frequency division clock signal CK2_A, an input S end of the RS trigger is connected with an output end of a comparator COMP in the pulse width modulation module, an output end R end of the RS trigger is connected with one input end PH1_ii of the NAND gate, the other input end PH1_i signal of the NAND gate is used as an input end of the driving module.
The driving module consists of two driving devices (dr) and a group of phase-error clock generator (phase_gen), wherein the output end PH1_i signal of the NAND gate is connected with the input end of the phase-error clock generator to generate two groups of phase-error clock signals which are not overlapped with each other, the two groups of signals are respectively connected with the input ends of the two driving devices, and the output ends of the two driving devices respectively output driving signals PH1 and PH2.
The working principle is as follows:
1. ClK generation, namely generating a ring oscillator;
2. CK2_A generates a frequency divided signal of CLK with a fixed duty cycle of 50%;
3. the generation of CK2, namely grabbing the rising edge of CK2_A;
4. FB is generated by vgh partial pressures, fb=k× vgh, fb=vref at steady state;
5. VC is generated, the output of the error amplifier, vc=k (VREF-FB);
6. generation of Slope signal, fixed ramp signal with duty cycle of 50% (controlled by CK2_A);
7. Generation of R signal VC is compared with slope signal, when VC is higher, R signal is more backward (far from CK 2). The lower VC, the farther forward (closer to CK 2) the R signal is;
8. The PH1 signal is generated, the low level time is from rising edge of CK2 signal to rising edge of R signal, the high level time is from rising edge of R signal to rising edge of CK2 signal, because the rising edge of CK2 is fixed, VC controls the rising edge of R signal, so that the duty ratio of PH1 signal can be changed through VC (the maximum duty ratio is 50%, because the duty ratio of charge pump is from 0 to 50%, the output voltage is from low to high, and from 50 to 100%, the output voltage is from high to low, so that the duty ratio is controlled to be linearly adjusted within 0 to 50%), the corresponding proportion of charge pump charging and discharging is changed, and the vgh voltage is controlled;
9. The PH2 signal is generated opposite to PH 1.
And (3) feedback control working process:
The difference between VREF-FB is amplified by an error amplifier to generate VC, VC=Av (VREF-FB), namely when FB is higher, VC is lower, compared with a slope signal (when VC is higher, R signal is backward, namely far from CK2.VC is lower, R signal is forward, namely near CK2, so that the duty ratio of PH1 and PH2 is adjusted, and the voltage vgh is controlled, wherein the feedback control loop process is that when FB is smaller than VREF, VC output is high, PH1 low level time is prolonged (cannot exceed 50% at maximum), namely charging time is increased, vgh output is high, FB is increased, VFB=VREF, and similarly, when FB is larger than VREF, VC output is low, PH1 low level time is shortened (the shortest is 0), namely charging time is reduced, vgh output is low, FB is reduced, FB=VREF.
Referring to fig. 2, the ring oscillator always generates a clock CIK with a fixed frequency, which generates a clock signal ck2_a with a fixed duty ratio of 50% by two frequency division of the D flip-flop, the ck2_a signal is extracted by the rising edge extracting module, the rising edge clock signal CK2 of the ck2_a is used as the S end of the RS flip-flop, the ck2_a signal also controls the ramp generating signal module, that is, the slope signal is a low signal with 50% time, the time is a triangle wave signal with 50% time, when the load is heavy, vgh is pulled down by the load, when the VFB is low even if the charge pump reaches 50% (maximum output energy) and cannot meet the load requirement, VC is high, that is, VC is always greater than slope, that is, the R end of the RS flip-flop is always low, the R signal is not triggered, at this time, the PH1 duty ratio is over 50% and when the output energy of the charge pump is lowered (charge pump characteristics: the charge pump duty ratio is from 0 to 50% and the output voltage is low to high; the output voltage is from high to low at 50% to 100%), so the duty ratio is fixed at 50% by logic control when the PH1 duty ratio is higher than 50%, at this time, the load is changed from heavy load to light load, vgh is gradually increased, i.e. VFB is gradually increased, VC is gradually decreased until VC and slope have an intersection, i.e. the R signal generates a high level, i.e. the PH1 duty ratio is reduced from 50%, so as to inhibit vgh voltage increase, and achieve negative feedback control, and finally stable VFB is equal to VREF, i.e. vgh is stable (vgh =k VFB).
The charge pump circuit structure for AMOLED low-power PWM modulation has the following advantages:
1. low power consumption, namely, when in light load, the low power consumption can be achieved through 0% duty ratio;
2. the precision is high, the duty ratio adjustment belongs to analog signal adjustment, and higher precision can be achieved compared with a digital adjustment mode;
3. High efficiency and small area, one less adjustment rdson tube, and thus one less adjustment rdson tube, relative to a fixed duty cycle, change rdson, i.e., avoid energy loss above the rdson tube.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120122615A (en) * | 2011-04-29 | 2012-11-07 | 주식회사 실리콘웍스 | A charge pump circuit controlling output voltage by time constant |
| CN107046748A (en) * | 2017-03-02 | 2017-08-15 | 上海灿瑞科技股份有限公司 | A kind of LED drive chip and circuit improved to controllable silicon dimmer compatibility |
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| JP5103084B2 (en) * | 2007-07-26 | 2012-12-19 | ローム株式会社 | Charge pump circuit and control circuit thereof |
| KR101310378B1 (en) * | 2008-11-19 | 2013-09-23 | 엘지디스플레이 주식회사 | Liquid crystal display |
| CN101478300B (en) * | 2009-01-06 | 2010-09-15 | 东南大学 | Digital clock duty ratio calibrating circuit |
| CN105897190B (en) * | 2016-04-25 | 2019-03-01 | 深圳市纳芯威科技有限公司 | A kind of D-type audio power amplifier, chip and its distortion detection circuit |
| CN212231423U (en) * | 2020-05-25 | 2020-12-25 | 无锡有容微电子有限公司 | Phase frequency detector and phase-locked loop circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20120122615A (en) * | 2011-04-29 | 2012-11-07 | 주식회사 실리콘웍스 | A charge pump circuit controlling output voltage by time constant |
| CN107046748A (en) * | 2017-03-02 | 2017-08-15 | 上海灿瑞科技股份有限公司 | A kind of LED drive chip and circuit improved to controllable silicon dimmer compatibility |
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Address after: Room 1905, building 4, No. 209, Zhuyuan Road, high tech Zone, Suzhou City, Jiangsu Province 215000 Applicant after: Sunrise Microelectronics (Suzhou) Co.,Ltd. Address before: Room 1905, building 4, No.209, Zhuyuan Road, Suzhou hi tech Zone, Suzhou, Jiangsu 215000 Applicant before: Sheng Microelectronics (Suzhou) Co.,Ltd. |
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