CN115394239A - Display panel and display device - Google Patents

Abstract

The application discloses display panel and display device, this display panel includes a plurality of sub-pixels, many scanning lines and many data lines, through dispose at least a row of sub-pixel in pixel unit and include first sub-pixel, the second sub-pixel that distributes along the first direction in proper order in turn, then many scanning lines are used for driving odd row sub-pixel along the first direction in proper order earlier in a frame, again along the first direction drive even row sub-pixel in proper order, reduced display panel's power consumption.

Description

Display panel and display device

technical field

The present application relates to the field of display technology, in particular to a display panel and a display device.

Background technique

Display panels are widely used in mobile consumer electronic products. For mobile electronic products, not only need to achieve the corresponding display effect, but also need to consider the battery life, and the power consumption is inversely proportional to the battery life. Therefore, low power Power consumption is one of the goals that display panels have been pursuing.

Contents of the invention

The present application provides a display panel and a display device to alleviate the technical problem of high power consumption caused by frequent switching of potentials of data signals.

In a first aspect, the present application provides a display panel, the display panel includes a plurality of sub-pixels, a plurality of scanning lines, and a plurality of data lines, the plurality of sub-pixels includes at least one pixel unit, and each pixel unit includes N*4 rows of sub-pixels , wherein, N is a positive integer, at least one column of sub-pixels in the pixel unit includes first sub-pixels and second sub-pixels that are alternately distributed in sequence along the first direction; multiple scanning lines are arranged in sequence along the first direction, and each scanning line Connected to a corresponding row of sub-pixels in the pixel unit, multiple scanning lines are used to sequentially drive odd-numbered row sub-pixels along the first direction in a frame, and then sequentially drive even-numbered row sub-pixels along the first direction; multiple data lines along The second direction is arranged sequentially, each data line is connected to a corresponding column of sub-pixels in the pixel unit, and the multiple data lines are used to output corresponding data signals according to the driving timing of the multiple scanning lines.

In some of the implementation manners, each pixel unit includes a first row of sub-pixels, a second row of sub-pixels, a third row of sub-pixels, and a fourth row of sub-pixels arranged sequentially along the first direction; The first scanning line, the second scanning line, the third scanning line and the fourth scanning line arranged in sequence in the first direction, the first scanning line is connected to the sub-pixels in the first row, and the second scanning line is connected to the sub-pixels in the second row , the third scanning line is connected to the sub-pixels in the third row, and the fourth scanning line is connected to the sub-pixels in the fourth row; wherein, in one frame, the first scanning line and the third scanning line first respectively drive the sub-pixels in the first row respectively , the sub-pixels in the third row, the second scanning line, and the fourth scanning line respectively drive the sub-pixels in the second row and the sub-pixels in the fourth row in sequence.

In some of the implementation manners, each pixel unit further includes a fifth row of sub-pixels, a sixth row of sub-pixels, a seventh row of sub-pixels, and an eighth row of sub-pixels arranged sequentially along the first direction; the plurality of scanning lines also includes The fifth scanning line, the sixth scanning line, the seventh scanning line and the eighth scanning line arranged in sequence along the first direction, the fifth scanning line is connected to the sub-pixels in the fifth row, and the sixth scanning line is connected to the sub-pixels in the sixth row , the seventh scanning line is connected to the sub-pixels in the seventh row, and the eighth scanning line is connected to the sub-pixels in the eighth row; wherein, in one frame, the first scanning line, the third scanning line, the fifth scanning line, and the seventh scanning line First, the first row of sub-pixels, the third row of sub-pixels, the fifth row of sub-pixels, and the seventh row of sub-pixels are respectively driven in sequence, and the second scanning line, the fourth scanning line, the sixth scanning line, and the eighth scanning line are respectively sequentially The second row of sub-pixels, the fourth row of sub-pixels, the sixth row of sub-pixels, and the eighth row of sub-pixels are driven.

In some of the implementation manners, the pixel unit is configured with a first column of sub-pixels, a second column of sub-pixels and a third column of sub-pixels sequentially arranged along the second direction; The first sub-pixel, the second sub-pixel, the second row of sub-pixels includes a plurality of third sub-pixels distributed along the first direction, the third row of sub-pixels includes second sub-pixels, first sub-pixels alternately distributed along the first direction .

In some embodiments, the first sub-pixel is one of red sub-pixel, green sub-pixel or blue sub-pixel, and the second sub-pixel is another one of red sub-pixel, green sub-pixel or blue sub-pixel, The third sub-pixel is another one of the red sub-pixel, the green sub-pixel or the blue sub-pixel.

In some implementations, in the pixel unit, a data line continuously charges at least two first sub-pixels and/or at least two second sub-pixels.

In some of the implementation manners, each scan line transmits a scan signal; the driving timing of the multiple scan lines is the sequence in which the pulses of the multiple scan signals appear in one frame.

In some of the implementation manners, the sub-pixels in odd rows and the sub-pixels in even rows are alternately distributed in sequence along the first direction.

In a second aspect, the present application provides a display device. The display device includes the display panel and the gate drive circuit in at least one embodiment above. The gate drive circuit is connected to a plurality of scan lines and is used to control the scan lines drive timing.

In some of these embodiments, the display device further includes a data driver, and the data driver is respectively connected to a plurality of data lines; wherein, each data line transmits a data signal; Modulates the voltage output timing of the data signal.

In the display panel and the display device provided by the present application, at least one column of sub-pixels is arranged in the pixel unit, including the first sub-pixels and the second sub-pixels which are alternately distributed in sequence along the first direction, and then a plurality of scanning lines are used in one frame The sub-pixels of the odd rows are sequentially driven along the first direction, and then the sub-pixels of the even rows are sequentially driven along the first direction, so that the data signals provided by the corresponding data lines can continuously be at least two first sub-pixels or at least two second sub-pixels The pixels provide the same charging voltage, which reduces the potential switching frequency of the data signal, thereby reducing the power consumption of the display panel.

Description of drawings

The technical solutions and other beneficial effects of the present application will be apparent through the detailed description of the specific embodiments of the present application below in conjunction with the accompanying drawings.

FIG. 1 is a schematic structural diagram of a pixel circuit in the related art.

FIG. 2 is a timing schematic diagram of the pixel circuit shown in FIG. 1 .

FIG. 3 is a schematic diagram of frame time allocation at different frequencies.

FIG. 4 is another structural schematic diagram of a pixel circuit in the related art.

FIG. 5 is a timing schematic diagram of the pixel circuit shown in FIG. 4 .

FIG. 6 is a schematic structural diagram of a display device provided by an embodiment of the present application.

FIG. 7 is another schematic structural diagram of a display device provided by an embodiment of the present application.

FIG. 8 is a schematic diagram of the driving sequence of the display device shown in FIG. 7 in the related art.

FIG. 9 is a schematic diagram of potential changes of the data signal in FIG. 8 .

FIG. 10 is a schematic diagram of the driving sequence of the display device shown in FIG. 7 in this application.

FIG. 11 is a schematic diagram of potential changes of the data signal in FIG. 10 .

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application.

1 is a schematic structural diagram of a pixel circuit in the related art. The pixel circuit includes a first initialization transistor T7, a second initialization transistor T4, a compensation transistor T3, a driving transistor T1, a writing transistor T2, a first light emission control transistor T5, The second light emission control transistor T6, the storage capacitor Cst and the light emitting device LED, the positive power line is connected to one end of the storage capacitor Cst and the source/drain of the first light emission control transistor T5, and the source of the first light emission control transistor T5 The other electrode/drain is connected to one of the source/drain of the write transistor T2 and one of the source/drain of the drive transistor T1, and the gate of the first light emission control transistor T5 is connected to the light emission control line Connected, the other of the source/drain of the write transistor T2 is connected to the data line, the gate of the write transistor T2 is connected to the first control line, the other of the source/drain of the drive transistor T1 is connected to the compensation One of the source/drain of the transistor T3 and one of the source/drain of the second light emission control transistor T6 are connected, and the other of the source/drain of the second light emission control transistor T6 is connected to the light emitting device LED One of the anode and the source/drain of the first initialization transistor T7 is connected, the cathode of the light-emitting device LED is connected to the negative power supply line, the gate of the first initialization transistor T7 is connected to the second control line, and the gate of the first initialization transistor T7 The other of the source/drain is connected to one of the source/drain of the reference voltage line and the second initialization transistor T4, the gate of the second initialization transistor T4 is connected to the second control line, and the second initialization transistor T4 The other of the source/drain is connected to the other end of the storage capacitor Cst, the other of the source/drain of the compensation transistor T3 and the gate of the driving transistor T1, and the gate of the compensation transistor T3 is connected to the first control line connection.

Wherein, point G represents the gate of the driving transistor T1. The positive power line is used to transmit the positive power signal ELVDD, and the negative power line is used to transmit the negative power signal ELVSS. The potential of the positive power signal ELVDD is generally a positive voltage, and the potential of the negative power signal ELVSS is generally a negative voltage. The light emitting control line is used to transmit the light emitting control signal EM. The data line is used to transmit the data signal DATA. The reference voltage line is used to transmit the reference voltage signal VREF. The first control line is used to transmit the first control signal S2. The second control signal S1 is used to transmit the second control signal S1.

Wherein, the light emitting device LED may be an organic light emitting diode, a micro light emitting diode, a mini light emitting diode or a quantum dot light emitting diode.

Wherein, the first initialization transistor T7, the second initialization transistor T4, the compensation transistor T3, the drive transistor T1, the write transistor T2, the first light emission control transistor T5, and the second light emission control transistor T6 can all be P-channel thin film transistors, Specifically, it may also be a low temperature polysilicon thin film transistor.

Fig. 2 is a schematic timing diagram of the pixel circuit shown in Fig. 1, and the working stages of the pixel circuit shown in Fig. 1 in one frame include the following stages:

Reset phase P1: the second control signal S1 is at low level, the first initialization transistor T7 and the second initialization transistor T4 are turned on, the light emission control signal EM and the first control signal S2 are at high level, and other transistors are turned off. Pull the potential of point G and the anode of the light-emitting device LED to the potential of the reference voltage signal VREF to reset the anode of the light-emitting device LED and the gate of the driving transistor T1, that is, point G.

Charging compensation stage P2: the first control signal S2 is at low level, the second control signal S1 and the light emission control signal EM are at high level, and the compensation transistor T3 and the writing transistor T2 are turned on. Since the potential at point G in the reset stage P1 is Referring to the potential of the voltage signal VREF, the driving transistor T1 is turned on to charge the point G.

Light-emitting stage P3: the light-emitting control signal EM is at low level, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the driving transistor T1 are turned on, other transistors are turned off, and the light-emitting device LED emits light.

The working frequency of display products is usually not limited to 60hz, and can also be 120hz, 90hz and other frequency points. In order to ensure the screen display effect and avoid brightness differences caused by switching between different frequencies, the data writing time T10 of different frequency points is the same. The writing time T10 is shown in FIG. 3 . In one frame (1 frame), the data writing time T10 for all frequencies is the same, and the rest of the time is filled in the blank time T11, and the blank time T11 decreases as the frequency increases.

Under the premise of the above driving scheme, the power saving driving scheme:

First: within the blank time T11, turn off the voltage output of the data signal DATA;

Second: during the blank time T11, the first control signal S2 and/or the second control signal S1 related to the data writing time T10 are turned off.

The above solution mainly uses the blank time T11 to turn off the corresponding signal and voltage, so as to save power consumption. It can be seen from FIG. 3 that the blank time T11 has different lengths at different frequencies. The higher the frequency, the shorter the blank time T11 , and the less power consumption can be reduced. That is to say, the higher the frequency, the higher the power consumption. The above solution for saving power consumption is mainly realized by reducing the power consumption of each signal in the pixel circuit, and the proportion of power consumption that can be reduced is relatively small.

In order to save power consumption, the development of a new LTPO (Low Temperature Polycrystalline Oxide) process is to replace the channel type of the compensation transistor T3, the first initialization transistor T7 and the second initialization transistor T4 in Figure 1 with the metal oxide shown in Figure 4 The thin film transistor, specifically the InGaZnO thin film transistor, can reduce the gate leakage current of the driving transistor T1 and realize low-frequency driving. Different frequencies are used according to the displayed application scenarios, for example, a still image can use a frequency of 30Hz or 1Hz, which can achieve the purpose of saving power consumption as a whole.

Compared with the pixel circuit shown in FIG. 1, the pixel circuit shown in FIG. 4 replaces the compensation transistor T3, the first initialization transistor T7, and the second initialization transistor T4 with indium gallium zinc oxide thin film transistors, correspondingly, the first initialization The gate of the transistor T7 is still connected to the second control signal S1, the connection signal of the gate of the second initialization transistor T4 is changed to the first control signal S2, and the connection signal written to the gate of the transistor T2 is changed to the third control signal S1. The signal S3, the input signal of the gate of the compensation transistor T3, is changed to the fourth control signal S4.

The working stages of the pixel circuit shown in Figure 4 in one frame are shown in Figure 5, including the following stages:

First stage: the first control signal S2 and the second control signal S1 are at high level, and the gate potential of the driving transistor T1 and the anode potential of the light emitting device LED are reset.

The second stage: the third control signal S3 is at low level, the fourth control signal S4 is at high level, and the data signal DATA is written into the gate of the driving transistor T1.

The third stage: the light-emitting control signal EM is at a low level, and the light-emitting device LED emits light.

For the pixel circuits shown in FIG. 4 and FIG. 5 , electric leakage still exists when operating at a low frequency, resulting in flickering. In order to solve the flickering problem, the second control signal S1 , the third control signal S3 and the data signal DATA still need to work during the blanking time, that is, consume power continuously. It can be seen that the solution for saving power in the pixel circuits shown in FIGS. 1 to 3 cannot be applied to the pixel circuits shown in FIGS. 4 and 5 .

To sum up, the above solutions for reducing power consumption have certain limitations. Therefore, it is necessary to propose a new driving scheme that can reduce power consumption as a whole, so as to be applicable to various pixel circuits.

6 is a schematic structural diagram of a display device provided by an embodiment of the present application. The display device includes a data driver 200 and a display panel 300. The data driver 200 provides the display panel 300 with a control signal and a data signal DATA with power consumption; and the external The drive power supplies the data driver 200 with the first power supply VDDIO, the second power supply AVDD and the third power supply VCI, so as to ensure the normal operation of the data driver 200 . At the same time, the light-emitting power supply provides the display panel 300 with a positive power signal ELVDD and a negative power signal ELVSS.

It can be understood that reducing the power consumption of at least one of the first power supply VDDIO, the second power supply AVDD, the third power supply VCI, the control signal, the data signal DATA, the positive power signal ELVDD, and the negative power signal ELVSS can reduce power consumption. Purpose.

In view of the limitations of the above-mentioned technical means for reducing power consumption, it is necessary to propose a technical means for reducing the potential switching frequency of the data signal DATA to reduce power consumption. Therefore, this embodiment provides a display panel 300 , please refer to FIG. 1 to FIG. 11 , as shown in FIG. 7 , FIG. 10 and FIG. 11 , the display panel 300 includes a plurality of sub-pixels, a plurality of scanning lines and a plurality of data lines.

The multiple sub-pixels include at least one pixel unit, and each pixel unit includes N*4 rows of sub-pixels, where N is a positive integer.

For example, when N is 1, one pixel unit may include 4 rows of sub-pixels as shown in FIG. 7 . It can be understood that N can also be a positive integer such as 2, 3, 4, 5... and so on.

At least one column of sub-pixels in the pixel unit includes first sub-pixels and second sub-pixels that are sequentially and alternately distributed along the first direction DR1.

It should be noted that, in different embodiments, the first sub-pixel can be one of red sub-pixel, green sub-pixel or blue sub-pixel; the second sub-pixel can be red sub-pixel, green sub-pixel or blue sub-pixel. Another one of the dichromatic subpixels.

A plurality of scanning lines are arranged in sequence along the first direction DR1, and each scanning line is connected to a corresponding row of sub-pixels in the pixel unit, and the plurality of scanning lines are used to sequentially drive odd-numbered rows of sub-pixels along the first direction DR1 in one frame and driving the sub-pixels in even rows sequentially along the first direction DR1.

It should be noted that, in this way, at least two first sub-pixels or at least two second sub-pixels in the same column of sub-pixels can be continuously driven or turned on, and the same charging voltage is continuously provided to at least two first sub-pixels for the data signal DATA. A sub-pixel or at least two second sub-pixels form the basis.

A plurality of data lines are sequentially arranged along the second direction DR2, each data line is connected to a corresponding column of sub-pixels in the pixel unit, and the plurality of data lines are used to output corresponding data signals DATA according to the driving timing of the plurality of scanning lines.

It can be understood that, in the display panel 300 provided in this embodiment, by configuring at least one column of sub-pixels in the pixel unit to include first sub-pixels and second sub-pixels that are alternately distributed in sequence along the first direction DR1, and then multiple scanning lines use In one frame, the odd-numbered sub-pixels are sequentially driven along the first direction DR1, and then the even-numbered sub-pixels are sequentially driven along the first direction DR1, so that the data signal DATA provided by the corresponding data line can continuously be at least two first sub-pixels The pixels or at least two second sub-pixels provide the same charging voltage, which reduces the potential switching frequency of the data signal DATA, thereby reducing the power consumption of the display panel 300 .

In one embodiment, as shown in FIG. 7 , each pixel unit includes a first row of sub-pixels, a second row of sub-pixels, a third row of sub-pixels, and a fourth row of sub-pixels arranged in sequence along the first direction DR1. The plurality of scanning lines include the first scanning line GL1, the second scanning line GL2, the third scanning line GL3 and the fourth scanning line GL4 arranged in sequence along the first direction DR1, the first scanning line GL1 and the first row of sub-pixels connected, the second scan line GL2 is connected with the sub-pixels of the second row, the third scan line GL3 is connected with the sub-pixels of the third row, and the fourth scan line GL4 is connected with the sub-pixels of the fourth row; wherein, in one frame, the first The scanning line GL1 and the third scanning line GL3 first respectively drive the sub-pixels of the first row and the sub-pixels of the third row in turn, and the second scanning line GL2 and the fourth scanning line GL4 respectively drive the sub-pixels of the second row and the sub-pixels of the fourth row respectively in turn. pixels.

It should be noted that the first scanning line GL1 , the second scanning line GL2 , the third scanning line GL3 and the fourth scanning line GL4 are respectively used to transmit the first scanning signal G1 , the second scanning signal G2 and the third scanning signal in sequence. G3 and the fourth scanning signal G4.

The first data line DL1 is connected to the sub-pixels of the first column, the second data line DL2 is connected to the sub-pixels of the second column, the third data line DL3 is connected to the sub-pixels of the third column, and the fourth data line DL4 is connected to the sub-pixels of the fourth column. The first data line DL1, the second data line DL2, the third data line DL3 and the fourth data line DL4 are respectively used to transmit the first data signal D1, the second data signal D2, the third data signal D3 and the fourth data signal in sequence D4.

It can be understood that, in this embodiment, when the first scan line GL1 and the third scan line GL3 respectively drive the sub-pixels in the first row and the sub-pixels in the third row in sequence, the first data signal D1 can continuously be the first row of sub-pixels. The two first sub-pixels of the same color in a column of sub-pixels are charged without switching potentials, which can reduce the power consumption of the data signal DATA. Similarly, when the second scanning line GL2 and the fourth scanning line GL4 respectively drive the sub-pixels in the second row and the sub-pixels in the fourth row in sequence, the first data signal D1 can continuously be the sub-pixels of the same color in the first row of sub-pixels. The two second sub-pixels are charged without switching potentials, which can reduce the power consumption of the data signal DATA.

In one embodiment, each pixel unit further includes a fifth row of sub-pixels, a sixth row of sub-pixels, a seventh row of sub-pixels, and an eighth row of sub-pixels arranged in sequence along the first direction DR1; It includes the fifth scanning line, the sixth scanning line, the seventh scanning line and the eighth scanning line arranged in sequence along the first direction DR1, the fifth scanning line is connected to the sub-pixels in the fifth row, and the sixth scanning line is connected to the sub-pixels in the sixth row. The pixels are connected, the seventh scanning line is connected to the sub-pixels in the seventh row, and the eighth scanning line is connected to the sub-pixels in the eighth row; wherein, in one frame, the first scanning line GL1, the third scanning line GL3, the fifth scanning line , The seventh scanning line respectively drives the first row of sub-pixels, the third row of sub-pixels, the fifth row of sub-pixels, the seventh row of sub-pixels, the second scanning line GL2, the fourth scanning line GL4, the sixth scanning line, the The eight scanning lines respectively drive the sub-pixels in the second row, the sub-pixels in the fourth row, the sub-pixels in the sixth row, and the sub-pixels in the eighth row in sequence.

It should be noted that the pixel unit in this embodiment includes eight rows of sub-pixels, which can save more power consumption than four rows of sub-pixels. By analogy, when the number of rows of sub-pixels in a pixel unit increases For a long time, more and more power consumption can be saved correspondingly.

It can be understood that, in this embodiment, when the first scanning line GL1 , the third scanning line GL3 , the fifth scanning line, and the seventh scanning line respectively drive the sub-pixels in the first row, the sub-pixels in the third row, and the sub-pixels in the When there are five rows of sub-pixels and the seventh row of sub-pixels, the first data signal D1 can continuously charge the four first sub-pixels of the same color in the first column of sub-pixels without switching potentials, which can further reduce the power consumption of the data signal DATA . Similarly, when the second scanning line GL2, the fourth scanning line GL4, the sixth scanning line, and the eighth scanning line respectively drive the sub-pixels in the second row, the sub-pixels in the fourth row, the sub-pixels in the sixth row, and the eighth row When using sub-pixels, the first data signal D1 can continuously charge the four second sub-pixels of the same color in the first column of sub-pixels without switching potentials, which can further reduce the power consumption of the data signal DATA.

In one of the embodiments, the pixel unit is configured with a first column of sub-pixels, a second column of sub-pixels and a third column of sub-pixels sequentially arranged along the second direction DR2; distributed first sub-pixels and second sub-pixels, the second column of sub-pixels includes a plurality of third sub-pixels distributed along the first direction DR1, and the third column of sub-pixels includes second sub-pixels alternately distributed in sequence along the first direction DR1, the first subpixel.

It should be noted that the arrangement of the second sub-pixels and the first sub-pixels in the third row of sub-pixels can also reduce the power consumption of the third data signal D3 , and further reduce the power consumption of the display panel 300 .

In one of the embodiments, the first sub-pixel is one of red sub-pixel, green sub-pixel or blue sub-pixel, and the second sub-pixel is another one of red sub-pixel, green sub-pixel or blue sub-pixel, The third sub-pixel is another one of the red sub-pixel, the green sub-pixel or the blue sub-pixel.

It should be noted that, in some embodiments, the plurality of sub-pixels may further include a fourth sub-pixel, wherein any two of the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel are If they are arranged alternately in the same column, the power consumption of the corresponding data signal DATA can be reduced.

In one embodiment, in the pixel unit, a data line continuously charges at least two first sub-pixels and/or at least two second sub-pixels.

It should be noted that when the number of rows of sub-pixels in the pixel unit is more, the corresponding data line can continuously charge more first sub-pixels and/or second sub-pixels without potential switching, which can Save more power consumption.

In one embodiment, as shown in FIG. 7 and FIG. 10 , each scan line transmits a scan signal; the driving timing of multiple scan lines is the order in which pulses of multiple scan signals appear in one frame.

For example, the driving timing of multiple scanning lines is to sequentially drive or turn on the sub-pixels in the first row, the sub-pixels in the third row, the sub-pixels in the second row, and the sub-pixels in the fourth row to allow the data signal DATA to be written into the corresponding sub-pixels. .

In one of the embodiments, sub-pixels in odd rows and sub-pixels in even rows are alternately distributed in sequence along the first direction DR1.

It should be noted that the odd row of sub-pixels can be the first row of sub-pixels, the third row of sub-pixels, etc., and the even-numbered row of sub-pixels can be the second row of sub-pixels, the fourth row of sub-pixels.. .and so on.

In one of the embodiments, as shown in FIG. 7 , this embodiment provides a display device, the display device includes the display panel 300 and the gate drive circuit 100 in at least one embodiment above, and the gate drive circuit 100 and multiple The scan lines are respectively connected to control the driving timing of the multiple scan lines.

It can be understood that, in the display device provided by this embodiment, by configuring at least one column of sub-pixels in the pixel unit to include first sub-pixels and second sub-pixels that are alternately distributed in sequence along the first direction DR1, and then a plurality of scanning lines are used for In one frame, the odd-numbered sub-pixels are sequentially driven along the first direction DR1, and then the even-numbered sub-pixels are sequentially driven along the first direction DR1, so that the data signal DATA provided by the corresponding data line can continuously be at least two first sub-pixels Or at least two second sub-pixels provide the same charging voltage, which reduces the potential switching frequency of the data signal DATA, thereby reducing the power consumption of the display panel 300 .

It should be noted that the gate drive circuit 100 may include a first gate drive unit GU1, a second gate drive unit GU2, a third gate drive unit GU3, and a fourth gate drive unit GU4. The scanning mode can be realized by connecting the second gate driving unit GU2 to the third scanning line GL3, and connecting the third gate driving unit GU3 to the second scanning line GL2, or it can also be realized by connecting the first gate driving unit GU1 and the third scanning line GL3. The gate driving unit GU, the second gate driving unit GU2 and the fourth gate driving unit GU4 are sequentially cascaded to realize the change of the driving timing.

In one of the embodiments, as shown in FIG. 7, the display device further includes a data driver 200, and the data driver 200 is respectively connected to a plurality of data lines; wherein, each data line transmits a data signal DATA; the data driver 200 includes a data mapping module, the data mapping module is used to modulate the voltage output timing of the data signal DATA according to the driving timing.

It should be noted that the change of the scanning sequence also involves the adjustment of the charging sequence. Therefore, the adjustment of the charging sequence can directly change the format of the video data connected from the outside according to the driving sequence, or it can also be done without changing the video data. In the case of the format, the data mapping module configured in this embodiment is used to adjust the arrangement order of different voltages in the data signal DATA.

8 is a schematic diagram of the driving sequence of the display device shown in FIG. 7 in the related art. The first scanning signal G1, the second scanning signal G2, the third scanning signal G3, and the fourth scanning signal G4 sequentially drive the first row of sub-pixels, The sub-pixels in the second row, the sub-pixels in the third row, and the sub-pixels in the fourth row correspond to each time after the first data signal D1 and the third data signal D3 charge a sub-pixel, a potential switching is required. Larger power consumption; both the second data signal D2 and the fourth data signal D4 can continuously charge a sub-pixel of one color, therefore, no potential switching is required, and more power consumption for potential switching is unnecessary.

Wherein, R may be used to represent a red sub-pixel, G may be used to represent a green sub-pixel, and B may be used to represent a blue sub-pixel.

FIG. 9 is a schematic diagram of potential changes of the data signal DATA in FIG. 8. When a red picture is displayed, the first data signal D1 and the third data signal D3 both provide low potentials for the corresponding red sub-pixels, and provide corresponding low potentials for the blue sub-pixels. However, every time the charging object is changed, the corresponding data signal DATA needs to switch the potential once, that is, switch from high potential to low potential or switch from low potential to high potential, so that the first data signal D1, the third data The signal D3 needs to consume relatively large power consumption. The second data signal D2 and the fourth data signal D4 only need to provide a constant potential to the sub-pixels in the second column and the sub-pixels in the fourth column.

Similarly, when a green screen is displayed, the first data signal D1, the third data signal D3, the second data signal D2, and the fourth data signal D4 all need to provide a constant potential to the corresponding sub-pixels, so that there is no need to consider the data The potential switching power consumption of the signal DATA is also the lowest.

Similarly, when a blue screen is displayed, the first data signal D1 and the third data signal D3 both provide a high potential for the corresponding red sub-pixel, and provide a corresponding low potential for the blue sub-pixel. When the object is connected, the corresponding data signal DATA needs to be switched once, that is, switched from high potential to low potential or from low potential to high potential, so that the first data signal D1 and the third data signal D3 need to consume large power consumption. The second data signal D2 and the fourth data signal D4 only need to provide a constant potential to the sub-pixels in the second column and the sub-pixels in the fourth column.

In view of this, FIG. 10 uses the first scanning signal G1, the third scanning signal G3, the second scanning signal G2, and the fourth scanning signal G4 to sequentially drive the first row of sub-pixels, the third row of sub-pixels, and the second row of sub-pixels respectively. , the fourth row of sub-pixels, correspondingly, after the first data signal D1 and the third data signal D3 charge two sub-pixels each time, a potential switching is required, which can save 50 % power consumption; both the second data signal D2 and the fourth data signal D4 can continuously charge a sub-pixel of one color, therefore, there is no need for potential switching, and no more power consumption for potential switching.

Fig. 11 is a schematic diagram of the potential change of the data signal DATA in Fig. 10. When a red picture is displayed, the first data signal D1 and the third data signal D3 both provide a low potential for the corresponding red sub-pixel, and provide a corresponding low potential for the blue sub-pixel. high potential. Every time at least two sub-pixels of the same color can be continuously charged, the potential needs to be switched once, that is, switching from high potential to low potential or switching from low potential to high potential, so that the first data signal D1 and the third data signal D3 Compared with the switching frequency shown in FIG. 8 , the switching frequency is reduced by at least half, and correspondingly, the power consumption required for potential switching is also reduced by half. The second data signal D2 and the fourth data signal D4 only need to provide a constant potential to the sub-pixels in the second column and the sub-pixels in the fourth column.

Similarly, when a green screen is displayed, the first data signal D1, the third data signal D3, the second data signal D2, and the fourth data signal D4 all need to provide a constant potential to the corresponding sub-pixels, so that there is no need to consider the data The potential switching power consumption of the signal DATA is also the lowest.

Similarly, when a blue picture is displayed, both the first data signal D1 and the third data signal D3 provide a high potential for the corresponding red sub-pixel, and provide a corresponding low potential for the blue sub-pixel. Every time at least two sub-pixels of the same color can be continuously charged, the potential needs to be switched once, that is, switching from high potential to low potential or switching from low potential to high potential, so that the first data signal D1 and the third data signal D3 Compared with the switching frequency shown in FIG. 8 , the switching frequency is reduced by at least half, and correspondingly, the power consumption required for potential switching is also reduced by half. The second data signal D2 and the fourth data signal D4 only need to provide a constant potential to the sub-pixels in the second column and the sub-pixels in the fourth column.

In the foregoing embodiments, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments.

The display panel 300 and the display device provided by the embodiment of the present application have been introduced in detail above. In this paper, specific examples are used to illustrate the principle and implementation of the present application. The description of the above embodiment is only used to help understand the present application. Technical solutions and their core ideas; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not The essence of the corresponding technical solutions deviates from the scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. A display panel, characterized in that, comprising: A plurality of sub-pixels, the plurality of sub-pixels include at least one pixel unit, each of which includes N*4 rows of sub-pixels, where N is a positive integer, and at least one column of sub-pixels in the pixel unit includes first sub-pixels and second sub-pixels distributed alternately in sequence; A plurality of scanning lines, the plurality of scanning lines are arranged in sequence along the first direction, each of the scanning lines is connected to a corresponding row of sub-pixels in the pixel unit, and the plurality of scanning lines are used for In the frame, the odd-numbered rows of sub-pixels are sequentially driven along the first direction, and then the even-numbered rows of sub-pixels are sequentially driven along the first direction; and A plurality of data lines, the plurality of data lines are arranged in sequence along the second direction, each of the data lines is connected to a corresponding column of sub-pixels in the pixel unit, and the plurality of data lines are used to The corresponding data signals are output in the driving timing of the scan lines. 2. The display panel according to claim 1, wherein each of the pixel units comprises a first row of sub-pixels, a second row of sub-pixels, and a third row of sub-pixels arranged in sequence along the first direction. and the fourth row of sub-pixels; The plurality of scan lines include a first scan line, a second scan line, a third scan line and a fourth scan line arranged in sequence along the first direction, the first scan line and the first row sub-line pixel connection, the second scan line is connected to the second row of sub-pixels, the third scan line is connected to the third row of sub-pixels, and the fourth scan line is connected to the fourth row of sub-pixels ; Wherein, in one frame, the first scan line and the third scan line respectively drive the sub-pixels in the first row and the sub-pixels in the third row respectively in turn, and the second scan line, the third scan line The four scan lines respectively drive the sub-pixels in the second row and the sub-pixels in the fourth row in sequence. 3. The display panel according to claim 2, wherein each of the pixel units further comprises a fifth row of sub-pixels, a sixth row of sub-pixels, and a seventh row of sub-pixels arranged in sequence along the first direction. and the eighth row of sub-pixels; The plurality of scan lines further include a fifth scan line, a sixth scan line, a seventh scan line, and an eighth scan line arranged in sequence along the first direction, and the fifth scan line is connected to the fifth row of sub-lines. pixel connection, the sixth scan line is connected to the sixth row of sub-pixels, the seventh scan line is connected to the seventh row of sub-pixels, and the eighth scan line is connected to the eighth row of sub-pixels ; Wherein, in one frame, the first scanning line, the third scanning line, the fifth scanning line, and the seventh scanning line respectively drive the first row of sub-pixels, the third row of sub-pixels, the fifth row of sub-pixels, the seventh row of sub-pixels, the second scan line, the fourth scan line, the sixth scan line, and the eighth scan line are respectively driven sequentially The second row of sub-pixels, the fourth row of sub-pixels, the sixth row of sub-pixels, and the eighth row of sub-pixels. 4. The display panel according to claim 1, wherein a first column of sub-pixels, a second column of sub-pixels, and a third column of sub-pixels arranged sequentially along the second direction are arranged in the pixel unit; Wherein, the first row of sub-pixels includes the first sub-pixels and the second sub-pixels that are alternately distributed along the first direction, and the second row of sub-pixels includes a plurality of sub-pixels distributed along the first direction. The third sub-pixel, the third column of sub-pixels includes the second sub-pixels and the first sub-pixels which are sequentially and alternately distributed along the first direction. 5. The display panel according to claim 4, wherein the first sub-pixel is one of a red sub-pixel, a green sub-pixel or a blue sub-pixel, and the second sub-pixel is a red sub-pixel, a green sub-pixel, or a blue sub-pixel. The other one of the green sub-pixel or the blue sub-pixel, and the third sub-pixel is another one of the red sub-pixel, the green sub-pixel or the blue sub-pixel. 6. The display panel according to claim 1, wherein in the pixel unit, one of the data lines is at least two of the first sub-pixels and/or at least two of the second sub-pixels Charge continuously. 7. The display panel according to claim 1, wherein each of the scanning lines transmits a scanning signal; the driving timing of the plurality of scanning lines is that a plurality of pulses of the scanning signal appear in one frame in the order of. 8 . The display panel according to claim 1 , wherein the sub-pixels of the odd rows and the sub-pixels of the even rows are alternately distributed in sequence along the first direction. 9. A display device, characterized in that it comprises: A display panel as claimed in any one of claims 1 to 8; and A gate driving circuit, the gate driving circuit is respectively connected to the plurality of scanning lines, and is used to control the driving timing of the plurality of scanning lines. 10. The display device according to claim 9, further comprising a data driver, the data driver is respectively connected to the plurality of data lines; Wherein, each data line transmits a data signal; the data driver includes a data mapping module, and the data mapping module is used for modulating the voltage output timing of the data signal according to the driving timing.

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