CN115394232B - Gate scanning circuit and method - Google Patents
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- CN115394232B CN115394232B CN202211205072.0A CN202211205072A CN115394232B CN 115394232 B CN115394232 B CN 115394232B CN 202211205072 A CN202211205072 A CN 202211205072A CN 115394232 B CN115394232 B CN 115394232B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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Abstract
本发明公开了一种栅极扫描电路及方法，扫描电路包括第一电平输入线、第二电平输入线、第三电平输入线、第一扫描线、第二扫描线、第三扫描线、第四电平输入线、第五电平输入线、第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第一电容及下拉单元；还公开了一种扫描方法。通过扫描电路中设置常开晶体管，使得输入端的晶体管的栅极仅承受一行的高电平，通过进一步在输入端采用“双删结构”，进一步降低和分担了输入端的晶体管栅极的应力，从而使栅极扫描电路的可靠性和稳定性得到提升。
The present invention discloses a gate scanning circuit and method, wherein the scanning circuit comprises a first level input line, a second level input line, a third level input line, a first scanning line, a second scanning line, a third scanning line, a fourth level input line, a fifth level input line, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor and a pull-down unit; and also discloses a scanning method. By setting a normally-on transistor in the scanning circuit, the gate of the transistor at the input end only bears a high level of one row, and by further adopting a "double deletion structure" at the input end, the stress of the transistor gate at the input end is further reduced and shared, thereby improving the reliability and stability of the gate scanning circuit.
Description
Technical Field
The present invention relates to the field of display panels, and in particular, to a gate scanning circuit and a method thereof.
Background
The display panel usually performs a normal scan or a reverse scan operation, however, when one of the operation states is switched to the other scan operation state, stress abnormality of the individual transistors often occurs, which results in failure of the gate circuit to transfer, and abnormal display.
For example, during a normal scan, the input high level causes the gate of the transistor at the input terminal to be subjected to high level stress for a long time, and especially during a high and low temperature reliability test, such stress is further exacerbated, which eventually leads to the transistor failure.
In chinese patent CN 106452025A, a technical solution for a switch with an on transistor and an off transistor is disclosed, so that the problem of transistor stress anomalies can be considered to be solved with an on transistor.
Disclosure of Invention
In the scanning process, the input high level of the gate driving circuit of the conventional display panel can enable the high level of the input end to bear high level stress for a long time, and finally, the transistor is disabled.
Aiming at the problems, a gate scanning circuit and a method are provided, wherein normally-on transistors are arranged in the scanning circuit, so that the gates of the transistors at the input end only bear one row of high level, and the stress of the gates of the transistors at the input end is further reduced and shared by adopting a double-deleting structure at the input end, so that the reliability and the stability of the gate scanning circuit are improved.
In a first aspect, a gate scan circuit for forming a display panel gate scan circuit by cascading includes:
a first level input line, a second level input line, a third level input line, a first scan line, a second scan line, a third scan line, a fourth level input line, a fifth level input line, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, and a pull-down unit;
the first level input line and the second level input line are respectively connected with the grid electrode of the first transistor and the grid electrode of the second transistor;
the first scanning line and the third scanning line are respectively connected with the drain electrode of the first transistor and the source electrode of the second transistor;
the source electrode of the first transistor is commonly connected with the drain electrode of the second transistor to form a first common joint;
The fourth level input line and the fifth level input line are respectively connected with the grid electrode of the third transistor and the grid electrode of the fourth transistor;
The source electrode of the third transistor and the drain electrode of the fourth transistor are respectively connected with the first common junction;
The drain electrode of the third transistor and the source electrode of the fourth transistor are connected together to form a second common joint;
the grid electrode of the fifth transistor, the first end of the first capacitor and the first end of the pull-down unit are respectively connected with the second common contact point;
the source electrode of the fifth transistor, the second end of the first capacitor and the second end of the pull-down unit are connected together to form a third common joint;
the second scanning line is connected with the third common joint;
the third level input line is connected to the drain of the fifth transistor.
In combination with the gate scanning circuit according to the present invention, in a first possible implementation manner, the scanning circuit further includes:
A sixth transistor;
A seventh transistor;
The first level input line is electrically connected with the grid electrode of the first transistor and the grid electrode of the sixth transistor respectively, and the source electrode of the first transistor is electrically connected with the drain electrode of the sixth transistor;
the second level input line is electrically connected with the grid electrode of the second transistor and the grid electrode of the seventh transistor respectively, and the drain electrode of the second transistor is electrically connected with the source electrode of the seventh transistor;
The source electrode of the sixth transistor and the drain electrode of the seventh transistor are respectively and electrically connected with the first common connection point.
In combination with the first possible embodiment of the present invention, in a second possible embodiment, the fourth level input line and the fifth level input line alternately input a high level and a low level to the third transistor and the fourth transistor, respectively, in units of frames.
In combination with the second possible embodiment of the present invention, in a third possible embodiment, the third transistor and the fourth transistor are normally-on transistors.
A second aspect of the present invention provides a gate scanning method, using the scanning circuit of the first aspect, comprising:
In the normal sweeping stage:
At a first moment, a first level input line is controlled to input a high level to the grid electrode of the first transistor, so that the first transistor is turned on, and a high level and a low level are alternately input to the grid electrode of the third transistor and the grid electrode of the fourth transistor respectively in a frame unit through a fourth level input line and a fifth level input line, so that the grid electrode of the third transistor and the fourth transistor are in a normally-on state;
At a second moment, the third level input line is controlled to input a high level to the drain electrode of the fifth transistor, so that the fifth transistor is turned on, and the high level and the low level are alternately input to the gate electrode of the third transistor and the gate electrode of the fourth transistor by taking a frame as a unit through the fourth level input line and the fifth level input line, so that the gate electrode of the third transistor and the fourth transistor are in a normally-on state.
With reference to the scanning method according to the second aspect of the present invention, in a first possible implementation manner, the steps include:
Alternately inputting a high level and a low level to a gate of a third transistor and a gate of a fourth transistor in a frame unit through a fourth level input line and a fifth level input line, respectively, and placing the gate of the third transistor and the fourth transistor in an on state includes:
in the first frame, a high level and a low level are respectively input to a grid electrode of a third transistor and a grid electrode of a fourth transistor through a fourth level input line and a fifth level input line, so that the grid electrode of the third transistor and the fourth transistor are in a normally-on state;
in the second frame, a low level and a high level are input to the gate of the third transistor and the gate of the fourth transistor respectively through a fourth level input line and a fifth level input line, so that the gate of the third transistor and the fourth transistor are in a normally-on state.
In a third aspect, a gate scanning method, which uses the scanning circuit of the first aspect, includes:
In the normal sweeping stage:
At a first moment, a first level input line is controlled to input high level to a grid electrode of a first transistor and a grid electrode of a sixth transistor respectively, so that the first transistor and the sixth transistor are turned on, and a fourth level input line and a fifth level input line are used for inputting high level and low level to a grid electrode of a third transistor and a grid electrode of a fourth transistor respectively in a frame unit, so that the third transistor and the fourth transistor are in a normally-on state;
At a second moment, a high level is input to the drain electrode of the fifth transistor by controlling the third level input line, so that the fifth transistor is turned on, and a high level and a low level are input to the gate electrode of the third transistor and the gate electrode of the fourth transistor respectively in a frame unit through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state.
With reference to the scanning method according to the third aspect of the present invention, in a first possible implementation manner, the steps include:
Alternately inputting a high level and a low level to a gate of a third transistor and a gate of a fourth transistor in a frame unit through a fourth level input line and a fifth level input line, respectively, and placing the gate of the third transistor and the fourth transistor in an on state includes:
in the first frame, a high level and a low level are respectively input to a grid electrode of a third transistor and a grid electrode of a fourth transistor through a fourth level input line and a fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state;
In the second frame, a low level and a high level are input to the gate of the third transistor and the gate of the fourth transistor respectively through a fourth level input line and a fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state.
A fourth aspect of the present invention provides a gate scanning method, using the scanning circuit of the first aspect, comprising:
in the reverse sweep phase:
At a first moment, a second level input line is controlled to input high level to the grid electrode of the second transistor and the grid electrode of the seventh transistor respectively, so that the second transistor and the seventh transistor are turned on, and a fourth level input line and a fifth level input line are used for inputting low level and high level to the grid electrode of the third transistor and the grid electrode of the fourth transistor respectively in a frame unit, so that the third transistor and the fourth transistor are in a normally-on state;
At a second moment, a high level is input to the drain electrode of the fifth transistor by controlling the third level input line, so that the fifth transistor is turned on, and a low level and a high level are input to the gate electrode of the third transistor and the gate electrode of the fourth transistor respectively in a frame unit through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state.
With reference to the scanning method according to the fourth aspect of the present invention, in a first possible implementation manner, the steps include:
Alternately inputting a high level and a low level to a gate of a third transistor and a gate of a fourth transistor in a frame unit through a fourth level input line and a fifth level input line, respectively, and placing the gate of the third transistor and the fourth transistor in an on state includes:
in the first frame, a high level and a low level are respectively input to a grid electrode of a third transistor and a grid electrode of a fourth transistor through a fourth level input line and a fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state;
In the second frame, a low level and a high level are input to the gate of the third transistor and the gate of the fourth transistor respectively through a fourth level input line and a fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state.
By implementing the scanning circuit and the scanning method, the normally-on transistor is arranged in the scanning circuit, so that the grid electrode of the transistor at the input end only bears one row of high level, and the stress of the grid electrode of the transistor at the input end is further reduced and shared by adopting a double-deleting structure at the input end, so that the reliability and the stability of the grid scanning circuit are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a gate scan circuit according to an embodiment 1 of the present invention;
FIG. 2 is a schematic diagram of an embodiment 2 of a gate scan circuit according to the present invention;
FIG. 3 is a timing diagram of a prior art gate scan circuit;
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. Based on the embodiments of the present invention, other embodiments that may be obtained by those of ordinary skill in the art without undue burden are within the scope of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In the scanning process, the input high level of the gate driving circuit of the conventional display panel can enable the high level of the input end to bear high level stress for a long time, and finally, the transistor is disabled.
In order to solve the above problems, a gate scanning circuit and a method are provided.
1. Gate scanning circuit embodiment
Example 1 addition of two normally-on transistors between scan lines
A gate scan circuit for forming a display panel gate scan circuit by cascading, comprising:
The first level input line U2D, the second level input line D2U, the third level input line CK, the first scan line Gn-1, the second scan line, the third scan line, the fourth level input line VDD1, the fifth level input line VDD2, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the first capacitor C, and the pull-down unit.
The first level input line U2D and the second level input line D2U are connected to the gate of the first transistor T1 and the gate of the second transistor T2, respectively. The first scan line Gn-1 and the third scan line gn+1 are connected to the drain of the first transistor T1 and the source of the second transistor T2, respectively. The source of the first transistor T1 is commonly connected to the drain of the second transistor T2 to form a first common node Q.
The fourth and fifth level input lines VDD1 and VDD2 are connected to the gates of the third and fourth transistors T3 and T4, respectively. The source of the third transistor T3 and the drain of the fourth transistor T4 are connected to the first common node Q, respectively. The drain of the third transistor T3 and the source of the fourth transistor T4 are commonly connected to form a second common node P. The gate of the fifth transistor T5, the first end of the first capacitor C, and the first end of the pull-down unit are respectively connected to the second common node P. The source of the fifth transistor T5, the second terminal of the first capacitor C, and the second terminal of the pull-down unit are commonly connected to form a third common node H. The second scanning line Gn is connected to the third common node H. The third level input line CK is connected to the drain of the fifth transistor T5.
The third transistor T3 and the fourth transistor T4 are normally-on transistors.
In the normal scanning stage, since U2D is at a normal high level, and the gates of the transistors T1 are subjected to long-time high-level stress without adding normally-on transistors T3 and T4, especially in the process of performing high-low temperature reliability test, the stress is aggravated, and finally T1 failure is caused. The drain Q of T1 has two rows of high levels in one frame, referring to the level of the timing Qn of fig. 3, fig. 3 is a timing diagram of a gate scan circuit in the prior art, referring to fig. 1, fig. 1 is a diagram of a gate scan circuit embodiment 1 of the present invention, fig. 1 adds normally-on transistors T3 and T4, the P point is secondarily lifted due to the coupling effect of the CK high level and the capacitor C, the secondary lifting voltage can generally reach (VGH-VGL) 30V or more, the voltage of the P point is not transferred to the Q point by setting normally-on transistors T3 and T4, the potential of the Q point is close to the VGH potential, so that the stress on the transistors T1 and T2 is greatly reduced, and the characteristic damage of the P point high potential to T1 and T2 is avoided.
Preferably, the fourth and fifth level input lines VDD1 and VDD2 alternately input high and low levels to the third and fourth transistors T3 and T4, respectively, in units of frames.
In order to avoid that the gates of the normally-on transistors T3 and T4 bear high-level stress for a long time, the normally-on transistors T3 and T4 are alternately driven at high-level and low-level, that is, the gate of the normally-on transistor T3 is at high-level, the gate of the normally-on transistor T4 is at low-level in one frame, the gate of the next frame is at low-level, and the gate of the normally-on transistor T4 is at high-level. The normally-on transistor is arranged in the scanning circuit, so that the grid electrode of the transistor at the input end only bears one row of high level, and the reliability and the stability of the scanning circuit are improved.
Example 2 adding a transistor at the level input
Fig. 2 is a schematic diagram of an embodiment 2 of a gate scan circuit according to the present invention, in which transistors T6 and T7 are added to the level input terminal based on embodiment 1.
The scan circuit further includes a sixth transistor T6 and a seventh transistor T7, wherein the first level input line U2D is electrically connected to the gate of the first transistor T1 and the gate of the sixth transistor T6, the source of the first transistor T1 is electrically connected to the drain of the sixth transistor T6, the second level input line D2U is electrically connected to the gate of the second transistor T2 and the gate of the seventh transistor T7, the drain of the second transistor T2 is electrically connected to the source of the seventh transistor T7, and the source of the sixth transistor T6 and the drain of the seventh transistor T7 are electrically connected to the first common node Q.
Preferably, the fourth and fifth level input lines VDD1 and VDD2 alternately input high and low levels to the third and fourth transistors T3 and T4, respectively, in units of frames.
Preferably, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are normally-on transistors.
In the normal scanning, the normally open transistors T3 and T4 are added in the embodiment 1, the P point is secondarily lifted due to the coupling effect of the CK high level and the capacitor C, the secondary lifting voltage can reach (VGH-VGL) 30V or above approximately, the voltage at the P point is not transferred to the Q point by setting the normally open transistors T3 and T4, the potential at the Q point is close to the VGH potential, so that the stress on the transistors T1 and T2 is greatly reduced, in the embodiment 2, the transistors T6 and T7 are further added on the first level input line and the second level input line respectively, namely, the double-gate structure further reduces and shares the stress condition of the transistors T1 and T2, and further avoids the characteristic damage to the transistors T1 and T2 caused by the P point high potential, thereby further improving the reliability and stability of the gate driving circuit.
Preferably, the fourth and fifth level input lines VDD1 and VDD2 alternately input high and low levels to the third and fourth transistors T3 and T4, respectively, in units of frames.
In embodiment 2, in order to avoid that the gates of the normally-on transistors T3 and T4 are subjected to high-level stress for a long time, the normally-on transistors T3 and T4 are alternately driven at high level and low level, that is, the gate of the normally-on transistor T3 is at high level, the gate of the normally-on transistor T4 is at low level in one frame, the gate of the normally-on transistor T3 is at low level in the next frame, and the gate of the normally-on transistor T4 is at high level.
First Gate scanning method embodiment
A scan circuit in an embodiment employing a gate scan circuit, comprising the steps of:
In the normal sweeping stage:
at the first time, the first level input line U2D is controlled to input a high level to the gate of the first transistor T1, the first transistor T1 is turned on, and the high level and the low level are alternately input to the gate of the third transistor T3 and the gate of the fourth transistor T4 in frame units through the fourth level input line VDD1 and the fifth level input line VDD2, respectively, so that the gate of the third transistor T3 and the fourth transistor T4 are in a normally-on state.
At the second time, the third level input line CK is controlled to input a high level to the drain of the fifth transistor T5, the fifth transistor T5 is turned on, and a high level and a low level are alternately input to the gate of the third transistor T3 and the gate of the fourth transistor T4 in frame units through the fourth level input line VDD1 and the fifth level input line VDD2, respectively, so that the gate of the third transistor T3 and the fourth transistor T4 are in a normally-on state.
Through making normally open transistor T3 and T4 be in normally open state for P point voltage can not transmit to the Q point, and the potential of Q point is close VGH potential, has obtained very big reduction to transistor T1 and T2's stress like this, avoids P point high potential to cause the characteristic damage to T1 and T2, has improved scanning circuit's stability.
Preferably, in order to avoid that the gates of the normally-on transistors T3 and T4 are subjected to high-level stress for a long time, the normally-on transistors T3 and T4 are alternately high-level and low-level driven, and in particular,
In the first frame, a high level and a low level are input to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the fourth level input line VDD1 and the fifth level input line VDD2, respectively, so that the gate of the third transistor T3 and the fourth transistor T4 are in a normally-on state;
In the second frame, the low level and the high level are input to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the fourth level input line VDD1 and the fifth level input line VDD2, respectively, and the gate of the third transistor T3 and the fourth transistor T4 are turned on.
That is, the normally-on transistors T3 and T4 are alternately inputted with high and low levels between the first frame, which may be the previous frame, and the second frame, which may be the next frame.
In a second gate scanning method embodiment, a scanning circuit in a scanning circuit scheme is used, and the scanning circuit includes:
In the normal sweeping stage:
At the first time, the first level input line U2D is controlled to input a high level to the gate of the first transistor T1 and the gate of the sixth transistor T6, respectively, to turn on the first transistor T1 and the sixth transistor T6, and to input a high level and a low level to the gate of the third transistor T3 and the gate of the fourth transistor T4 in frame units through the fourth level input line VDD1 and the fifth level input line VDD2, respectively, to turn on the third transistor T3 and the fourth transistor T4.
At the second time, the third level input line CK is controlled to input a high level to the drain of the fifth transistor T5, the fifth transistor T5 is turned on, and the high level and the low level are input to the gate of the third transistor T3 and the gate of the fourth transistor T4 in frame units through the fourth level input line VDD1 and the fifth level input line VDD2, respectively, so that the third transistor T3 and the fourth transistor T4 are in a normally-on state.
Preferably, in order to avoid that the gates of the normally-on transistors T3 and T4 are subjected to high-level stress for a long time, the normally-on transistors T3 and T4 are alternately high-level and low-level driven, and in particular,
In the first frame, a high level and a low level are input to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the fourth level input line VDD1 and the fifth level input line VDD2, respectively, so that the gate of the third transistor T3 and the fourth transistor T4 are in a normally-on state;
In the second frame, the low level and the high level are input to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the fourth level input line VDD1 and the fifth level input line VDD2, respectively, and the gate of the third transistor T3 and the fourth transistor T4 are turned on.
That is, the normally-on transistors T3 and T4 are alternately inputted with high and low levels between the first frame, which may be the previous frame, and the second frame, which may be the next frame.
A third gate scanning method embodiment, which employs a scanning circuit in a scanning circuit embodiment, includes:
in the reverse sweep phase:
at the first moment, the second level input line D2U is controlled to input high level to the grid electrode of the second transistor T and the grid electrode of the seventh transistor T respectively, so that the second transistor T and the seventh transistor T are turned on, and low level and high level are input to the grid electrode of the third transistor T and the grid electrode of the fourth transistor T respectively in a frame unit through the fourth level input line VDD1 and the fifth level input line VDD2, so that the third transistor T and the fourth transistor T are in a normally-on state;
At the second time, the third level input line CK is controlled to input a high level to the drain of the fifth transistor T, the fifth transistor T is turned on, and the low level and the high level are input to the gate of the third transistor T and the gate of the fourth transistor T in frame units through the fourth level input line VDD1 and the fifth level input line VDD2, respectively, so that the third transistor T and the fourth transistor T are in a normally-on state.
Preferably, in order to avoid that the gates of the normally-on transistors T3 and T4 are subjected to high-level stress for a long time, the normally-on transistors T3 and T4 are alternately high-level and low-level driven, and in particular,
In the first frame, a high level and a low level are input to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the fourth level input line VDD1 and the fifth level input line VDD2, respectively, so that the gate of the third transistor T3 and the fourth transistor T4 are in a normally-on state;
In the second frame, the low level and the high level are input to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the fourth level input line VDD1 and the fifth level input line VDD2, respectively, and the gate of the third transistor T3 and the fourth transistor T4 are turned on.
That is, the normally-on transistors T3 and T4 are alternately inputted with high and low levels between the first frame, which may be the previous frame, and the second frame, which may be the next frame.
By implementing the scanning circuit and the scanning method, the normally-on transistor is arranged in the scanning circuit, so that the grid electrode of the transistor at the input end only bears one row of high level, and the stress of the grid electrode of the transistor at the input end is further reduced and shared by adopting a double-deleting structure at the input end, so that the reliability and the stability of the grid scanning circuit are improved.
The foregoing is only illustrative of the present invention and is not to be construed as limiting thereof, but rather as various modifications, equivalent arrangements, improvements, etc., within the spirit and principles of the present invention.
Claims (10)
1. A gate scanning circuit for forming a display panel gate scanning circuit by cascading, comprising:
a first level input line, a second level input line, a third level input line, a first scan line, a second scan line, a third scan line, a fourth level input line, a fifth level input line, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, and a pull-down unit;
the first level input line and the second level input line are respectively connected with the grid electrode of the first transistor and the grid electrode of the second transistor;
the first scanning line and the third scanning line are respectively connected with the drain electrode of the first transistor and the source electrode of the second transistor;
the source electrode of the first transistor is commonly connected with the drain electrode of the second transistor to form a first common joint;
The fourth level input line and the fifth level input line are respectively connected with the grid electrode of the third transistor and the grid electrode of the fourth transistor;
The source electrode of the third transistor and the drain electrode of the fourth transistor are respectively connected with the first common junction;
The drain electrode of the third transistor and the source electrode of the fourth transistor are connected together to form a second common joint;
the grid electrode of the fifth transistor, the first end of the first capacitor and the first end of the pull-down unit are respectively connected with the second common contact point;
the source electrode of the fifth transistor, the second end of the first capacitor and the second end of the pull-down unit are connected together to form a third common joint;
the second scanning line is connected with the third common joint;
The third level input line is connected with the drain electrode of the fifth transistor;
And the third transistor and the fourth transistor are driven in an alternating high level and low level mode, so that the voltage of the second common junction cannot be transmitted to the first common junction, the potential of the first common junction is close to VGH potential, the stress on the first transistor and the second transistor is reduced, and the characteristic damage of the high potential of the second common junction to the first transistor and the second transistor is avoided.
2. The gate scan circuit of claim 1, wherein the scan circuit further comprises:
A sixth transistor;
A seventh transistor;
The first level input line is electrically connected with the grid electrode of the first transistor and the grid electrode of the sixth transistor respectively, and the source electrode of the first transistor is electrically connected with the drain electrode of the sixth transistor;
the second level input line is electrically connected with the grid electrode of the second transistor and the grid electrode of the seventh transistor respectively, and the drain electrode of the second transistor is electrically connected with the source electrode of the seventh transistor;
The source electrode of the sixth transistor and the drain electrode of the seventh transistor are respectively and electrically connected with the first common connection point.
3. The gate scanning circuit according to claim 2, wherein the fourth level input line and the fifth level input line alternately input a high level and a low level to the third transistor and the fourth transistor, respectively, in a frame unit.
4. A gate scan circuit according to claim 3, wherein the third and fourth transistors are normally-on transistors.
5. A gate scanning method using the scanning circuit of any one of claims 1 to 4, comprising:
In the normal sweeping stage:
At a first moment, a first level input line is controlled to input a high level to the grid electrode of the first transistor, so that the first transistor is turned on, and a high level and a low level are alternately input to the grid electrode of the third transistor and the grid electrode of the fourth transistor respectively in a frame unit through a fourth level input line and a fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state;
and at a second moment, controlling a third level input line to input a high level to the drain electrode of the fifth transistor, so that the fifth transistor is turned on, and alternately inputting a high level and a low level to the gate electrode of the third transistor and the gate electrode of the fourth transistor by taking a frame as a unit through a fourth level input line and a fifth level input line respectively so that the third transistor and the fourth transistor are in a normally-on state.
6. The gate scanning method according to claim 5, characterized in that said steps of:
Alternately inputting a high level and a low level to a gate of a third transistor and a gate of a fourth transistor in units of frames through a fourth level input line and a fifth level input line, respectively, and placing the third transistor and the fourth transistor in an on state includes:
in the first frame, a high level and a low level are respectively input to a grid electrode of a third transistor and a grid electrode of a fourth transistor through a fourth level input line and a fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state;
In the second frame, a low level and a high level are input to the gate of the third transistor and the gate of the fourth transistor respectively through a fourth level input line and a fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state.
7. A gate scanning method using the scanning circuit of any one of claims 1 to 4, comprising:
In the normal sweeping stage:
At a first moment, a first level input line is controlled to input high level to a grid electrode of a first transistor and a grid electrode of a sixth transistor respectively, so that the first transistor and the sixth transistor are turned on, and a fourth level input line and a fifth level input line are used for inputting high level and low level to a grid electrode of a third transistor and a grid electrode of a fourth transistor respectively in a frame unit, so that the third transistor and the fourth transistor are in a normally-on state;
At a second moment, a high level is input to the drain electrode of the fifth transistor by controlling the third level input line, so that the fifth transistor is turned on, and a high level and a low level are input to the gate electrode of the third transistor and the gate electrode of the fourth transistor respectively in a frame unit through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state.
8. The gate scanning method according to claim 7, characterized in that said steps of:
Alternately inputting a high level and a low level to a gate of a third transistor and a gate of a fourth transistor in units of frames through a fourth level input line and a fifth level input line, respectively, and placing the third transistor and the fourth transistor in an on state includes:
in the first frame, a high level and a low level are respectively input to a grid electrode of a third transistor and a grid electrode of a fourth transistor through a fourth level input line and a fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state;
In the second frame, a low level and a high level are input to the gate of the third transistor and the gate of the fourth transistor respectively through a fourth level input line and a fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state.
9. A gate scanning method using the scanning circuit of any one of claims 1 to 4, comprising:
in the reverse sweep phase:
At a first moment, a second level input line is controlled to input high level to the grid electrode of the second transistor and the grid electrode of the seventh transistor respectively, so that the second transistor and the seventh transistor are turned on, and a fourth level input line and a fifth level input line are used for inputting low level and high level to the grid electrode of the third transistor and the grid electrode of the fourth transistor respectively in a frame unit, so that the third transistor and the fourth transistor are in a normally-on state;
At a second moment, a high level is input to the drain electrode of the fifth transistor by controlling the third level input line, so that the fifth transistor is turned on, and a low level and a high level are input to the gate electrode of the third transistor and the gate electrode of the fourth transistor respectively in a frame unit through the fourth level input line and the fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state.
10. The gate scanning method according to claim 9, characterized in that said steps of:
Alternately inputting a high level and a low level to a gate of a third transistor and a gate of a fourth transistor in units of frames through a fourth level input line and a fifth level input line, respectively, and placing the third transistor and the fourth transistor in an on state includes:
in the first frame, a high level and a low level are respectively input to a grid electrode of a third transistor and a grid electrode of a fourth transistor through a fourth level input line and a fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state;
In the second frame, a low level and a high level are input to the gate of the third transistor and the gate of the fourth transistor respectively through a fourth level input line and a fifth level input line, so that the third transistor and the fourth transistor are in a normally-on state.
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| CN105788553B (en) * | 2016-05-18 | 2017-11-17 | 武汉华星光电技术有限公司 | GOA circuits based on LTPS semiconductor thin-film transistors |
| CN107845403B (en) * | 2017-11-07 | 2021-04-23 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN108281124B (en) * | 2018-03-30 | 2020-11-24 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN108648705B (en) * | 2018-03-30 | 2020-03-27 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| WO2020140292A1 (en) * | 2019-01-04 | 2020-07-09 | 京东方科技集团股份有限公司 | Shift register unit and driving method, gate drive circuit and display device |
| US11232734B2 (en) * | 2019-09-25 | 2022-01-25 | Boe Technology Group Co., Ltd. | Shift register unit, driving method, gate driving circuit and display device |
| CN112259038B (en) * | 2020-11-16 | 2023-07-14 | 武汉天马微电子有限公司 | Shift register and driving method, grid driving circuit, display panel and device |
| CN113257168B (en) * | 2021-05-18 | 2022-07-12 | 武汉华星光电技术有限公司 | Grid driving circuit and display panel |
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| CN105469760A (en) * | 2015-12-17 | 2016-04-06 | 武汉华星光电技术有限公司 | GOA circuit based on LTPS semiconductor film transistor |
| CN108597454A (en) * | 2018-05-09 | 2018-09-28 | 上海天马有机发光显示技术有限公司 | A kind of shift register and its driving method, scan drive circuit and display device |
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