CN115377071A - Chip and method for fully wrapping and isolating signal line and chip manufacturing method - Google Patents

Abstract

A chip, a method and a chip manufacturing method for full-wrapping isolation of signal lines are provided, wherein the chip 100 comprises at least three metal layers which are arranged in a stacked mode, and a plurality of functional through holes which are arranged in corresponding positions of the at least three metal layers; the classified signal line clusters are arranged in the middle metal layer, isolation is achieved based on the isolation layer and other signal lines in the chip, the noisy, common and sensitive signal line clusters are arranged at different positions in the chip respectively, the metal lines with high levels are wrapped outside the noisy signal lines, the metal lines with zero levels are wrapped outside the sensitive signal lines, isolation arrangement of the noisy, common and sensitive signal line clusters is achieved, and isolation of the noisy signals and protection of the sensitive signals are achieved.

Description

Chip, method and chip manufacturing method for signal line fully wrapped isolation

technical field

The present invention relates to the field of integrated circuits and chip manufacturing, and more specifically, to a chip, a method and a chip manufacturing method in which signal lines are completely wrapped and isolated.

Background technique

In the prior art, since different signal lines in the analog chip have different signal transmission functions, the signals transmitted in some signal lines are relatively noisy, which causes serious electromagnetic interference to other signal lines with relatively short distances around them. Thereby affecting the transmission quality of signals in other signal lines, and further affecting the performance of the analog chip.

Specifically, according to the different functions of different signal lines in an analog chip, they can be classified into noisy signal lines and relatively sensitive signal lines. Among them, the relatively noisy signal lines have larger signal amplitudes or frequent signal actions and more amplitude changes, which are likely to cause interference to other adjacent signal lines. The signals transmitted in the more sensitive signal lines are usually required to be more precise, because their slight changes may have a greater impact on the performance of the chip, and it is easy to cause signal transmission errors after being interfered, so such signal lines should try to avoid external interference. Factor interference, and ensure that its signal value tends to remain unchanged during the transmission process.

At present, in the process of layout of integrated circuits, noisy signal lines and sensitive signal lines are usually arranged at positions with a certain interval, so as to prevent interference. Nevertheless, with the improvement of chip manufacturing size and circuit complexity, the use of this method in the prior art will increase the complexity of the integrated circuit, increase the length of the circuit, the area of the chip cannot be further reduced, and the degree of integration of the chip will be reduced. .

Therefore, there is an urgent need for a new method of isolating sensitive signal lines in the chip to prevent interference from noisy signals.

Contents of the invention

In order to solve the deficiencies in the prior art, the purpose of the present invention is to provide a chip, method and chip manufacturing method in which signal wires are completely wrapped and isolated, by arranging noisy, common and sensitive signal wire clusters in different position, and wrap high-level metal wires around noisy signal lines, and wrap zero-level metal wires around sensitive signal lines, thereby realizing the isolation of noisy signals and the protection of sensitive signals.

The present invention adopts the following technical solutions.

The first aspect of the present invention relates to a fully-wrapped and isolated chip for signal lines, wherein the chip 100 includes at least three metal layers stacked, and a plurality of functional through holes arranged at corresponding positions in the at least three metal layers ; Wherein, the classified signal line cluster is arranged in the middle metal layer, and is isolated from other signal lines in the chip based on the isolation layer.

Preferably, the isolation layer includes the metal layers on both sides of the area where the classified signal line clusters are located in the middle metal layer, the area where the classified signal line clusters are located and the upper metal layer areas corresponding to the areas on both sides, the area where the classified signal line clusters are located and the areas on both sides correspond to The lower metal layer area; wherein, each metal layer area inside the isolation layer is not connected to other metal layer areas outside the isolation layer; and each metal layer area inside the isolation layer is connected to each other through signal lines to classify signal lines Clusters are isolated.

Preferably, the signal line clusters are classified into noisy signal lines 101 , common signal lines 102 and sensitive signal lines 103 .

Preferably, the metal layer regions in the isolation layer are connected by signal wires and metal wires to realize connection of different metal layers based on multiple functional through holes 204 and 205 at corresponding positions in at least three metal layers.

Preferably, the cluster of noisy signal lines is isolated after being connected to the power supply potential by the metal lines 104 and 106 located in the isolation layer corresponding to the cluster of noisy signal lines.

Preferably, the cluster of sensitive signal lines is isolated after being connected to the ground potential by the metal line 105 located in the isolation layer corresponding to the cluster of sensitive signal lines.

Preferably, the noisy signal line cluster and its isolation layer are located at one end of the chip, the sensitive signal line cluster and its isolation layer are located at the other end of the chip, and the common signal line cluster is located in the middle of the chip to realize the separation between the noisy signal line cluster and the sensitive signal line cluster. isolation between.

Preferably, a plurality of first functional through holes 204 are arranged between the upper metal layer 201 and the middle metal layer 202, and a plurality of second functional through holes 205 are arranged between the middle metal layer 202 and the lower metal layer 203; and , the metal lines in the upper metal layer 201 in the isolation layer are connected to the metal lines in the middle metal layer 202 on both sides of the area where the classification signal line cluster is located through the first functional through hole 204; the isolation layer is located in the classification signal line The metal lines on both sides of the area where the clusters are located are connected to the metal lines located in the area where the classification signal line clusters are located and the areas on both sides in the lower metal layer 203 through the second functional through hole 205 .

The second aspect of the present invention relates to a method for fully wrapping and isolating signal lines, wherein the method is implemented by using a chip for fully wrapping and isolating signal lines as described in the first aspect of the present invention.

The third aspect of the present invention relates to a chip manufacturing method in which signal lines are fully wrapped and isolated, wherein the chip manufacturing method adopts the chip wiring method in a chip with signal lines fully wrapped and isolated as described in the first aspect of the present invention, To realize the manufacture of the chip.

The beneficial effect of the present invention is that, compared with the prior art, a chip, method and chip manufacturing method in which signal lines are completely wrapped and isolated in the present invention can arrange noisy, common and sensitive signal line clusters in different parts of the chip respectively. Position, and wrap high-level metal wires around noisy signal lines, and wrap zero-level metal wires around sensitive signal lines to achieve isolation of noisy signals and protection of sensitive signals.

The beneficial effects of the present invention also include:

1. Isolating noisy signals through full wrapping can make the external circuit have better anti-noise ability; isolating sensitive signals through full wrapping can realize all-round protection for sensitive signals to prevent noise interference;

2. Since the isolation layer is set outside the sensitive signal line and the noisy signal line, the isolation distance between the sensitive signal line and the noisy signal line can be reduced to a large extent, and the same isolation effect can be achieved, reducing the effective circuit The length of the circuit supports a smaller chip area and improves the integration of the circuit;

3. The method for isolating noisy signal lines and sensitive signal lines in the present invention has a simple structure, is easy to implement, can support various types of chips, and circuit types commonly present in the prior art, and can be widely used.

Description of drawings

Fig. 1 is a schematic diagram of the arrangement of signal lines in a chip in which signal lines are fully wrapped and isolated in the present invention;

FIG. 2 is a schematic diagram of connection modes of different metal layers in a chip in which signal lines are fully wrapped and isolated according to the present invention.

Reference signs:

100-chip,

101-noisy signal line,

102-sensitive signal line,

103-Common signal line,

104 - metal wires connected to the power supply potential,

105 - metal wire connected to ground potential,

106 - metal wire,

201 - upper metal layer,

202 - middle metal layer,

203 - lower metal layer,

204 - first functional through hole,

205 - Second functional via.

Detailed ways

The application will be further described below in conjunction with the accompanying drawings. The following examples are only used to illustrate the technical solutions of the present invention more clearly, but not to limit the protection scope of the present application.

FIG. 1 is a schematic diagram of the arrangement of signal lines in a chip in which the signal lines are fully wrapped and isolated in the present invention. FIG. 2 is a schematic diagram of connection modes of different metal layers in a chip in which signal lines are fully wrapped and isolated according to the present invention. As shown in Figures 1-2, the first aspect of the present invention relates to a chip 100 with signal wires fully wrapped and isolated, wherein the chip 100 includes at least three metal layers stacked, and corresponding A plurality of functional through holes on the position; wherein, the group of classified signal lines is arranged in the middle metal layer, and is isolated from other signal lines in the chip based on the isolation layer.

Specifically, in an integrated circuit chip, the design layout in the integrated circuit can be realized by various material layers formed on a semiconductor substrate, such as a silicon wafer. Various material layers on the semiconductor substrate can be formed of various metals, metal oxides, and semiconductor thin layers. Individual portions of the thin layers formed of different materials may be used to implement eg gate electrodes, source and drain regions, metal lines or vias for metal interconnects, openings for solder pads, and the like.

It can be understood that various passive and active microelectronic devices may be included on the substrate, such as resistors, capacitors, inductors, diodes, various types of field effect transistors, various types of transistors or a combination of elements, and the like. In order to connect various components into the circuit in a suitable way, and to further reduce the area of the chip, in the prior art, a multi-layer metal layer is usually arranged on the substrate to realize wire connection to multiple different components. the wiring method. For example, in the patent application document with the publication number CN112558407A, a method of manufacturing a semiconductor device is disclosed, which discloses that the layout after routing includes interconnection structures, and the interconnection structures include first, second, third, etc. Technical scheme of the metal layer.

On the basis of the existing technology, the technical solution in the present invention places different types of signal line clusters on different positions of multiple metal layers, and realizes a comprehensive wrapping of the top, bottom, left, and right outside of them, thereby achieving a good signal isolation.

Wherein, the plurality of metal layers can be at least three layers, and the number of metal layers can be appropriately increased according to the actual wiring mode of the integrated circuit in the chip and the range permitted by the chip manufacturing process. Correspondingly, the classified signal line clusters can be disposed in one or more intermediate metal layers except the uppermost and lowermost metal layers among the plurality of metal layers. Since the outside of the classification signal line cluster needs to be wrapped with an isolation layer, at least one upper metal layer and one lower metal layer need to be reserved for isolation.

Similarly, on the left and right sides of the classified signal line clusters, functional through holes of the metal layer may be provided, and the metal layer at the corresponding position of the functional through holes may be reserved for isolation.

Preferably, the isolation layer includes metal layer areas 202 on both sides of the metal layer where the classified signal line clusters are located in the middle metal layer, the area where the classified signal line clusters are located and the upper metal layer area 104 or 105 corresponding to the two sides areas, and where the classified signal line clusters are located. region and the lower layer metal layer regions 106 corresponding to the regions on both sides; each metal layer region in the isolation layer is not connected to other metal layer regions in the non-isolation layer part of the chip, and each metal layer region in the isolation layer is connected to each other to classify The cluster of signal lines realizes isolation; wherein, each metal layer area is each metal line used to realize the connection of internal components inside the chip.

It can be understood that, according to the specific position of the classified signal line cluster, the adjacent metal lines up, down, left, and right are selected, and these metal lines are connected to each other to form an isolation layer. As shown in FIG. 1 , the isolation layer includes the metal layer areas on both sides of the layer where the classified signal line clusters are located, as well as the uppermost metal layer and the lowermost metal layer in the above-mentioned area. Through such a setting method, all-round wrapping and isolation of signal lines can be achieved, thereby effectively preventing mutual interference between signals. Compared with the isolation method commonly used in the prior art, the effect of the method in the present invention is more prominent.

Preferably, the classification methods of the classified signal line clusters are noisy signal lines 101, common signal lines 103, and sensitive signal lines 102; wherein, the noisy signal lines 101 at least include signal lines for connecting high-power devices that perform chip functions; sensitive The signal lines 102 include at least signal lines used to connect the control circuits required to perform chip functions, and the common signal lines 103 are other signal lines in the chip except the noisy signal line 101 and the sensitive signal line 102 .

Specifically, the specific classification method of the signal line can be set according to the function of the chip, the principle of the circuit, the characteristics of the signal transmitted in the signal line, and the like. For example, a signal line used to transmit a signal with a relatively large amplitude can be classified as a noisy signal line, while a signal line carrying a signal with a small amplitude that is easily disturbed and seriously affects the function of the chip can be classified as For sensitive signal lines. In one embodiment, high-power input and output signals used as high-power devices, or signals such as the conduction voltage and current of MOS tubes, transistors and other devices can be classified into noisy signals, and the signal lines carrying the signals can also be are accordingly classified as noisy signal lines. In another embodiment, signals used as auxiliary functions of the above-mentioned high-power devices, such as some commonly used control signals, etc., may be classified as sensitive signals. In the chip circuit layout design, the signal lines can be classified according to the above content. To sum up, there is no fixed or completely clear definition of noisy signal lines and sensitive signal lines in the prior art or in this application. The method for classifying signal lines in this application may be defined according to specific chips that need to be isolated.

Preferably, the metal layer regions in the isolation layer are connected by signal wires and metal wires 106 to realize connection of different metal layer regions based on multiple functional via holes 204 and 205 at corresponding positions in at least three metal layers.

Specifically, each metal layer region represents a metal line preset inside the chip, such as the metal lines 201 , 202 and 203 described in FIG. 2 . Since the area where these metal lines are located is adjacent to the upper, lower, left, and right sides of the noisy signal line, it is used as an isolation layer. In order to achieve the isolation effect, these metal lines should be connected end to end, and an appropriate potential should be applied to them to isolate the noisy signal lines located inside them. Since each metal layer area, that is, each metal wire is located in a different layer, so to realize the connection of the metal wires in different layers, it needs to be based on a plurality of functional through holes 204 and 205 .

Preferably, the noisy signal line clusters are isolated after being connected to the power potential bus by the metal line regions 104 and 106 located in the isolation layer corresponding to the noisy signal line clusters.

Specifically, for noisy signal lines, because the signal carried inside the noisy signal line is generally of high power, the signal changes frequently, and the amplitude change may also be large, so it is necessary to use a metal line with a high internal voltage for isolation. This is because when the metal wire has a stable high voltage inside, the high voltage will shield most of the electromagnetic interference caused by the noisy signal, and it is relatively less affected by the noisy signal. Therefore, the signal lines outside the high-voltage isolation layer are basically not or less affected by noisy signal lines.

Preferably, the cluster of sensitive signal lines is isolated after being connected to the ground potential by the metal line 105 located in the isolation layer corresponding to the cluster of sensitive signal lines.

Specifically, since the sensitive signal line cluster carries a small signal therein, it will not have too much externally radiated interference. On the contrary, such signal lines are susceptible to external interference. According to this feature, its isolation layer can be connected to a clean ground to achieve isolation. Specifically, within a chip, for reasons such as easier and more standardized implementation of wiring, multiple power supply potential buses and multiple ground potential buses may be included.

Preferably, the noisy signal line cluster and its isolation layer are located at one end of the chip, the sensitive signal line cluster and its isolation layer are located at the other end of the chip, and the common signal line cluster is located in the middle of the chip to realize the separation between the noisy signal line cluster and the sensitive signal line cluster. isolation between.

Since the noisy signal line and the sensitive signal line already have a fully-wrapped isolation layer, there is no need to set a redundant isolation layer outside the common signal line.

Preferably, a plurality of first functional through holes 204 are arranged between the upper metal layer 201 and the middle metal layer 202, and a plurality of second functional through holes 205 are arranged between the middle metal layer 202 and the lower metal layer 203; and , the metal lines in the upper metal layer 201 in the isolation layer are connected to the metal lines in the middle metal layer 202 on both sides of the area where the classification signal line cluster is located through the first functional through hole 204; the isolation layer is located in the classification signal line The metal lines on both sides of the area where the clusters are located are connected to the metal lines located in the area where the classification signal line clusters are located and the areas on both sides in the lower metal layer 203 through the second functional through hole 205 .

Specifically, there is no difference between the functional through holes described in the present invention and the functional through holes between multiple metal layers commonly used in the prior art, and they are all used to realize metal lines in multiple different metal layers. connected.

The second aspect of the present invention relates to a method for fully wrapping and isolating signal lines, wherein the method is implemented by using a chip for fully wrapping and isolating signal lines as described in the first aspect of the present invention.

The third aspect of the present invention relates to a chip manufacturing method in which signal lines are fully wrapped and isolated, wherein the chip manufacturing method adopts the chip wiring method in a chip with signal lines fully wrapped and isolated as described in the first aspect of the present invention, In order to realize the manufacture of the chip.

The beneficial effect of the present invention is that, compared with the prior art, a chip, method and chip manufacturing method in which signal lines are completely wrapped and isolated in the present invention can arrange noisy, common and sensitive signal line clusters in different parts of the chip respectively. Position, and wrap high-level metal wires around noisy signal lines, and wrap zero-level metal wires around sensitive signal lines to achieve isolation of noisy signals and protection of sensitive signals.

The applicant of the present invention has made a detailed description and description of the implementation examples of the present invention in conjunction with the accompanying drawings, but those skilled in the art should understand that the above implementation examples are only preferred implementations of the present invention, and the detailed description is only to help readers better To understand the spirit of the present invention rather than limit the protection scope of the present invention, on the contrary, any improvement or modification made based on the spirit of the present invention shall fall within the protection scope of the present invention.

Claims (10)

1. A chip with signal line fully wrapped and isolated, characterized in that: The chip (100) includes at least three metal layers stacked in layers, and a plurality of functional through holes arranged at corresponding positions in the at least three metal layers; Wherein, the classified signal line cluster is arranged in the middle metal layer, and is isolated from other signal lines in the chip based on the isolation layer. 2. A chip with signal lines fully wrapped and isolated according to claim 1, characterized in that: The isolation layer includes the metal layer areas on both sides of the metal layer where the classified signal line clusters are located in the middle metal layer, the area where the classified signal line clusters are located and the upper metal layer areas corresponding to the areas on both sides, the area where the classified signal line clusters are located, and the areas on both sides the corresponding lower metal layer area; Each metal layer area in the isolation layer is not in communication with other metal layer areas in the non-isolation layer part of the chip, and each metal layer area in the isolation layer is connected to each other, so as to isolate the classified signal line cluster ; Wherein, each of the metal layer regions is each of the metal lines inside the chip for realizing the connection of internal components. 3. A chip with signal lines fully wrapped and isolated according to claim 2, characterized in that: The classification methods of the classified signal line clusters are noisy signal lines (101), common signal lines (103) and sensitive signal lines (102); wherein, The noisy signal lines (101) at least include signal lines for connecting high-power devices that perform chip functions; The sensitive signal line (102) at least includes a signal line for connecting to a control circuit required to perform chip functions, The common signal line (103) is other signal lines in the chip except the noisy signal line (101) and the sensitive signal line (102). 4. A signal line fully wrapped and isolated chip according to claim 3, characterized in that: The metal layer regions in the isolation layer are connected by signal wires and metal wires to realize the connection of different metal layer regions based on multiple functional through holes (204, 205) at corresponding positions in the at least three metal layers . 5. A signal line fully wrapped and isolated chip according to claim 4, characterized in that: The noisy signal line clusters are isolated after being connected to a power supply potential bus by metal layer regions (104, 106) located in the isolation layer corresponding to the noisy signal line clusters. 6. A signal line fully wrapped and isolated chip according to claim 4, characterized in that: The clusters of sensitive signal lines are isolated after being connected to a ground potential bus by metal layer regions (105, 106) in the isolation layer corresponding to the clusters of sensitive signal lines. 7. A signal line fully-wrapped and isolated chip according to claim 3, characterized in that: The noisy signal line cluster and its isolation layer are located at one end of the chip, the sensitive signal line cluster and its isolation layer are located at the other end of the chip, and the normal signal line cluster is located in the middle of the chip to achieve the The isolation between the noisy signal line cluster and the sensitive signal line cluster. 8. A signal line fully-wrapped and isolated chip according to claim 1, characterized in that: A plurality of first functional through holes (204) are arranged between the upper metal layer (201) and the middle metal layer (202), and a plurality of first functional through holes (204) are arranged between the middle metal layer (202) and the lower metal layer (203). a plurality of second functional vias (205); and, The metal wires in the upper metal layer (201) in the isolation layer pass through the first functional through hole (204) and the two metal wires in the middle metal layer (202) in the area where the classified signal wire clusters are located. Side metal wire connection; The metal wires on both sides of the area where the classified signal line clusters are located in the isolation layer pass through the second functional through hole (205) and the metal line located in the area where the classified signal line clusters are located in the lower metal layer (203). And the metal wire connection on both sides of the area. 9. A method for fully wrapping and isolating signal lines, characterized in that: The method is realized by using a chip with signal lines fully wrapped and isolated as described in claims 1-8. 10. A chip manufacturing method for fully wrapping and isolating signal lines, characterized in that, The chip manufacturing method adopts a chip wiring method in a chip with signal wires fully wrapped and isolated as described in claims 1-8, so as to realize the manufacturing of the chip.

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