CN115376918A - A kind of IGBT device and its manufacturing method - Google Patents

Abstract

An IGBT device and its manufacturing method, the manufacturing method comprising: providing a substrate; forming a first conductivity type region on the front surface of the substrate, or forming a first conductivity type region and a second conductivity type region on the front surface of the substrate ; Forming a first trench on the substrate; forming a trench gate on the first trench, during the formation of the trench gate, the part of the first conductivity type region in contact with the thick gate dielectric layer forms an extraction channel; The front side of the substrate is doped to form a base region; the emitter region is formed on the base region; the first electrode is formed on the front side of the substrate, and the first electrode is electrically connected to the extraction channel, the base region, and the emitter region; A collector region, or a buffer layer and a collector region are formed on the back of the substrate; a second electrode is formed on the collector region. The application can reduce the lateral size of the IGBT device, improve the current capability of the device, and ensure that the minority carrier can be extracted in the off state.

Description

A kind of IGBT device and its manufacturing method

technical field

The invention relates to the technical field of semiconductor devices, in particular to an IGBT device and a manufacturing method thereof.

Background technique

In IGBT devices, in order to improve the function or performance of the device, it is often necessary to use more than two kinds of gates. In addition to conventional gates, shielded gates, floating gates, etc. are also set. For example, in the existing patent CN202210453957.6, two kinds of gates are used, one gate is used to turn on the device in the on state, and the other gate is used to extract minority carriers in the off state.

In this existing patent, the size of the cell is relatively large. On the one hand, two types of trench gates are required, and on the other hand, the deep base region needs to be diffused laterally to a certain distance, and a certain distance needs to be kept between the two trench gates. , to ensure that the deep base region does not completely surround the bottom of the trench gate or that the deep base region cannot protect the weak position where the electric field concentration at the corner of the trench gate is concentrated (prone to breakdown).

It can be seen that the lateral size of the cells in this prior patent is large, and in the same chip size, the number of cells is small and the current capability is small.

Contents of the invention

The technical problem mainly solved by the invention is the technical problem that the cell lateral size of the existing IGBT device is large and the current capacity is small.

According to the first aspect, a method for manufacturing an IGBT device is provided in an embodiment, including:

providing a substrate, the substrate serves as part or all of the drift region of the IGBT device, and the substrate has a second conductivity type;

forming a region of the first conductivity type on the front surface of the substrate, or forming a region of the first conductivity type and a region of the second conductivity type on the front surface of the substrate;

forming a first trench on the substrate, the first trench piercing through a part of the first conductivity type region;

A trench gate is formed on the first trench, and the trench gate includes a gate and a gate dielectric layer surrounding the gate; the gate dielectric layer includes thick gate dielectric layers and thin gate dielectric layers on both sides of the gate respectively formed, and the thick gate The thickness of the dielectric layer is greater than the thickness of the thin gate dielectric layer; the thick gate dielectric layer is located on the side close to the first conductivity type region and is in contact with the first conductivity type region; wherein, in the process of forming the trench gate, the first conductivity type The portion of the region in contact with the thick gate dielectric layer forms an extraction channel;

Doping the front side of the substrate to form a base region, the base region has the first conductivity type, and the bottom of the base region is higher than the bottom of the trench gate;

Forming an emitter region on the base region, the emitter region has a second conductivity type; the emitter region is located on one side of the thin gate dielectric layer of the trench gate and is in contact with the thin gate dielectric layer;

A first electrode is formed on the front side of the substrate, and the first electrode is electrically connected to the extraction channel, the base area, and the emitter area; the extraction channel is used to extract the bottom of the trench gate through the extraction channel when the IGBT device is in the off state of minority carriers;

Form a collector region on the back of the substrate, or form a buffer layer and a collector region on the back of the substrate; form a second electrode on the collector region, the second electrode is electrically connected to the collector region, and the buffer layer has a second conductive type, the collector region has a first conductivity type, and the first conductivity type and the second conductivity type belong to different semiconductor conductivity types.

In one embodiment, forming a trench gate on the first trench includes:

A silicon dioxide layer with a first thickness is grown on the first trench by thermal oxidation as a thick gate dielectric layer. During the formation of the thick gate dielectric layer, an extraction channel is formed on one side of the trench gate;

removing the thick gate dielectric layer on the sidewall of the first trench away from the first conductivity type region;

A silicon dioxide layer with a second thickness is grown on the first trench by thermal oxidation as a thin gate dielectric layer.

In one embodiment, forming the first conductivity type region on the front surface of the substrate includes:

The first doping sub-step is doping the front side of the substrate to form a first conductivity type region;

The epitaxy sub-step, forming an epitaxial layer on the substrate, the epitaxial layer has a second conductivity type;

The sub-step of epitaxial doping is doping the epitaxial layer at the position corresponding to the first conductivity type region to extend the depth of the first conductivity type region;

Repeating the above epitaxial sub-step and epitaxial doping sub-step in sequence until the depth of the first conductivity type region is extended to the first depth.

In one embodiment, forming a region of the first conductivity type and a region of the second conductivity type on the front surface of the substrate includes:

The first doping sub-step is doping the front side of the substrate to form a second conductivity type region;

In the second doping sub-step, doping the front side of the substrate to form a region of the first conductivity type;

The epitaxy sub-step, forming an epitaxial layer on the substrate, the epitaxial layer has a second conductivity type;

The sub-step of epitaxial doping, doping the epitaxial layer corresponding to the second conductivity type region and the first conductivity type region respectively, extending the depth of the second conductivity type region and the first conductivity type region;

The above-mentioned epitaxial sub-step and epitaxial doping sub-step are repeated in sequence until the depth of the region of the first conductivity type is extended to the first depth, and the depth of the region of the second conductivity type is extended to the second depth.

In one embodiment, before forming the emission region on the base region, it further includes:

A minority carrier barrier layer is formed under the base region, the minority carrier barrier layer has a second conductivity type, and the bottom of the minority carrier barrier layer is higher than the bottom of the trench gate; the extraction channel penetrates the minority carrier barrier layer and is electrically connected to the first conductivity type region.

In one embodiment, before forming the trench gate on the first trench, the method further includes:

A lightly doped region of the second conductivity type is formed at the bottom of the first trench, and the lightly doped region of the second conductivity type is located on a side of the bottom of the first trench away from the region of the first conductivity type.

In one embodiment, the thick gate dielectric layer is formed by dry-wet-dry oxidation, and/or the thin gate dielectric layer is formed by dry oxygen oxidation.

According to the second aspect, an embodiment provides an IGBT device manufactured by using the manufacturing method described in the first aspect.

According to a third aspect, an IGBT device is provided in an embodiment, including at least one cell, the cell includes a first electrode, a second electrode, and a semiconductor unit located between the first electrode and the second electrode, and the semiconductor unit includes :

The drift region, which has the second conductivity type, is used as a depletion layer when the IGBT device is in a forward withstand voltage process;

A first conductivity type region, which has a first conductivity type, is formed in the drift region, the bottom surface of the first conductivity type region is away from the top of the drift region, and is close to or flush with the bottom of the drift region;

a base region having a first conductivity type;

The trench gate includes a gate and a gate dielectric layer surrounding the gate. The trench gate penetrates the base region and extends to the drift region; the gate dielectric layer includes a thick gate dielectric layer and a thin gate dielectric layer respectively formed on both sides of the gate, The thickness of the thick gate dielectric layer is greater than the thickness of the thin gate dielectric layer;

An extraction channel, which has a first conductivity type, and the first electrode is electrically connected to the region of the first conductivity type through the extraction channel; when the IGBT device is in an off state, the first electrode extracts the minority load at the bottom of the trench gate through the extraction channel Ryuko;

The emitter region has a second conductivity type, the first conductivity type and the second conductivity type belong to different semiconductor conductivity types, a first PN junction is formed between the emitter region and the base region, and the base region and the emitter region are electrically connected to the first electrode respectively. connect;

The extraction channel is located on one side of the thick gate dielectric layer, and the emission area is located on one side of the thin gate dielectric layer;

The collector region, which is located below the drift region, has the first conductivity type, and is electrically connected to the second electrode for providing carriers when the IGBT device is in an on state.

In one embodiment, one cell includes two trench gates, and the extraction channel is formed between the thick gate dielectric layers of two adjacent trench gates; and/or, the acceptor doping concentration in the middle region of the extraction channel is The acceptor doping concentration is lower than the acceptor doping concentration in the regions at both ends, or the donor doping concentration in the middle region of the extraction channel is higher than the donor doping concentration in the two ends regions.

According to the IGBT device and its manufacturing method of the above-mentioned embodiments, the gate dielectric layer of the trench gate includes a thin gate dielectric layer and a thick gate dielectric layer, and the extraction channel is formed on the side of the thick gate dielectric layer, and does not need to pass through a thick gate dielectric layer alone. To form, the extraction channel extracts the minority carrier through the first conductivity type region when the device is off, only one kind of trench gate is needed to complete the extraction of the minority carrier and the conduction effect of the gate, which can reduce the lateral size of the cell and improve the device current capability.

Description of drawings

Fig. 1 is the structural representation of a kind of IGBT device of prior art;

Fig. 2 is a schematic structural diagram (1) of an IGBT device of an embodiment;

Fig. 3 is a schematic structural diagram (2) of an IGBT device of an embodiment;

Fig. 4 is a schematic structural diagram (3) of an IGBT device of an embodiment;

Fig. 5 is a flow chart of a method for manufacturing an IGBT device of an embodiment;

Fig. 6 is a process schematic diagram (1) of a manufacturing method of an IGBT device according to an embodiment;

Fig. 7 is a process schematic diagram (2) of a manufacturing method of an IGBT device according to an embodiment;

Fig. 8 is a process schematic diagram (3) of a manufacturing method of an IGBT device according to an embodiment;

FIG. 9 is a process schematic diagram (4) of a manufacturing method of an IGBT device according to an embodiment;

Fig. 10 is a process schematic diagram (5) of a manufacturing method of an IGBT device according to an embodiment;

Fig. 11 is a process schematic diagram (6) of a method for manufacturing an IGBT device according to an embodiment;

Fig. 12 is a process schematic diagram (7) of a manufacturing method of an IGBT device according to an embodiment;

Fig. 13 is a schematic diagram of the base area and the emission area of an embodiment;

Fig. 14 is a schematic structural diagram of an extraction channel of an embodiment;

FIG. 15 is a process schematic diagram (8) of a manufacturing method of an IGBT device according to an embodiment.

Reference signs: 1-drift region; 101-first trench; 2-first conductivity type region; 3-second conductivity type region; 4-trench gate; 41-gate dielectric layer; 411-thick gate dielectric layer ; 412-thin gate dielectric layer; 42-grid; 5-extraction channel; 6-base region; 7-emitter region; 8-first electrode; 9-collector region; ; 12-minority carrier barrier layer; 13-lightly doped region of the second conductivity type.

Detailed ways

The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. Wherein, similar elements in different implementations adopt associated similar element numbers. In the following implementation manners, many details are described for better understanding of the present application. However, those skilled in the art can readily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, and methods. In some cases, some operations related to the application are not shown or described in the description, this is to avoid the core part of the application being overwhelmed by too many descriptions, and for those skilled in the art, it is necessary to describe these operations in detail Relevant operations are not necessary, and they can fully understand the relevant operations according to the description in the specification and general technical knowledge in the field.

In addition, the characteristics, operations or characteristics described in the specification can be combined in any appropriate manner to form various embodiments. At the same time, the steps or actions in the method description can also be exchanged or adjusted in a manner obvious to those skilled in the art. Therefore, various sequences in the specification and drawings are only for clearly describing a certain embodiment, and do not mean a necessary sequence, unless otherwise stated that a certain sequence must be followed.

The serial numbers assigned to components in this document, such as "first", "second", etc., are only used to distinguish the described objects, and do not have any sequence or technical meaning. The "connection" and "connection" mentioned in this application include direct and indirect connection (connection) unless otherwise specified.

In this application, the first conductivity type and the second conductivity type belong to different semiconductor conductivity types, the first conductivity type is N-type or P-type, and the second conductivity type is P-type or N-type; when the first conductivity type is N-type Type, the second conductivity type is P-type, and vice versa. In this application, the first conductivity type is P-type, and the second conductivity type is N-type as an example for illustration.

In this application, the substrate of an IGBT device generally refers to a silicon wafer, but other materials, such as silicon carbide, gallium nitride, etc., can also be used according to actual device applications. The substrate can be N-type, P-type or undoped, and is used as the starting material or starting structure layer in the device manufacturing process. When the substrate corresponds to different device types, after the device is fabricated, it can be used as a structure such as a collector region, a buffer layer or a drift region of the device. The substrate (or substrate) is a structure obtained by doping, epitaxy, thermal oxidation, etc. on the substrate. The shape structure is still a sheet-like structure mainly composed of single crystal silicon, which can also be generally called wafer or silicon wafer. , or still referred to as the substrate. In mass production, multiple devices may use the same substrate for the same processing, therefore, a standardized substrate can be formed for production, and there is no need to process the substrate from scratch, which can save time. Depending on the type of corresponding IGBT device, the IGBT device can be a PT (punch through) type, NPT (non-punch through) type or FS (field stop) type IGBT device. Depending on the type of device, different substrates can be selected.

For example, when the IGBT device is a PT-type IGBT device, the substrate may include a collector region, a buffer layer, and a drift region. It can be a layer of N-type single crystal silicon with higher doping concentration grown on the substrate, and the drift region can be a lightly doped N-type epitaxial layer deposited on the buffer layer.

For another example, when the IGBT device is an NPT type IGBT device, the substrate can include a silicon wafer using lightly doped N-type zone fused single crystal silicon as the substrate (as the drift region of the subsequent device), and the cell is first fabricated on the front side of the silicon wafer. And protect it with a passivation layer, and then thin the back of the silicon wafer to an appropriate thickness. Finally, P-type doping is performed on the back of the thinned silicon wafer to form a collector region.

For another example, when the IGBT device is an FS type IGBT device, the substrate may include a drift region or a buffer layer and a drift region. The substrate can be a silicon wafer with lightly doped N-type region fused single crystal silicon. When the substrate only has a drift region, the backside process (thinning of the silicon wafer, formation of a buffer layer and a collector area) is performed after the fabrication of the front cell is completed. . When the substrate can include a buffer layer and a drift region, an N-type silicon wafer is used as the substrate (corresponding to the buffer layer of the device), and the drift region is formed on the front side of the epitaxial silicon wafer to complete the fabrication of the front cell, and the back side of the silicon wafer is thinned , for P-type doping to form a collector region.

As shown in Figure 1, in the existing patent CN202210453957.6, in order to solve the technical problem of dynamic avalanche in the turn-off switching process of IGBT devices, on the one hand a super junction structure (first conductivity type region) is introduced, on the other hand The extraction channel is used to work with the superjunction structure, and there are at least two problems in the existing patents. The first problem is that in order to form the extraction channel, two adjacent second trench gates with a thick gate dielectric layer are required, which are formed during the thermal oxidation of the gate dielectric layer, which causes the cells of the device to be in the lateral direction (Figure 1 The left and right directions) are too large in size and the current capacity is low. The second problem is that the first conductivity type region is formed by etching trenches to fill silicon. The trenches formed by etching are not strictly vertical, and there are angles, and the depth of etching should not be too deep. If the bottom is too narrow, it will cause Too few ionized impurities affect the charge balance.

In the embodiment of the present invention, aiming at the first problem, an IGBT device is proposed, wherein the gate dielectric layer 41 of the trench gate 4 includes a thin gate dielectric layer 412 and a thick gate dielectric layer 411, and the extraction channel 5 is formed on the thick gate dielectric layer 412. The side of the dielectric layer 411 does not need to be formed through a thick oxygen gate (corresponding to the second trench gate shown in FIG. A trench gate 4 is needed to complete the extraction of minority carriers and the conduction effect of the gate 42, which can reduce the lateral size of the cell and improve the current capability of the device. For the second problem, by providing a manufacturing method for IGBT devices, the first conductivity type region 2 is formed by multiple ion implantation and epitaxy, ensuring that the width of the first conductivity type region 2 (the left and right directions in Figure 2) is consistent from top to bottom As well as the amount of ionized impurities in the overall area, the charge balance problem can be guaranteed to be stable.

As shown in FIG. 2 , the first conductivity type is P-type and the second conductivity type is N-type as an example. In some embodiments of the present application, an IGBT device is provided. The IGBT device may include at least one cell, cell It may include a first electrode 8, a second electrode 10, and a semiconductor unit located between the first electrode 8 and the second electrode 10, and the semiconductor unit may include: a drift region 1, a first conductivity type region 2, a base region 6, a trench Gate 4, extraction channel 5, emitter region 7 and collector region 9.

The drift region 1 may have a second conductivity type, and is used as a depletion layer when the IGBT device is in a forward withstand voltage process. In some embodiments, the drift region 1 may include part or all of the substrate, and may also include an epitaxial layer epitaxially formed on the substrate.

The first conductivity type region 2 may have the first conductivity type and is formed in the drift region 1. The bottom surface of the first conductivity type region 2 is far away from the top (or upper surface or front surface) of the drift region 1 and is close to the bottom of the drift region 1. Or flush with the bottom of drift zone 1. The width (the left-right direction in FIG. 2 ) of the first conductivity type region 2 is smaller than the height/depth (the up-down direction in FIG. 2 ).

For example, the region 2 of the first conductivity type may be a P-type region (or simply called a P-column). form. The first conductivity type region 2 may be in contact with the buffer layer 11 ; or the first conductivity type region 2 is close to the buffer layer 11 , and the depth of the first conductivity type region 2 is greater than or equal to 2/3 of the depth of the drift region 1 .

The base region 6 may have the first conductivity type. In the embodiment of the present application, the base region 6 does not include the deep base region as shown in FIG. 1 . The bottom surface of the base region 6 is higher than the bottom surface of the trench gate 4 .

The trench gate 4 may include a gate 42 and a gate dielectric layer 41 surrounding the gate 42. The trench gate 4 penetrates the base region 6 and extends to the drift region 1; as shown in FIG. Thick gate dielectric layer 411 (referred to as thick oxide) and thin gate dielectric layer 412 (referred to as thin oxide) on both sides of gate 42 , thick gate dielectric layer 411 is thicker than thin gate dielectric layer 412 .

In some embodiments, the thick gate dielectric layer 411 may be formed on the first trench 101 by thermal oxidation, and the thin gate dielectric layer 412 may be formed on the first trench 101 by deposition or thermal oxidation. Wherein, a thick gate dielectric layer is formed on the bottom of the first trench 101 to alleviate the electric field concentration effect at the bottom of the gate. Because the electric field is concentrated at this position, the thin gate oxide is usually easy to break down. When the thickness increases, the potential dropped under the unit gate oxide thickness decreases, so that the potential borne by the unit gate oxide thickness is reduced, thereby alleviating the electric field spike and improving device breakdown. wear ability. In addition, due to the existence of the coupling capacitance between the gate and the collector, increasing the thickness of this part can greatly reduce the gate charge and strengthen the control of dV/dt during the switching process of the device.

The extraction channel 5 may have a first conductivity type, and the first electrode 8 is electrically connected to the region 2 of the first conductivity type through the extraction channel 5; when the IGBT device is in an off state, the first electrode 8 extracts the groove through the extraction channel 5 Minority carriers at the bottom of gate 4.

In some embodiments, one cell may include two trench gates 4, and the extraction channel 5 is formed between the thick gate dielectric layers 411 of two adjacent trench gates 4; and/or, when the extraction channel 5 is P type, the acceptor doping concentration in the middle region of the extraction channel 5 is lower than the acceptor doping concentration in the regions at both ends, or, when the extraction channel 5 is N-type, the donor doping concentration in the middle region of the extraction channel 5 is higher than that in the two ends. Donor doping concentration in the terminal region.

In some embodiments, as shown in FIG. 2, the depth of the extraction channel 5 can be the same as the depth of the trench gate 4; as shown in FIG. The doping concentration is lower than the P-type doping concentration of the two end regions. When the device is forward-conducting, a positive voltage is applied to the gates 42 on both sides, and the channel is inverted, and the inverted carriers are P-type minority carriers (electrons), and the concentration in the middle is higher than that at both ends. When the reverse is cut off, negative voltage is applied to the gates 42 on both sides, and the concentration of P-type multiples at both ends is higher than that in the middle.

When the drift region 1 is P-type, the base region 6 is N-type, and the extraction channel 5 is N-type, the N-type doping concentration in the middle region of the extraction channel 5 is higher than the N-type doping concentration in the regions at both ends. The technical effect corresponds to that when the extraction channel 5 is P-type, and will not be repeated here.

In some embodiments, as shown in FIGS. 9 and 12 , the thick gate dielectric layer 411 is formed by thermal oxidation. Since silicon dioxide has the effect of absorbing boron and releasing phosphorus, the first trench between the two first trenches 101 The boron element in the conductivity type region 2 decreases, and the phosphorus element increases, which eventually reduces the doping concentration of the first conductivity type region 2 between the two first trenches 101 (referring to the concentration of boron element), which is affected by boron absorption and phosphorus emission The part of the first conductivity type region 2 of the effect constitutes the extraction channel 5 . At the same time, the middle of the extraction channel 5 is more significantly affected by boron absorption and phosphorus removal, the middle area is the lowest, and the doping concentration increases from the middle to both ends (the up and down directions in the figure). It can be seen that, by adopting the structure in which two trench gates 4 are arranged adjacent to each other in FIG. 2 , the change of the doping concentration in the region between the two trench gates 4 can be more obvious, and the concentration in the middle of the region is lower, so that Faster extraction of minority carriers.

Further, the thickness of the thick gate dielectric layer 411 can be greater than the thickness of the thin gate dielectric layer 412; the thicker thick gate dielectric layer 411 consumes a part of single crystal silicon through thermal oxidation to reduce the PMOS channel (corresponding to the extraction channel 5) The width of the PMOS reduces the channel density of the PMOS, and when the minority carriers accumulate at the bottom, the leakage can be suppressed and the leakage of the device can be reduced. For example, when a semiconductor unit has two trench gates 4, in order to avoid interference between the two gates 42, the distance between the two cannot be too close, and at the same time, in order to ensure the channel density of the extraction channel 5, the two The distance between the gates 42 should not be too far. In this embodiment, the width of the extraction channel 5 can be 300A-1000A. In relation, the ratio is about 1:10, corresponding to the thickness of the thick gate dielectric layer 411 being 4000A-10000A.

The emitter region 7 may have a second conductivity type, a first PN junction is formed between the emitter region 7 and the base region 6 , and the base region 6 and the emitter region 7 are electrically connected to the first electrode 8 respectively. The extraction channel 5 is located on one side of the thick gate dielectric layer 411 , and the emitter region 7 is located on one side of the thin gate dielectric layer 412 .

The collector region 9 is located under the drift region 1 and may have the first conductivity type. The collector region 9 is electrically connected to the second electrode 10 for providing carriers when the IGBT device is in an on state.

Aiming at the problem of the large lateral size of the IGBT device shown in Figure 1, the applicant found through research that there are two reasons for the large lateral size, one is that the cells are provided with two types of trench gates, and the other is that The reason for the deep base area is that the deep base area should include the bottom part of the first trench gate, and the deep base area is spread across the first trench gate after ion implantation, so the gap between the first trench gate and the second trench gate is A certain lateral distance should also be ensured between them, so as to prevent the bottom of the first trench gate from being completely wrapped, and avoid losing the function of controlling the conduction of the device.

Therefore, in the above embodiment, on the one hand, by providing a trench gate 4, there are gate dielectric layers 41 with different thicknesses on both sides of the trench gate 4, so that one trench gate 4 combines the two trench gates in FIG. The technical effect is that it has both conduction control and minority carrier extraction control at the same time. On the premise that two types of trench gates and deep base regions are not required, the lateral size of the cell can be reduced, and finally it can be obtained under the same chip size. Lower conduction voltage drop, larger current capability, and lower cost advantages.

As shown in FIG. 3 , on the basis of the above-mentioned embodiments, the IGBT device provided by the present application may further include a minority carrier barrier layer 12 and a lightly doped region 13 of the second conductivity type. The lightly doped region 13 of the second conductivity type is located at A side of the bottom of the first trench 101 away from the region 2 of the first conductivity type. The minority carrier barrier layer 12 may have a second conductivity type, the bottom of the minority carrier barrier layer 12 is higher than the bottom of the trench gate 4 and located below the base region 6; the extraction channel 5 penetrates the minority carrier barrier layer 12 and the first conductivity type region 2 electrical connections. The lightly doped region 13 of the second conductivity type has a second conductivity type, and its doping concentration is lower than that of the drift region 1 .

Compared with the deep base region shown in FIG. 1 , the IGBT device provided by the present application uses the minority carrier barrier layer 12 and the lightly doped region 13 of the second conductivity type to have similar or better technical effects, which will be described in detail below.

Taking the N-type drift region 1 as an example, the function of the minority carrier barrier layer 12 is different from that of the deep base region. It only reduces the resistivity of the epitaxial layer under the P-type base region 6 in the working state of the device. The existence of the minority carrier barrier layer 12 is In order to prevent minority carriers from flowing out from the P-type base region 6 , the concentration of minority carriers there is accumulated, thereby reducing the conduction voltage drop Vcesat and conduction loss.

The role of the deep base region shown in Figure 1 is to protect the gate 42 from breaking down the weak point and reduce the peak value of the electric field at the bottom of the gate 42, which is now obtained by using the lightly doped region 13 of the second conductivity type (N-region) at the bottom of the gate 42 Similar technical effects, such that deep bases may not be used. It may be that a small amount of boron ions are implanted after the gate 42 is trenched. After thermal processes such as gate oxide growth and P-type base region 6 diffusion, these small amount of boron ions are compensated by epitaxy background impurities, and will form a Lower N-zone. In the reverse-bias cut-off state of the device, EC≈4010N _D ^1/8 , the critical electric field at this place is increased, which will alleviate the electric field concentration at the bottom of the gate oxide, disperse the potential, reduce the peak value of the electric field at this place, increase the breakdown voltage, and suppress the gate oxide. Pole 42 negative capacitance for better switch controllability.

As shown in Figure 4, in some embodiments, the IGBT device provided by the present application may also include a second conductivity type region 3 (corresponding to the first conductivity type region 2 is referred to as a P column for short, which may be referred to as an N+ column for short), which has The second conductivity type and the doping concentration is greater than that of the drift region 1, the second conductivity type region 3 and the first conductivity type region 2 are arranged at intervals along the left and right directions, forming a super junction epitaxy with PN-N+-NP lateral change doping, increasing the space hole path structure. For example, if two N epitaxial implants are used to implant the overlapping part to form an N+ column (corresponding to the process shown in Figure 15), because there are not many overlapping parts, and the implanted ions will also diffuse laterally during the growth of the epitaxy, so the N+ column It accounts for only a small part of the entire N area, and this area can also be called the N+ area of the N column. But because more ions are implanted, the net doping in this area will increase. According to ρ=(qNμ) ^-1 , the resistivity ρ is inversely proportional to the net doping, and according to Ohm's law, the current always chooses the one with the least resistance. path through.

Therefore, the N+ column can reduce the resistivity at the current conduction path of the device. Compared with the IGBT device shown in Figure 1, under the same chip area, this application will improve the current capability of the device, thereby reducing the conduction voltage drop Vcesat, reducing switching losses.

Among them, the N column (the part of the drift region 1 located between the first conductivity type region 2 and the second conductivity type region 3) with a lower concentration than the N+ column can play a role in contact with the P column during the reverse cut-off period of the device. The effect of charge balance, the reverse bias of the PN junction formed by the N column and the P column, forms a wider depletion region, establishes a vertical electric field, and at the same time prevents the horizontal electric field of the device from changing abruptly, so that the electric field of the device in the horizontal and vertical directions They are all in a state close to the critical state, increasing the width of the depletion region and improving the effective withstand voltage area. Specifically, the main space charge region of a traditional device (non-superjunction device) is generated by reverse bias depletion of the PN junction between the P base region and the epitaxial layer. When the breakdown voltage is reached, the peak value of the electric field is near the PN junction, cut off at the FS layer (cut-off layer), and the shape is trapezoidal. The integral of the electric field pattern to the space charge region is the breakdown voltage of the device. The N column and the P column form a PN junction. Under the condition of charge balance, the PN junction will be depleted in the reverse bias state to form a space charge region. In this way, two different PN junctions will be depleted, and the device body will be depleted. There will be two space charge regions with different depletion directions, and there will be two electric fields in different directions, one electric field direction is perpendicular to the PN junction of the super junction epitaxy and the P base region, and the other is perpendicular to the super junction epitaxy N column and the The pn junction of the P column, under the action of the electric fields in two different directions, can make the electric field approximately expand into a cuboid shape in three-dimensional space, and the cut surface in the vertical direction is approximately rectangular, and its breakdown voltage is the integral of the epitaxial thickness of the figure . The effective withstand voltage area of the epitaxy can be increased.

In addition, during the turn-off period, the existence of the first conductivity type region 2 (P column), combined with the depletion-type PMOS structure of the front structure, forms a path for non-equilibrium minority carriers to flow out of the body, and achieves rapid extraction of the N-type drift region The purpose of the unbalanced minority carrier of 1 is to suppress the tail current, thereby reducing the turn-off loss. Since the non-equilibrium minority carriers in the body reach the level of the background doping concentration or even more during the dynamic switching process, the critical electric field of the material is reduced, and the N/P column of the superjunction structure can quickly discharge the non-equilibrium minority carriers in this process and suppress the dynamic avalanche , to suppress the generation of turn-off noise.

The above is a specific description of each structure of the IGBT device provided by this application. The following is an expanded description of the manufacturing method of the IGBT device. It should be noted that the embodiment of this application uses Figure 4 as an example to describe the manufacturing method, corresponding to Figures 2 to 2. The IGBT device shown in Figure 4 can selectively reduce one or more of the following method steps to obtain any IGBT device in Figure 2 to Figure 4, which is not limited to the device corresponding to the manufacturing method of the IGBT device provided by this application type.

As shown in FIG. 5, the following takes the first conductivity type as P-type and the second conductivity type as N-type as an example. The method for manufacturing an IGBT device provided in the embodiment of the present application may include:

Step 1. Provide a substrate. The substrate serves as part or all of the drift region 1 of the IGBT device. The substrate may have a second conductivity type. For example, as shown in (A) of Fig. 6, an N-type single crystal silicon substrate can be used.

Step 2, forming the first conductivity type region 2 on the front surface of the substrate, or forming the first conductivity type region 2 and the second conductivity type region 3 on the front surface of the substrate.

In some embodiments, as shown in FIG. 2, FIG. 3 and FIG. 6, the IGBT device may only include the first conductivity type region 2. At this time, forming the first conductivity type region 2 on the front side of the substrate may include:

The first doping sub-step, as shown in Figure 6(B), is to dope the front side of the substrate to form the first conductivity type region 2; for example, implant 1e12cm ^-2 -1e13cm ^-2 with an energy of 40- 100KeV boron ions to form the first conductivity type region 2 .

In the sub-step of epitaxy, as shown in (C) of FIG. 6 , an epitaxial layer is formed on the substrate, and the epitaxial layer may have the second conductivity type; the thickness of each epitaxy may be 1um-10um. The formed epitaxial layer has the same conductivity type as that of the drift region 1 , and its doping concentration may also be the same as that of the drift region 1 .

The sub-step of epitaxial doping, as shown in FIG. 6 (D), is to dope the position of the epitaxial layer corresponding to the first conductivity type region 2 to extend the depth of the first conductivity type region 2 .

The above-mentioned epitaxial sub-step and epitaxial doping sub-step are repeated in sequence until the depth of the first conductivity type region 2 is extended to the first depth. At this time, the total thickness of the corresponding multi-layer epitaxial layer may be 50um-100um.

In some embodiments, as shown in FIG. 4 and FIG. 7, the IGBT device may include a first conductivity type region 2 and a second conductivity type region 3. At this time, the first conductivity type region 2 and the second conductivity type region are formed on the front side of the substrate. Conductivity type zone 3 may include:

The first doping sub-step, as shown in FIG. 7(B), is to dope the front side of the substrate to form the second conductivity type region 3 .

The second doping sub-step, as shown in FIG. 7(B), is to dope the front side of the substrate to form the first conductivity type region 2 . The order of the above-mentioned first doping sub-step and second doping sub-step is not limited, for example, phosphorus ions with a dose of 1e12-1e13cm ^-2 and an energy of 40-100KeV are first implanted to obtain the second conductivity type region 3 and form N-N+-N lateral change doping region, and then implant 1e12-1e13cm ^-2 boron ions with an energy of 40-100KeV to obtain the first conductivity type region 2 and form a PN-N+-NP lateral change doping superjunction extension.

In the sub-step of epitaxy, as shown in (C) of FIG. 7 , an epitaxial layer is formed on the substrate, and the epitaxial layer may have the second conductivity type. The thickness of each epitaxy can be 1um-10um. The formed epitaxial layer has the same conductivity type as that of the drift region 1 , and its doping concentration may also be the same as that of the drift region 1 .

The sub-step of epitaxial doping, as shown in (D) in Figure 7, is to dope the epitaxial layer corresponding to the second conductivity type region 3 and the first conductivity type region 2, and extend the second conductivity type region 3 and the first conductivity type region. The depth of conductivity type zone 2.

In some embodiments, the manner of forming the region 3 of the second conductivity type and the region 2 of the first conductivity type may also adopt the following manner.

First, as shown in Figure 15, one region can be N-type doped first (as shown in Figure 15 (A) on the left), and then another region is N-type doped (as shown in Figure 15 (B) ) on the right side), the double doping has an overlapping region, as shown in (C) in FIG. 15 , the overlapping region corresponds to the formation of the second conductivity type region 3 . Subsequently, as shown in (D) of FIG. 15 , doping of the first conductivity type region 2 is performed. Finally, the structure shown in FIG. 8 is formed through multiple epitaxy and doping.

In some embodiments, the second conductivity type region 3 is formed between every two first conductivity type regions 2 , and a drift region is further provided between the first conductivity type region 2 and the second conductivity type region 3 .

As shown in FIG. 8 , the above epitaxial sub-step and epitaxial doping sub-step are repeated in sequence until the depth of the first conductivity type region 2 is extended to the first depth, and the depth of the second conductivity type region 3 is extended to the second depth. Repeat the above process, at this time, the total thickness of the corresponding multi-layer epitaxial layer may be 50um-100um.

Step 3. As shown in FIG. 9 , a first trench 101 is formed on the substrate, and the first trench 101 penetrates a part of the region 2 of the first conductivity type.

In some embodiments, as shown in FIG. 10 , before forming the trench gate 4 on the first trench 101 , the manufacturing method may further include:

A lightly doped region 13 of the second conductivity type is formed at the bottom of the first trench 101 , and the lightly doped region 13 of the second conductivity type is located on a side of the bottom of the first trench 101 away from the region 2 of the first conductivity type. For example, after the first trench 101 is etched, an oxide layer with a thickness of 1000A can be formed as a sacrificial oxide layer to reduce lattice damage caused by ion implantation. The re-implantation dose is 1e11-1e12cm-2, Boron ions with an energy of 20-60KeV.

By implanting a small amount of boron ions in the N-type drift region 1 to form an N-region, reduce the charge of the gate 42, suppress the negative capacitance of the gate 42, reduce the noise generated during the switching process, disperse the reverse bias potential, reduce the peak value of the electric field, and protect the trench The weak area at the corner of the grid 4 that is prone to breakdown. Among them, the injection dose and energy should be controlled, neither too much nor too little. If the dose and energy are too high, it will become a P region, which will surround the bottom of the gate, which will affect the conduction voltage drop and increase the conduction loss. If it is too small, the effect will not be obvious.

Step 4. As shown in FIG. 11 , a trench gate 4 is formed on the first trench 101. The trench gate 4 may include a gate 42 and a gate dielectric layer 41 surrounding the gate 42; the gate dielectric layer 41 may include a gate dielectric layer formed separately. The thick gate dielectric layer 411 and the thin gate dielectric layer 412 on both sides of the gate 42, the thickness of the thick gate dielectric layer 411 is greater than the thickness of the thin gate dielectric layer 412; the thick gate dielectric layer 411 is located near the first conductivity type region 2 side and is in contact with the first conductivity type region 2; wherein, during the formation of the trench gate 4, the part of the first conductivity type region 2 in contact with the thick gate dielectric layer 411 forms the extraction channel 5.

In some embodiments, forming the trench gate 4 on the first trench 101 may include:

Step 401, as shown in (A) of FIG. 11 , a silicon dioxide layer of a first thickness is grown on the first trench 101 by thermal oxidation as a thick gate dielectric layer 411 . During the formation of the thick gate dielectric layer 411 , an extraction channel 5 is formed on the trench gate 4 side. In some embodiments, a layer of gate oxide with a thickness of 4000A-10000A can be grown by a dry-wet-dry oxidation method, part of which is used for etching and removal, and part of which is used for gate oxide of PMOS. The concentration in the middle part of the PMOS channel will decrease due to boron absorption and phosphorus discharge during the growth of the oxide layer.

Step 402 , as shown in FIG. 11 (B), remove the thick gate dielectric layer 411 on the sidewall of the first trench 101 away from the first conductivity type region 2 . For example, anisotropic etching is used to etch the thick gate dielectric layer 411 of the sidewall portion of the first channel away from the first conductivity type region 2 .

Step 403 , as shown in (C) of FIG. 11 , a silicon dioxide layer with a second thickness is grown on the first trench 101 as a thin gate dielectric layer 412 by thermal oxidation. For example, dry oxygen oxidation is used to form a thin gate dielectric layer 412 with a thickness of 500-2000 Å.

Step 404 , as shown in (D) of FIG. 11 , perform polysilicon backfilling and polysilicon etching on the first trench 101 to obtain a gate 42 .

Among them, because the thick gate dielectric layer is formed by dry-wet-dry oxidation, the speed of wet oxygen is fast, but the quality of the formed oxide layer is poor, with many defects and poor consistency (different thickness), and the density of dry oxygen is good, and there are few defects. , high quality, good consistency, but slow speed, for production efficiency, wet and dry oxidation is used to grow thick gate oxide.

Because the threshold voltage needs to match the actual driving circuit, usually around 2-6V, and the threshold voltage is proportional to the thickness of the gate oxide. Under the same P base condition, the thick gate oxide will increase the threshold voltage several times. It is difficult to invert the electronic conduction channel, thereby increasing the conduction voltage drop and conduction loss, so a thin gate dielectric layer is required. The thin gate dielectric layer is the thickness of the traditional device, which can match the existing P-base region without changing it.

Step 5, as shown in FIG. 12 , doping the front side of the substrate to form a base region 6 , the base region 6 may have the first conductivity type, and the bottom of the base region 6 is higher than the bottom of the trench gate 4 .

In some embodiments, as shown in FIG. 12, before forming the emission region 7 on the base region 6, the manufacturing method may further include:

A minority carrier barrier layer 12 is formed below the base region 6, the minority carrier barrier layer 12 may have a second conductivity type, and the bottom of the minority carrier barrier layer 12 is higher than the bottom of the trench gate 4; the extraction channel 5 penetrates the minority carrier barrier layer 12 and The first conductivity type regions 2 are electrically connected.

For example, the front side of the substrate is doped, and the ion implantation of the P-type base region 6 and the minority carrier barrier layer 12 is performed respectively. The base region 6 is implanted with boron ions, the dose is 1e13-1e14, the energy is 50-100KeV, and the minority carrier barrier layer 12 Implant phosphorus ions with a dose of 1e13-1e14, an energy of 150-300KeV, annealing at 1100-1180°C, and a time of 100-300 minutes. The depths of the minority carrier barrier layer 12 and the base region 6 are controlled by controlling the implantation energy. Among them, the implantation energy and dose of the minority carrier barrier layer 12 should be well controlled. If the concentration of this layer is too high, the breakdown voltage will be reduced, and if it is too small, the conduction voltage drop will be increased.

Step 6. As shown in FIG. 4 , an emitter region 7 is formed on the base region 6, and the emitter region 7 may have a second conductivity type; the emitter region 7 is located on one side of the thin gate dielectric layer 412 of the trench gate 4 and is connected to the thin gate Dielectric layer 412 contacts.

In some embodiments, the structural relationship between the emission region 7 and the base region 6 can be as shown in Figure 13, and can be the vertical emission region 7 structure (perpendicular to the direction of Figure 4) as shown in Figure 1 and (A) in Figure 13 ), an emitter region 7 is located between two trench gates 4, the vertical structure can reduce the lateral size of the device, the length of the emitter region 7 (the direction perpendicular to Figure 4) and the length of the base region 6 can be adjusted according to the actual device needs Adjustment, the short length of the emission region 7 is good for short circuit, and the long length of the emission region 7 is good for the conduction voltage drop. In this embodiment, the two are equal as an example (see (A) in FIG. 13 ). Or adopt the lateral emitter region 7 structure as shown in (B) in FIG. 13 , one emitter region 7 corresponds to one trench gate 4, as shown in FIG. The contact area of the electrode 8 can be adjusted. Reducing the image area of the emission region 7 is beneficial to the short circuit time and avalanche test, and increasing it will reduce the conduction voltage drop.

For example, N+ is implanted with phosphorous ions at a dose of 3e15-1e16 and energy is 50-100KeV, and P+ is implanted with boron ions at a dose of 1e15-5e16 with an energy of 100-120KeV and annealed at 950°C for 10-60min, wherein the emitter region 7 is formed after N+ implantation and annealing. After P+ implantation and annealing, the ohmic contact area is made.

Step 7, as shown in Figure 4, form the first electrode 8 on the front side of the substrate, the first electrode 8 is electrically connected with the extraction channel 5, the base region 6 and the emitter region 7 respectively; the extraction channel 5 is used for when the IGBT device is off In the off state, the first electrode 8 extracts the minority carriers at the bottom of the trench gate 4 through the extraction channel 5 .

For example, after depositing an interlayer dielectric layer, for example, 1000-3000A of USG and 6000-11000A of BPSG are deposited, and then annealed at 950° C. for 30 minutes.

Then conduct contact hole etching and implantation, respectively etch the contact holes in the NMOS and PMOS regions, implant boron ions, the dose is 1e15-1e16, the energy is 20-100KeV, and then deposit metal to form ohmic contact with the metal to form the emitter (first electrode 8).

Step 8, as shown in FIG. 4 , form a collector region 9 on the back of the substrate, or form a buffer layer 11 and a collector region 9 on the back of the substrate; form a second electrode 10 on the collector region 9, the second The electrode 10 is electrically connected to the collector region 9, the buffer layer 11 may have a second conductivity type, the collector region 9 may have a first conductivity type, and the first conductivity type and the second conductivity type belong to different semiconductor conductivity types.

In some embodiments, in step 8, forming the buffer layer 11 on the back side of the substrate may include:

Thinning the back of the substrate to a preset thickness, forming a buffer layer 11 on the back of the substrate by doping, the doping concentration of the buffer layer 11 is greater than the doping concentration of the drift region 1; the first conductivity type region 2 and the buffer layer 11 contact, or the region 2 of the first conductivity type is close to the buffer layer 11 , and the depth of the region 2 of the first conductivity type is greater than or equal to 2/3 of the depth of the drift region 1 .

For example, the back side of the substrate is thinned to a thickness of 50-100 microns in the drift region 1, and the buffer layer 11 is first doped with phosphorus to form an N-type buffer layer 11, so that the first conductivity type The bottom of region 2 is close to or in contact with buffer layer 11 . Then the buffer layer 11 is doped with boron to form a P-type collector region 9 . Alternatively, the thinned drift region 1 is directly doped with boron to form a P-type collector region 9 . Finally, the second electrode 10 is formed on the surface of the collector region 9 .

Through the manufacturing method of the above embodiment, the IGBT device manufactured and formed has at least the following technical effects.

First, in order to balance the saturation voltage drop and turn-off loss, this application adopts a super-junction process and adds a hole path structure. The epitaxial layer adopts multiple injection growth methods to form super junction epitaxy with P-N-N+-N-P lateral change doping. The laterally variable doped superjunction epitaxial N+ column can reduce the resistivity at the current conduction path of the device, improve the current capability, reduce the conduction voltage drop, and reduce the conduction loss. Moreover, compared with the N+ column, the lower N column can achieve the effect of charge balance with the P column during the reverse cut-off period of the device. The PN junction formed by the N column and the P column is reversely biased to form a wider depletion region. The vertical electric field is established, and at the same time, the horizontal electric field of the device does not produce a sudden change, so that the electric field of the device in the horizontal and vertical directions is in a state close to the critical state, increasing the width of the depletion region and improving the effective withstand voltage area.

Second, during the turn-off period, the existence of the P column, combined with the depletion-type PMOS structure of the front structure, forms a path for the non-equilibrium minority carriers to flow out of the body, and achieves the purpose of quickly extracting the non-equilibrium minority carriers in the N-type drift region 1 , to suppress the tail current, thereby reducing the turn-off loss. Since the non-equilibrium minority carriers in the body reach the level of the background doping concentration or even more during the dynamic switching process, the critical electric field of the material is reduced, and the N/P column of the superjunction structure can quickly discharge the non-equilibrium minority carriers in this process and suppress the dynamic avalanche , to suppress the generation of turn-off noise.

In the structure of this application, there are enhancement-type NMOS and depletion-type PMOS, forming a complementary MOS structure. When the IGBT is turned on, the NMOS is turned on and the PMOS is turned off. When it is turned off, the NMOS is turned off and the PMOS is turned on, so as to realize the rapid extraction of holes and reduce the turn-off loss. Among them, the enhanced NMOS refers to the overall structure of the emitter, the base region and the drift region on the side of the thin oxide layer.

Third, the relaxation of electric field concentration and the elimination of high holes are important factors to suppress dynamic avalanche. In the IGBT structure of the present application, the thickened bottom gate oxide, the N-region at the bottom of the trench gate 4 and the depletion-type PMOS play a role together. These two functions, and can realize high dV/dt turn-off operation under lower dynamic electric field, so can realize lower turn-off loss under the same conditions.

Fourth, compared with the structure of the existing IGBT device shown in Figure 1, this application thickens the oxide layer at the bottom of the gate 42, and etches a thick implant of ions opposite to the majority carriers of the substrate to form an N-region , let the potential below the gate 42 disperse, reduce the peak value of the electric field there, suppress the dynamic avalanche, reduce the charge on the gate 42, suppress the negative capacitance of the gate 42, and obtain better switch controllability.

Fifth, compared with the structure of the existing IGBT device shown in Figure 1, the device of this application uses minority carrier carriers as a barrier layer, which can help the device block non-equilibrium minority carriers during conduction , so that the non-equilibrium minority carrier accumulation under the minority carrier enhances the injection enhancement (IE) effect of the device, and its purpose is to achieve lower conduction voltage drop and smaller conduction loss, with a smaller unit cell width , under the same chip size, lower on-voltage drop, higher current capability, and lower cost can be obtained.

This document is described with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope herein. For example, the various operational steps, as well as the components used to perform the operational steps, may be implemented in different ways depending on the particular application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps may be deleted, modified or incorporated into other steps).

While the principles herein have been shown in various embodiments, many modifications in structure, arrangement, proportions, elements, materials and components, particularly suited to particular circumstances and operational requirements may be made without departing from the principles and scope of this disclosure use. The above modifications and other changes or amendments are intended to be included within the scope of this document.

The foregoing detailed description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of the present disclosure. Accordingly, the disclosure is to be considered in an illustrative rather than a restrictive sense, and all such modifications are intended to be embraced within its scope. Also, advantages, other advantages and solutions to problems have been described above with respect to various embodiments. However, neither benefits, advantages, solutions to problems, nor any elements that lead to these, or make the solutions more definite, should be construed as critical, required, or necessary. As used herein, the term "comprises" and any other variants thereof are non-exclusive, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also elements not expressly listed or not part of the process. , method, system, article or other element of a device. Additionally, the term "coupled" and any other variations thereof, as used herein, refers to a physical connection, an electrical connection, a magnetic connection, an optical connection, a communicative connection, a functional connection, and/or any other connection.

Those skilled in the art will recognize that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the invention. Accordingly, the scope of the invention should be determined only by the claims.

Claims (10)

1. A method for manufacturing an IGBT device is characterized by comprising the following steps:

providing a substrate, wherein the substrate is used as part or all of a drift region (1) of the IGBT device and has a second conduction type;

forming a first conductive type region (2) on the front surface of the substrate, or forming a first conductive type region (2) and a second conductive type region (3) on the front surface of the substrate;

forming a first trench (101) in the substrate, the first trench (101) passing through part of the first conductivity type region (2);

forming a trench gate (4) on the first trench (101), wherein the trench gate (4) comprises a gate electrode (42) and a gate dielectric layer (41) wrapping the gate electrode (42); the gate dielectric layer (41) comprises a thick gate dielectric layer (411) and a thin gate dielectric layer (412) which are respectively formed on two sides of the gate electrode (42), and the thickness of the thick gate dielectric layer (411) is larger than that of the thin gate dielectric layer (412); the thick gate dielectric layer (411) is positioned at one side close to the first conductive type region (2) and is in contact with the first conductive type region (2); in the process of forming the trench gate (4), an extraction channel (5) is formed at the part of the first conductive type region (2) contacted with the thick gate dielectric layer (411);

doping the front surface of the substrate to form a base region (6), wherein the base region (6) has a first conductivity type, and the bottom of the base region (6) is higher than the bottom of the trench gate (4);

-forming an emitter region (7) on said base region (6), said emitter region (7) having a second conductivity type; the emitting region (7) is positioned on one side of the thin gate dielectric layer (412) of the trench gate (4) and is in contact with the thin gate dielectric layer (412);

forming a first electrode (8) on the front surface of the substrate, wherein the first electrode (8) is respectively and electrically connected with the extraction channel (5), the base region (6) and the emitter region (7); the extraction channel (5) is used for extracting minority carriers at the bottom of the trench gate (4) through the first electrode (8) when the IGBT device is in an off state;

forming a collector region (9) on the back surface of the substrate, or forming a buffer layer (11) and the collector region (9) on the back surface of the substrate; -forming a second electrode (10) on the collector region (9), the second electrode (10) being electrically connected to the collector region (9), -the buffer layer (11) having a second conductivity type, -the collector region (9) having a first conductivity type, the first and second conductivity types being of different semiconductor conductivity types.

2. The manufacturing method according to claim 1, wherein forming a trench gate (4) over the first trench (101) comprises:

growing a silicon dioxide layer with a first thickness on the first groove (101) through thermal oxidation to serve as a thick gate dielectric layer (411), wherein in the process of forming the thick gate dielectric layer (411), one extraction channel (5) is formed on one side of the groove gate (4);

removing the thick gate dielectric layer (411) on the side wall of the first groove (101) far away from the first conductive type region (2);

and growing a silicon dioxide layer with a second thickness on the first trench (101) by thermal oxidation to be used as a thin gate dielectric layer (412).

3. A method of manufacturing as claimed in claim 1, characterized in that forming a region (2) of a first conductivity type on the front side of the substrate comprises:

a first doping sub-step of doping the front surface of the substrate to form a first conductivity type region (2);

an epitaxy substep of forming an epitaxial layer on the substrate, the epitaxial layer having a second conductivity type;

an epitaxial doping sub-step, doping the position of the epitaxial layer corresponding to the first conductive type region (2), and prolonging the depth of the first conductive type region (2);

the epitaxial sub-step and the epitaxial doping sub-step are repeated in sequence until the depth of the first conductivity type region (2) is extended to a first depth.

4. A method of manufacturing as claimed in claim 1, characterized in that forming a region of a first conductivity type (2) and a region of a second conductivity type (3) on the front side of the substrate comprises:

a first doping sub-step of doping the front side of the substrate to form a second conductivity type region (3);

a second doping substep of doping the front surface of the substrate to form a first conductivity type region (2);

an epitaxy substep of forming an epitaxial layer on the substrate, the epitaxial layer having a second conductivity type;

an epitaxial doping sub-step of doping the positions of the epitaxial layer corresponding to the second conductive type region (3) and the first conductive type region (2) respectively to extend the depths of the second conductive type region (3) and the first conductive type region (2);

repeating the epitaxy substep and the epitaxy doping substep in sequence until the depth of the first conductivity type region (2) is extended to a first depth and the depth of the second conductivity type region (3) is extended to a second depth.

5. A manufacturing method according to claim 1, characterized in that before forming the emitter region (7) on the base region (6), it further comprises:

forming an minority carrier barrier layer (12) under the base region (6), wherein the minority carrier barrier layer (12) is of a second conduction type, and the bottom of the minority carrier barrier layer (12) is higher than that of the trench gate (4); the extraction channel (5) is electrically connected to the first conductivity-type region (2) through the minority carrier barrier layer (12).

6. The manufacturing method according to claim 1, wherein before forming the trench gate (4) on the first trench (101), further comprising:

and forming a second conductive type lightly doped region (13) at the bottom of the first groove (101), wherein the second conductive type lightly doped region (13) is positioned at one side, far away from the first conductive type region (2), in the bottom of the first groove (101).

7. The method of manufacturing according to claim 2, wherein the thick gate dielectric layer (411) is formed by dry wet dry oxidation and/or the thin gate dielectric layer (412) is formed by dry oxygen oxidation.

8. An IGBT device produced by the production method according to any one of claims 1 to 7.

9. An IGBT device comprising at least one cell, characterized in that the cell comprises a first electrode (8), a second electrode (10) and a semiconductor unit between the first electrode (8) and the second electrode (10), the semiconductor unit comprising:

a drift region (1) having a second conductivity type for acting as a depletion layer during forward withstand voltage of the IGBT device;

a first conductivity type region (2) of a first conductivity type formed in the drift region (1), a bottom surface of the first conductivity type region (2) being remote from a top of the drift region (1) and being close to or level with a bottom of the drift region (1);

a base region (6) having a first conductivity type;

the trench gate (4) comprises a gate electrode (42) and a gate dielectric layer (41) wrapping the gate electrode (42), and the trench gate (4) penetrates through the base region (6) and extends to the drift region (1); the gate dielectric layer (41) comprises a thick gate dielectric layer (411) and a thin gate dielectric layer (412) which are respectively formed on two sides of the gate (42), and the thickness of the thick gate dielectric layer (411) is larger than that of the thin gate dielectric layer (412);

-an extraction channel (5) of a first conductivity type, the first electrode (8) being electrically connected to the region of the first conductivity type (2) through the extraction channel (5); the first electrode (8) is used for extracting minority carriers at the bottom of the trench gate (4) through the extraction channel (5) when the IGBT device is in a turn-off state;

an emitter region (7) having a second conductivity type, the first and second conductivity types being different semiconductor conductivity types, a first PN junction being formed between the emitter region (7) and the base region (6), the base region (6) and the emitter region (7) being electrically connected to the first electrode (8), respectively;

the extraction channel (5) is positioned on one side of the thick gate dielectric layer (411), and the emission region (7) is positioned on one side of the thin gate dielectric layer (412);

a collector region (9) located below the drift region (1) and having the first conductivity type, the collector region (9) being electrically connected with the second electrode (10) for providing carriers when the IGBT device is in an on-state.

10. The IGBT device according to claim 9, wherein one of the cells includes two of the trench gates (4), and the extraction channel (5) is formed between the thick gate dielectric layers (411) of two adjacent trench gates (4); and/or the acceptor doping concentration of the middle area of the extraction channel (5) is lower than that of the areas at the two ends, or the donor doping concentration of the middle area of the extraction channel (5) is higher than that of the areas at the two ends.

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