CN115361511A - On-chip real-time FPN correction method - Google Patents

Abstract

The invention relates to the technical field of image processing, in particular to an on-chip real-time FPN correction method, which comprises the following steps: s1, respectively carrying out addition calculation and quantization on reset voltage and signal voltage of an image pixel in an image signal reading stage to obtain first image information, wherein the first image information is image information subjected to related double sampling; s2, performing subtraction calculation and quantization on the reset voltage twice in the offset value extraction stage to obtain second image information, wherein the second image information is image information under a case; and S3, the image signal reading makes a difference between the first image information and the second image information, and real-time FPN correction is realized. The on-chip real-time FPN correction method can correct the FPN in real time, directly obtains the corrected result after the ADC quantization period, has low power consumption and high robustness, is insensitive to process, voltage and temperature changes, and is easy to realize the architecture.

Description

On-chip real-time FPN correction method

technical field

The invention relates to the technical field of image processing, in particular to an on-chip real-time FPN correction method.

Background technique

As the carrier of information recording, images occupy an increasingly important position in people's lives. The camera system used for image acquisition has higher and higher requirements for imaging. The core component of the imaging system is the image sensor for photosensitive imaging, and its performance index directly determines the quality of the image. The imaging process of the image sensor is as follows. First, the optical signal is captured by the photosensitive element (pixel) on the image sensor through the optical lens to form an electrical signal, and then the electrical signal is converted into a digital signal by analog and digital through the readout circuit. The digital signal is output to an off-chip composite image.

As shown in Figure 1, in the process of signal transmission, there will be noise from various parts to interfere with the signal, among which FPN (Fix Pattern Noise, fixed pattern noise) is one of the main noises, which will cause spots and longitudinal noise on the image. stripes. The generation of FPN seriously affects the imaging quality of CMOS image sensor, and becomes one of the main bottlenecks restricting the performance of CMOS image sensor.

The CMOS image sensor will use CDS (Correlated Double Sampling) or CMS (Correlated Multiple Sampling, correlated multi-sampling) to eliminate part of the FPN, that is, the fixed noise between pixel columns. The required architecture and timing of CDS are shown in Figure 2 and Figure 3 shown. ADC (Analog-to-Digital Converter, analog/digital converter) quantifies the RST voltage (reset voltage) and SIG voltage (signal voltage) of the pixel respectively, and stores the quantized digital quantity into SRAM (Static Random- Access Memory, Static Random Access Memory), in the subsequent data processing module, the difference is performed to eliminate the FPN between pixel columns and other part of the noise. However, this method cannot eliminate the FPN between columns of the readout circuit, and can only optimize the algorithm outside the chip.

Contents of the invention

In order to solve the above problems, the present invention provides an on-chip real-time FPN correction method, which can perform FPN correction on the chip, improve the imaging quality of the CMOS image sensor, and reduce the extra workload after the chip is manufactured.

The present invention provides an on-chip real-time FPN correction method, the timing in the on-chip real-time FPN correction method includes an image signal reading stage and an offset value extraction stage; the on-chip real-time FPN correction method includes steps:

S1. In the image signal reading stage, the reset voltage and the signal voltage of the image pixel are respectively added, calculated and quantized to obtain the first image information, and the first image information is the image information after correlated double sampling;

S2. In the phase of extracting the offset value, the reset voltage is subtracted and quantized twice to obtain the second image information, and the second image information is the image information in the field;

S3. Reading the image signal and making a difference between the first image information and the second image information to implement real-time FPN correction.

Preferably, the time of the image signal reading phase is the same as the time of the offset value extraction phase.

Preferably, the timing in the on-chip real-time FPN correction method is implemented through an ADC circuit structure.

Preferably, the ADC circuit structure includes a comparator, an ADC logic controller and an up-down counter.

Preferably, both the addition calculation and the subtraction calculation are realized by an up-down counter in the ADC circuit structure.

Preferably, the up-down counter includes a signal for controlling up-down counting, a clock signal, a stop counting signal, a combinational logic control signal, and an output of the counter.

Preferably, when the signal controlling up-down counting is at a high level, the up-down counter is up-counting; when the signal controlling up-down counting is at a low level, the up-down counter is down-counting.

The on-chip real-time FPN correction method of the present invention can correct the FPN in real time, obtain the corrected result directly after the ADC quantization cycle, has low power consumption, high robustness, is not sensitive to changes in process, voltage and temperature, and is relatively easy to implement . Moreover, the structure area of the ADC circuit is relatively small. By using a counter that can be added and subtracted for real-time FPN correction, it avoids the use of too many memory modules to store the quantized digital quantities of each signal voltage and reset voltage, and then does not require digital processing. module for data processing.

Description of drawings

Fig. 1 is a schematic diagram of noise classification that usually exists in a CMOS image sensor.

FIG. 2 is a schematic diagram of a single-slope ADC circuit commonly used in a CMOS image sensor.

FIG. 3 is a timing diagram of a single-slope ADC commonly used in a CMOS image sensor sampling through CDS.

FIG. 4 is a schematic diagram of a connection mode between a pixel bus and a comparator in a classic 4T pixel structure.

Fig. 5 is a schematic diagram of timing in the on-chip real-time FPN correction method in a specific embodiment of the present invention.

FIG. 6 is a schematic diagram of a circuit structure in an on-chip real-time FPN correction method in a specific embodiment of the present invention.

FIG. 7 is a schematic timing diagram of the correction process in the on-chip real-time FPN correction method in a specific embodiment of the present invention.

Fig. 8 is a schematic structural diagram of an up-down counter in an on-chip real-time FPN correction method in a specific embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention.

Each technical term mentioned in the present invention is explained as follows:

FPN: Fix Pattern Noise fixed pattern noise, the current mainstream processing structure of CMOS image sensor system is to use the column shared processing circuit, that is, each column of pixels shares a set of signal processing circuit, due to various factors such as manufacturing process and layout, the column processing circuit The mismatch between them will lead to performance deviation, so that even if the illumination on each pixel is the same, the magnitude of the output signal of the corresponding column circuit is different, that is, the fixed noise unique to the array circuit is generated. For a given single pixel, FPN is fixed, and it is different for different pixels, so this kind of noise is called fixed pattern noise.

CDS: Correlated Double Sampling, that is, sampling twice, one is the reset signal Vrst generated by the pixel, and the other is the integrated signal voltage Vsig of the pixel, and then the two signals are differentially processed to cancel part of the noise. CDS can mainly suppress noises such as 1/f and KTC in MOS circuits.

CMS: Correlated Multiple Sampling, similar to CDS, because some noise changes within a certain range with time, the noise of CDS sampling twice may not be the same, and such noise cannot be eliminated after making a difference. CMS is to calculate the average value after sampling Vrst and Vsig multiple times, so that the amount of noise carried by these two voltages tends to be more consistent. After subtracting them, the same-source or related noise and errors are finally effectively reduced.

As shown in Figure 4, it is a schematic diagram of the connection mode between the pixel bus and the comparator in the classic 4T pixel structure. It can be seen from the figure that the column bus Column bus is connected with the ramp ADC. The working process of the pixel is as follows. First, the reset tube RST is turned on, and the charge on the FD point is cleared, so that the floating node voltage Vfd of this point potential is equal to the pixel power supply voltage VDDPIX; PD is a photosensitive device, specifically a photodiode, and the received light signal Converted into an electrical signal, the voltage gradually decreases with the accumulation of electrons on its top. After the exposure is over, the TX tube is turned on, and the charge accumulated on the top of the photodiode PD is introduced into the floating node FD, causing the floating node voltage Vfd to drop. SEL is a strobe switch, which controls whether the pixels of a row are connected to the column bus. When the SEL transistor is turned on, the floating node voltage Vfd is amplified by the SF and used as the input Vpix of the ramp ADC. Usually, the pixel will output two voltage signals, one is the reset voltage Vrst, and the other is the signal voltage Vsig. The difference between the two voltages can remove the reset noise in the pixel and the compensation offset error of the comparator, which is the CDS mentioned above. However, CMS is similar to CDS. Because some noise changes within a certain range with time, the difference between the reset voltage Vrst and the signal voltage Vsig may not be able to be subtracted by sampling the difference between the reset voltage Vrst and the signal voltage Vsig once, so the reset voltage Vrst and the signal voltage Vsig are sampled multiple times. After calculating the mean, make a difference, so that the noise contained in Vrst and Vsig tends to be more equal, and the error is smaller after making a difference. Therefore, although CDS and CMS have greatly improved the image quality, they still cannot eliminate the FPN between columns.

Provide a kind of on-chip real-time FPN correction method in the specific embodiment of the present invention, the timing in the described on-chip real-time FPN correction method includes image signal reading stage and misalignment value extraction stage; Described on-chip real-time FPN correction method comprises steps:

S1. In the image signal reading stage, the reset voltage and the signal voltage of the image pixel are respectively added, calculated and quantized to obtain the first image information, and the first image information is the image information after correlated double sampling;

S2. In the phase of extracting the offset value, the reset voltage is subtracted and quantized twice to obtain the second image information, and the second image information is the image information in the field;

S3. Reading the image signal and making a difference between the first image information and the second image information to implement real-time FPN correction. Specifically, the first image information is an image acquired in a normal shooting mode, the second image information is equivalent to an image acquired in a dark field, and the difference between the information of the two images can be subtracted from the noise in the dark field image .

The timing in the on-chip real-time FPN correction method provided by the specific embodiment of the present invention is specifically shown in Figure 5, including the image signal reading phase (video signal reading phase) I and the offset value extraction phase (offsetextraction phase) II, in the image signal In the reading stage, the reset voltage Vrst and the signal voltage Vsig of the pixel are quantized, and both are added calculations; in the offset value extraction stage, Vrst is quantized twice, and both are subtracted calculations. Here, the counter of the ADC is required to have both upward and downward counting capabilities, that is, in the specific embodiment of the present invention, the ADC circuit structure includes a counter that can be added or subtracted, so that the final result can be directly obtained after quantization, and the real-time correction to the FPN can be realized. , instead of storing each result into the memory memory and then performing data processing, which can save a large part of the layout area.

In the specific implementation manner, under the time sequence of correcting FPN shown in Fig. 5, it is equivalent to acquiring two pieces of image information, one pair of normal CDS images is obtained in the first two counting stages, The counting stage obtains a pair of image information under the dark field and is specially used to extract FPN, and the FPN can be eliminated by making a difference between the two, and its specific process is as shown in Figure 7; Figure 7 is a real-time FPN on-chip in a specific embodiment of the present invention The timing diagram of the correction process in the correction method. If you want to get the best correction effect, the time in the image signal reading stage and the offset value extraction stage need to be the same, so as to obtain the same amount of FPN and then do the difference elimination, but so It will double the quantization time of the ADC. Figure 5 is only an example of one of the timings. In other implementations, according to the CMOS image sensor architecture, the image signal reading phase and the offset value extraction phase can be interchanged and adjusted. Specifically, it can be adjusted by adjusting Timing is used to adjust the image signal reading stage and the offset value extraction stage to each other, which is equivalent to doing the offset value extraction stage first, and then doing the image signal reading stage.

Fig. 6 is a schematic diagram of the circuit structure in the on-chip real-time FPN correction method in a specific embodiment of the present invention, specifically an ADC circuit structure, and the ADC circuit structure includes a comparator, an ADC logic controller and an add-subtractable counter; in Fig. 5 The timing in the on-chip real-time FPN correction method adopted can be realized by the circuit structure in Fig. 6, and the waveform of the ramp voltage Vramp in Fig. 5 is input to the same input terminal of the comparator comp, and Vramp is generated by the ramp generating circuit. The comparator comp’s reverse input terminal is connected to the pixel output signal. The connection method is shown in Figure 4. The pixel output signal is controlled by selecting SEL, resetting RST, and sending TX in Figure 5 to control the timing, and the control pixels output Vrst, Vsig, Vrst, and Vrst successively. , these signals are compared with Vramp to cause the output terminal of the comparator to flip, and generate the Conter_EN signal together with the timing control signal, as shown in Figure 7. The Counter_EN signal is a signal that controls whether the counter counts, and it is ANDed with the clock signal CLK to generate a signal required for the counter to count. The up/down counter can control whether the counter counts up or down through the Up/down control terminal. When it is high, the counter counts up, and when it is low, the counter counts down. After the counting is completed, the final value of the counter is stored in the SRAM through the Read signal. The up-down counter can be realized with the structure in Figure 8.

In a specific embodiment, the up/down counter includes a signal for controlling up/down counting, a counting clock, a stop counting signal, a combinational logic control signal, and the output of the counter; as shown in Figure 8, Up/down control is to control up/down The counting signal, when this signal is high level, all counters count up, when the signal is low level, all counters count down; CLK is the counting clock, that is, the clock signal, and the clock signal adds one bit or subtracts one on the rising edge of the clock signal One bit, plus or minus one bit is determined according to whether the Up/down control is high or low; LOCK is the stop counting signal, and the counting is stopped when the Up/down control is a low level signal, and the output is locked; CLR and SET are combined logic control signals. When CLR=1, the counts are all cleared, and when SET=1, the counts are all set to 1; BIT<0:N-1> is the output of the N-bit counter, among which, BIT<0> is the lowest bit.

The on-chip real-time FPN correction method of the present invention can correct the FPN in real time, obtain the corrected result directly after the ADC quantization cycle, has low power consumption, high robustness, is not sensitive to changes in process, voltage and temperature, and is relatively easy to implement . Moreover, the structure area of the ADC circuit is relatively small. By using a counter that can be added and subtracted for real-time FPN correction, it avoids the use of too many memory modules to store the quantized digital quantities of each signal voltage and reset voltage, and then does not require digital processing. module for data processing.

Although the embodiments of the present invention have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limitations on the present invention. Those skilled in the art can make changes, modifications, substitutions and modifications to the above-mentioned embodiments within the scope of the present invention.

The above specific implementation manners of the present invention do not constitute a limitation to the protection scope of the present invention. Any other corresponding changes and modifications made according to the technical concept of the present invention shall be included in the protection scope of the claims of the present invention.

Claims (7)

1. a real-time FPN correction method on a chip, it is characterized in that, the timing in the real-time FPN correction method on the described chip comprises image signal reading stage and offset value extraction stage; The real-time FPN correction method on the described chip comprises steps: S1. In the image signal reading stage, the reset voltage and the signal voltage of the image pixel are respectively added, calculated and quantized to obtain the first image information, and the first image information is the image information after correlated double sampling; S2. In the phase of extracting the offset value, the reset voltage is subtracted and quantized twice to obtain the second image information, and the second image information is the image information in the field; S3. Reading the image signal and making a difference between the first image information and the second image information to implement real-time FPN correction. 2. The on-chip real-time FPN correction method according to claim 1, wherein the time of the image signal reading phase is the same as the time of the offset value extraction phase. 3. The on-chip real-time FPN correction method according to claim 1, wherein the timing in the on-chip real-time FPN correction method is realized by an ADC circuit structure. 4. The on-chip real-time FPN correction method according to claim 1, wherein the ADC circuit structure includes a comparator, an ADC logic controller, and an up-down counter. 5. The on-chip real-time FPN correction method according to claim 1, characterized in that, both the addition calculation and the subtraction calculation are realized by an add-subtractable counter in the ADC circuit structure. 6. The on-chip real-time FPN correction method as claimed in claim 1, wherein the up-down counter includes a signal for controlling up-down counting, a clock signal, a stop counting signal, a combinational logic control signal and the output of the counter. 7. on-chip real-time FPN correcting method as claimed in claim 6, is characterized in that, when the signal of described control addition and subtraction counting is high level, described addition and subtraction counter is counting up; The signal of described control addition and subtraction counting When the level is low, the up-down counter is down-counting.

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