CN115361074B - Carrier-free ultra-wideband time control array technology verification system - Google Patents
Carrier-free ultra-wideband time control array technology verification system Download PDFInfo
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Abstract
The invention provides a system for verifying a carrier-free ultra-wideband time control array technology, and belongs to the technical field of carrier-free ultra-wideband time control arrays. The system comprises: the system comprises an upper computer, monitoring and control software, a lower computer central control unit, a clock forming circuit, an ultra-wideband antenna array, a signal transmitting module, a signal receiving module and a high-speed receiving and transmitting switch. The invention solves the problems that no carrier ultra-wideband array module or related verification system is lacking at home and abroad at present, researchers in the field can not acquire real echo data and can not verify processing algorithms of various UWB signals, and the verification system has the advantages of high difficulty in construction, high cost and difficulty in realization of universality, and has low cost and meets personalized requirements.
Description
Technical Field
The invention relates to the technical field of carrier-free ultra-wideband time control arrays, in particular to a carrier-free ultra-wideband time control array technical verification system.
Background
Phased array radar and array antenna technology thereof are mature at present, and related products and equipment are many. The technology and the equipment mainly adopt pulse signals with large time and bandwidth products, the duration of a single signal is tens to hundreds of microseconds, and the phase shifter is used for realizing the in-phase synthesis of multiple paths of signals, so that the purposes of improving the gain, compressing the beam width and controlling the beam direction are achieved. But the method and the technology cannot be popularized and applied to a carrier-free Ultra Wideband (UWB) impulse system. The pulse width of the UWB signal is only of nanosecond order, the bandwidth reaches gigahertz, the conventional phase shifter cannot cover such a large bandwidth, and serious dispersion problems occur after the UWB pulse passes through the conventional phase shifter, so that time domain waveform distortion is caused, and the dispersion severity degree caused by different phase shifters is different, namely the distortion degree is different. Thus, existing phase-controlled array techniques are not suitable for a carrierless Ultra Wideband (UWB) regime.
The current carrier-free Ultra Wideband (UWB) technology is widely applied to various fields such as radar, fuze, logistics, automobiles, positioning, anti-terrorism, emergency rescue, medical treatment and the like. The carrier-free ultra-wideband time control array technology comprises the following steps: the technical fields of carrierless ultra-wideband radar, ultra-wideband radio detector, ultra-wideband positioning, ultra-wideband communication and the like. Terminals in the application fields are basically single-shot and single-received architecture, the dimension of information acquisition is small, and the terminals can only simply measure distance (or time), omnidirectionally radiate communication or roughly orient. If accurate target positioning of a single station is to be achieved, with spatial target search and scanning capabilities, UWB array technology must be developed. Currently, UWB related array technologies and systems have few reports, and related test systems and verification systems are lacking, so that the technology in the field is seriously hindered from exploring and advancing due to high technical thresholds and great difficulty in design and development of the UWB array systems.
Disclosure of Invention
The invention solves the technical problems that: at present, no carrier Ultra Wideband (UWB) array module or related verification system is lacking at home and abroad, so that researchers in the field cannot acquire real echo data and cannot verify processing algorithms of various UWB signals, and the verification system is difficult to construct, high in cost and not universal.
In order to solve the problems, the technical scheme of the invention is as follows:
A kind of carrierless ultra-wideband time control array technology verification system, through ps-stage time control, has realized a kind of signal transmission that can be flexibly configured and received the time control array, include specifically:
the upper computer is used for controlling and monitoring and verifying the working state and the execution condition of the system in real time, the upper computer is provided with monitoring and control software,
The lower computer central control unit is used for receiving the control instruction of the upper computer and forwarding the control instruction after analyzing, the lower computer central control unit operates on the embedded processor, the lower computer central control unit carries out bidirectional communication with the monitoring and control software through a serial port,
The clock forming circuit is used for determining the working time reference of the lower computer central control unit and carrying out bidirectional communication with the lower computer central control unit through an SPI interface,
An ultra-wideband antenna array for transceiving signals, the ultra-wideband antenna array comprising: a plurality of transmitting channels for transmitting signals and a plurality of receiving channels for receiving signals, wherein the transmitting channels are internally provided with a second ps-stage program-controlled delay device, the receiving channels are internally provided with a third ps-stage stepping program-controlled delay chip,
The signal transmitting module is electrically connected with the clock forming circuit, and comprises:
A transmitting time sequence control circuit for realizing the time coordination of transmitting signals of each transmitting channel, a multi-path UWB waveform generator electrically connected with the transmitting time sequence control circuit and receiving the output signals of the clock forming circuit, a multi-path radio frequency transmitter for generating ultra-wideband impulse pulses, the multi-path radio frequency transmitter electrically connected with the UWB waveform generator and receiving the output signals of the UWB waveform generator, the multi-path radio frequency transmitter is built by a band-pass filter and a radio frequency amplifier,
The signal receiving module is electrically connected with the clock forming circuit, and comprises:
The receiving time sequence control circuit is used for realizing the time coordination of the receiving signals of all receiving channels, the receiving time sequence control circuit is electrically connected with the clock forming circuit and receives the output signals of the clock forming circuit, the sampling and holding circuit is electrically connected with the receiving time sequence control circuit and acquires the output switching pulse signals of the receiving time sequence control circuit, the sampling and holding circuit converts the output of the multipath radio frequency receiver into the intermediate frequency pulse signals by using the switching pulse signals, the multipath radio frequency receiver is electrically connected with the sampling and holding circuit and outputs the signals to the sampling and holding circuit, the intermediate frequency filter amplifying circuit is used for amplifying the intermediate frequency signals output by the sampling and holding circuit and filtering out the out-of-band interference signals and outputting the multichannel intermediate frequency signals, the intermediate frequency filter amplifying circuit is electrically connected with the sampling and holding circuit and receives the output signals of the sampling and holding circuit and is used for superposing and synthesizing the multichannel intermediate frequency signals to form an intermediate frequency echo synthesizing circuit which synthesizes one path of intermediate frequency signals, the intermediate frequency echo synthesizing circuit is electrically connected with the intermediate frequency filter amplifying circuit,
The high-speed receiving and transmitting switch is used for realizing the multiplexing of the ultra-wideband antenna array and the nanosecond switching of the electrical connection with the ultra-wideband antenna array, the high-speed receiving and transmitting switch is electrically connected with the signal transmitting module and the signal receiving module, the multipath radio frequency transmitter transmits the output multipath UWB transmitting signals to the high-speed receiving and transmitting switch, the multipath radio frequency transmitter is electrically connected with the high-speed receiving and transmitting switch,
The high-speed receiving and transmitting switch outputs the received multipath UWB transmitting signals to the ultra-wideband antenna array and transmits the signals through the ultra-wideband antenna array,
The ultra-wideband antenna array outputs the received signal to the high-speed receiving and transmitting switch, the high-speed receiving and transmitting switch inputs the received signal to the multi-path radio frequency receiver, the multi-path radio frequency receiver is electrically connected with the high-speed receiving and transmitting switch,
The lower computer central control unit performs unidirectional control on the clock shaping circuit, the transmitting time sequence control circuit, the receiving time sequence control circuit and the high-speed receiving and transmitting switch through control signals.
In the verification system, the carrier-free ultra-wideband time control array technology comprises carrier-free ultra-wideband radar, an ultra-wideband radio detector, ultra-wideband positioning, ultra-wideband communication and other technologies.
In the verification system, the monitoring and control software carried by the upper computer controls the pointing directions of the transmitting beam and the receiving beam, controls the beam scanning stepping and scanning range of the transmitting beam and the receiving beam, and monitors the working state and the instruction execution condition of the verification system.
The transmitting beam is obtained by the vector superposition of the spatial multipath signals after the signals of all transmitting channels are radiated by the antennas. The resulting transmit beam has a shape, which is typically a plot of the intensity of the spatially synthesized signal as a function of angle.
The receiving wave beam is obtained by mutually vector superposition of spatial multipath signals, the receiving wave beam is characterized in that the receiving signals in certain directions are large, the signals in certain directions are weak, and the strength change is the spatial shape of the receiving wave beam.
In the verification system, clock signals output by the clock forming circuit are provided for a multi-channel radio frequency receiver, a multi-channel radio frequency transmitter, a high-speed receiving and transmitting switch and a lower computer central control unit through a distribution network, and the components work cooperatively according to the clock signals to ensure normal receiving and transmitting of the signals.
In the verification system, the multi-channel radio frequency transmitter realizes the generation of ultra-wideband impulse, and simultaneously realizes the power amplification of ultra-wideband impulse signals of all channels, the filtering of the transmitted impulse and the waveform control.
In the verification system, the multi-path radio frequency receiver comprises a low noise amplifier, a band-pass filter, a sample-hold circuit and an intermediate frequency filter amplifying circuit, and the multi-path radio frequency receiver converts UWB narrow pulses into intermediate frequency pulse signals, and the pulse width is widened, so that the follow-up signal acquisition, storage and data observation are convenient.
The intermediate frequency echo synthesis circuit can judge whether a target exists or not and the accurate spatial position of the target through the acquisition and analysis of intermediate frequency synthesized echoes in different scanning angles.
Further, the ps-scale indicates that the delay step is not more than 10ps.
Further, the clock forming circuit includes: the system comprises a clock circuit, a first clock distributor electrically connected with an output end of the clock circuit, a ps-stage program-controlled delay device electrically connected with the output end of the first clock distributor, and a second clock distributor electrically connected with the output end of the ps-stage program-controlled delay device, wherein the clock circuit is built by a free-running oscillator and a clock shaping circuit electrically connected with the electrical output end of the free-running oscillator.
Furthermore, the intermediate frequency echo synthesis circuit realizes the analog receiving wave beam synthesis through the addition circuit, has the amplitude control capability for the intermediate frequency processing part of each receiving channel, and provides conditions and basis for the verification of the optimization algorithm of various receiving wave beams.
Further, the high-speed transceiver switch is a single-pole double-throw switch with ns-level switching speed, wherein ns-level is nanosecond-level. Under the control of the clock signal output by the clock forming circuit, the high-speed receiving and transmitting switch realizes the fast switching of single-pole double-throw, and is switched to a multi-channel radio frequency transmitter when transmitting the wave beam and to a multi-channel radio frequency receiver when receiving the wave beam. Because the high-speed receiving and transmitting switch is nanosecond switching speed, the verification system is guaranteed to have a small blind area (not more than 3 m) which is far smaller than the blind area range of at least hundred meters of the existing pulse radar.
Further, the transmitting time sequence control circuit outputs the working time sequence of each transmitting channel through a second ps-stage program control delay device in each transmitting channel, and the receiving time sequence control circuit outputs the working time sequence of each receiving channel through a third ps-stage step program control delay chip in each receiving channel.
Preferably, the process of the transmission time sequence control circuit for realizing the time coordination of the transmission signals of the transmission channels comprises the following steps:
The transmission time sequence control circuit executes the control signal of the lower computer central control unit, sets the transmission time difference of the transmission signals of each transmission channel as delta t 1, and differentiates the direction of the transmission beam, wherein the calculation formula of the direction of the transmission beam is as follows:
In the above formula, θ 1 is the pointing angle of the transmitting beam, Δt 1 is the transmitting time difference, d 1 is the distance difference between the adjacent 2 transmitting channels, and c is the propagation speed of the electromagnetic wave.
Preferably, the process of the receiving timing control circuit for realizing the time coordination of the receiving signals of the receiving channels comprises the following steps:
The receiving time sequence control circuit executes the control signal of the lower computer central control unit, sets the receiving time difference of the receiving signals of each receiving channel as delta t 2, and differentiates the receiving beam direction, wherein the calculating formula of the receiving beam direction is as follows:
In the above formula, θ 2 is the direction angle of the received beam, Δt 2 is the receiving time difference, d 2 is the distance difference between 2 adjacent receiving channels, and c is the propagation speed of the electromagnetic wave.
Preferably, the ultra-wideband array antenna is mounted on a one-dimensional or two-dimensional guide rail capable of continuously sliding, and each antenna port of the ultra-wideband array antenna is electrically connected with a common port of the high-speed receiving and transmitting switch through an equal-length coaxial cable.
Further preferably, the multipath radio frequency receiver is reserved with an intermediate frequency signal acquisition interface of each receiving channel and an intermediate frequency echo acquisition interface for synthesizing intermediate frequency signals.
The beneficial effects of the invention are as follows:
(1) The invention fills the blank of the non-UWB time control array verification system at home and abroad, the system has flexible control mode and universal interface, adopts modularized design, has compact structure, low cost and strong universality, and promotes the technical research and progress of the UWB field. The verification system can be popularized and applied to technology and experimental research in the fields of ultra-wideband system radar, ultra-wideband radio detector, ultra-wideband positioning, communication and the like;
(2) The invention realizes an active time control (time control for short) UWB array system, each transmitting and receiving branch circuit comprises a time sequence control and active amplifying component, and can simultaneously meet the verification requirement of transmitting beam synthesis and the verification requirement of receiving beam synthesis;
(3) The array antenna spacing can be flexibly adjusted, an operator can adjust the unit distribution according to the requirement, and various density weighting algorithms and sparse array algorithms can be verified, so that the influence of the array element spacing on the performance of the synthetic beam can be analyzed;
(4) The invention adopts a low-cost UWB pulse generation technology and a delay control technology based on a low-rate clock, avoids an expensive radio frequency delay device, and greatly reduces the realization cost of a multi-channel radio frequency transmitter; the invention adopts the sample-hold circuit, realizes the time delay of receiving UWB pulse by the delay control of the sampling pulse time, avoids the expensive radio frequency delay device and greatly reduces the realization cost of the multipath radio frequency receiver;
(5) The multipath radio frequency receiver reserves an intermediate frequency signal acquisition interface of each channel and a synthesized intermediate frequency echo acquisition interface, thereby meeting the personalized requirements of users in the aspects of analog beam synthesis and digital beam synthesis.
Drawings
FIG. 1 is a system frame diagram of a carrierless ultra wideband time-controlled array technical verification system of example 1;
Fig. 2 is an internal structure and an operation schematic diagram of the clock forming circuit of embodiment 1;
fig. 3 is a mechanism diagram of an ultra wideband antenna array of embodiment 1;
Fig. 4 is an internal structure and an operation schematic diagram of the intermediate frequency echo synthesis circuit of embodiment 1.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two.
It should be understood that although the terms first, second, third, etc. may be used in describing … … in embodiments of the present invention, these … … should not be limited to these terms. These terms are only used to distinguish … …. For example, the first … … may also be referred to as the second … …, and similarly the second … … may also be referred to as the first … …, without departing from the scope of embodiments of the present invention.
Example 1
The embodiment is a carrierless ultra-wideband time control array technology verification system, and realizes a flexibly configurable signal transmitting and receiving time control array through ps-level time control, as shown in fig. 1, which specifically comprises:
The upper computer is used for controlling and monitoring and verifying the working state and the execution condition of the system in real time, and is provided with monitoring and control software.
The monitoring and control software carried by the upper computer controls the pointing directions of the transmitting beam and the receiving beam, controls the beam scanning stepping and scanning range of the transmitting beam and the receiving beam, and monitors and verifies the working state and the instruction execution condition of the system.
And the lower computer central control unit is used for receiving the control instruction of the upper computer and forwarding the control instruction after analyzing, and operates on the embedded processor, and the lower computer central control unit is in bidirectional communication with the monitoring and control software through a serial port.
The clock forming circuit is used for determining the working time reference of the lower computer central control unit and carrying out bidirectional communication with the lower computer central control unit through an SPI interface, and comprises: the system comprises a clock circuit, a first clock distributor electrically connected with an output end of the clock circuit, a ps-stage program-controlled delay device electrically connected with the output end of the first clock distributor, and a second clock distributor electrically connected with the output end of the ps-stage program-controlled delay device, wherein the clock circuit is built by a free-running oscillator and a clock shaping circuit electrically connected with the electrical output end of the free-running oscillator.
The clock signal output by the clock forming circuit is provided for the multipath radio frequency receiver, the multipath radio frequency transmitter, the high-speed receiving and transmitting switch and the lower computer central control unit through the distribution network, and the components work cooperatively according to the clock signal, so that the normal receiving and transmitting of the signals are ensured.
The clock forming circuit is used for providing a unified time reference for each channel in the verification system, which is the premise that each array channel can work cooperatively, and a square wave signal with fixed frequency is generated by the free-running oscillator and the clock shaping circuit and is used as a clock signal of the whole time-controlled array system, and the principle of the clock forming circuit is shown in fig. 2.
An ultra-wideband antenna array for transceiving signals, the ultra-wideband antenna array comprising: five paths of transmitting channels for transmitting signals and five paths of receiving channels for receiving signals, wherein the transmitting channels are identical to the receiving channels. The transmitting channel is internally provided with a second ps-stage program control delay device, and the receiving channel is internally provided with a third ps-stage stepping program control delay chip.
The signal transmitting module is electrically connected with the clock forming circuit, and comprises:
the transmission time sequence control circuit is used for realizing the time coordination of the transmission signals of all transmission channels, and the process of realizing the time coordination of the transmission signals of all transmission channels by the transmission time sequence control circuit comprises the following steps:
The transmission time sequence control circuit executes the control signal of the lower computer central control unit, sets the transmission time difference of the transmission signals of each transmission channel as delta t 1, and differentiates the direction of the transmission beam, wherein the calculation formula of the direction of the transmission beam is as follows:
In the above formula, θ 1 is the pointing angle of the transmitting beam, Δt 1 is the transmitting time difference, d 1 is the distance difference between the adjacent 2 transmitting channels, and c is the propagation speed of the electromagnetic wave.
The transmission time sequence control circuit is electrically connected with the clock forming circuit and receives the output signal of the clock forming circuit, the multi-channel UWB waveform generator is electrically connected with the transmission time sequence control circuit and receives the output signal of the transmission time sequence control circuit, the multi-channel radio frequency transmitter is used for generating ultra-wideband impulse pulses, the multi-channel radio frequency transmitter is electrically connected with the UWB waveform generator and receives the output signal of the UWB waveform generator, the multi-channel radio frequency transmitter is built through a band-pass filter and a radio frequency amplifier, and the transmission time sequence control circuit outputs the working time sequence of each transmission channel through a second ps-stage program-controlled delay in each transmission channel.
The multi-channel radio frequency transmitter realizes the generation of ultra-wideband impulse, and simultaneously realizes the power amplification of ultra-wideband impulse signals of all channels, the filtering of transmitting impulse and the waveform control.
The signal receiving module is electrically connected with the clock forming circuit, and comprises:
The receiving time sequence control circuit is used for realizing the time coordination of the receiving signals of all receiving channels, and the process of the receiving time sequence control circuit for realizing the time coordination of the receiving signals of all receiving channels comprises the following steps:
The receiving time sequence control circuit executes the control signal of the lower computer central control unit, sets the receiving time difference of the receiving signals of each receiving channel as delta t 2, and differentiates the receiving beam direction, wherein the calculating formula of the receiving beam direction is as follows:
In the above formula, θ 2 is the direction angle of the received beam, Δt 2 is the receiving time difference, d 2 is the distance difference between 2 adjacent receiving channels, and c is the propagation speed of the electromagnetic wave.
The receiving time sequence control circuit is electrically connected with the clock forming circuit and receives a clock forming circuit output signal, the clock forming circuit is electrically connected with the receiving time sequence control circuit and acquires a sampling and holding circuit for receiving the switching pulse signal output by the receiving time sequence control circuit, the sampling and holding circuit converts the output of the multi-path radio frequency receiver into an intermediate frequency pulse signal by utilizing the switching pulse signal, the multi-path radio frequency receiver is electrically connected with the sampling and holding circuit and outputs the signal to the sampling and holding circuit, the intermediate frequency filter amplifying circuit is used for amplifying the intermediate frequency signal output by the sampling and holding circuit and outputting a multi-channel intermediate frequency signal, the intermediate frequency filter amplifying circuit is electrically connected with the sampling and holding circuit and is used for superposing and synthesizing the multi-channel intermediate frequency signal to form an intermediate frequency echo synthesizing circuit for synthesizing the intermediate frequency signal, the receiving time sequence control circuit outputs the working time sequence of each receiving channel through a third ps-stage step program control delay chip in each receiving channel, and the multi-path radio frequency receiver is provided with an intermediate frequency signal acquisition interface of each receiving channel and an intermediate frequency echo acquisition reserved interface for synthesizing the intermediate frequency signal.
The intermediate frequency echo synthesis circuit can judge whether a target exists or not and the accurate spatial position of the target through the acquisition and analysis of intermediate frequency synthesized echoes in different scanning angles.
The intermediate frequency echo synthesis circuit realizes analog receiving wave beam synthesis through the addition circuit, has amplitude control capability for the intermediate frequency processing part of each receiving channel, and provides conditions and basis for the verification of the optimization algorithm of various receiving wave beams.
The multi-channel radio frequency receiver comprises a low noise amplifier, a band-pass filter, a sample hold circuit and an intermediate frequency filter amplifying circuit, and converts UWB narrow pulses into intermediate frequency pulse signals, and the pulse width is widened, so that subsequent signal acquisition, storage and data observation are facilitated.
The high-speed receiving and transmitting switch is used for realizing nanosecond switching of ultra-wideband antenna array multiplexing and is electrically connected with the ultra-wideband antenna array, the high-speed receiving and transmitting switch is electrically connected with the signal transmitting module and the signal receiving module, the multipath radio frequency transmitter transmits output multipath UWB transmitting signals to the high-speed receiving and transmitting switch, the multipath radio frequency transmitter is electrically connected with the high-speed receiving and transmitting switch, and the high-speed receiving and transmitting switch is a single-pole double-throw switch with ns-level switching speed.
The high-speed receiving and transmitting switch outputs the received multipath UWB transmitting signals to the ultra-wideband antenna array and transmits the multipath UWB transmitting signals through the ultra-wideband antenna array.
The ultra-wideband antenna array outputs a received signal to the high-speed receiving and transmitting switch, the high-speed receiving and transmitting switch inputs the received signal to the multi-channel radio frequency receiver, the multi-channel radio frequency receiver is electrically connected with the high-speed receiving and transmitting switch, the ultra-wideband antenna array is arranged on a one-dimensional guide rail capable of continuously sliding, and each antenna port of the ultra-wideband antenna array is electrically connected with a common port of the high-speed receiving and transmitting switch through an equal-length coaxial cable.
The lower computer central control unit performs unidirectional control on the clock shaping circuit, the transmitting time sequence control circuit, the receiving time sequence control circuit and the high-speed receiving and transmitting switch through control signals.
In the verification system of the present embodiment, ps-level means that the delay step is not more than 10ps.
The hardware of the verification system of this embodiment includes: a hardware circuit with a shielding shell and an ultra-wideband antenna array with a guide rail.
The upper computer, the lower computer, the clock forming circuit, the signal transmitting module, the signal receiving module and the high-speed receiving and transmitting switch are integrated on a circuit board and are arranged in the metal shielding shell, so that the high-speed receiving and transmitting switch has a good shielding effect on external interference signals. The power line and the signal control line are led out through the side connector of the shielding shell, and the multipath radio frequency signals are transmitted to the antenna through the SMA connector.
The ultra-wideband antenna array consists of five identical index gradual change slot antennas, which is a typical ultra-wideband antenna, and the antenna array structure is shown in figure 3, wherein five identical Vivaldi antennas are fixed on a guide rail, and the positions of the antennas can be manually adjusted, so that the distance between the antennas and the caliber of the antenna array are changed, and the tail part of the antenna is welded with an SMA joint which can be connected with a coaxial cable.
The working process of the verification system of the embodiment comprises the following steps:
S1, monitoring and control software sends a control signal of a transmitting beam to a lower computer central control unit through a serial port, the lower computer central control unit analyzes the control instruction and then forwards the control instruction to a transmitting time sequence control circuit, and the time reference of subsequent transmitting beam synthesis, scanning and detecting distance adjustment is unified, as shown in fig. 2, and specifically comprises the following contents:
The clock circuit outputs a reference clock signal, the reference clock signal generates six identical clock signals through a first clock distributor, wherein five clock signals enter a multi-channel radio frequency transmitter, the other clock signals enter a first ps-stage program-controlled delay device, the first ps-stage program-controlled delay device controls the detection distance of the ultra-wideband antenna array, the clock signals delayed by the first ps-stage program-controlled delay device generate five identical clock signals through a second clock distributor and enter each receiving channel, and therefore the time standard of the system is verified to be uniform;
S2, under the reference of clock signals, the second ps-stage program-controlled delayers change the time when the clock signals of the respective transmitting channels enter the UWB waveform generator, so that the ultra-wideband transmitting signals of the transmitting channels and the time reference of the clock circuit generate required time delay, and the generated ultra-wideband signals are filtered and amplified by the multipath radio frequency transmitters to reach the high-speed receiving and transmitting switch;
S3, when the high-speed receiving and transmitting switch is switched to a transmitting state, the ultra-wideband antenna array transmits ultra-wideband signals outwards, in a receiving channel, a clock signal generated by the clock forming circuit is used as a time reference, and the third ps-stage program control delayer can change the moment when the clock signal reaches the receiving time sequence control circuit, so that a required delay amount is generated between the generated sampling pulse and the time reference of the clock circuit;
s4, when the high-speed receiving and transmitting switch is switched to a receiving state, echo signals received by the ultra-wideband antenna array enter a multipath radio frequency receiver, and are converted into intermediate frequency signals after being filtered, amplified and sample-and-hold processed by the multipath radio frequency receiver;
S5, the intermediate frequency echo synthesis circuit carries out amplitude weighting treatment on five intermediate frequency signals received by the multipath radio frequency receiver, the intermediate frequency echo synthesis circuit is shown in fig. 4, the five intermediate frequency signals enter the addition circuit for synthesis after amplitude control, the effect of simulating received wave beam synthesis is achieved, meanwhile, the five intermediate frequency signals can be respectively collected and stored, and digital wave beam synthesis is realized in a digital domain.
(1) Verification of the present embodiment for transmit beam synthesis and scanning
The embodiment transmits five paths of ultra-wideband signals generated by the verification system into free space through five antennas, and performs space transmission beam synthesis in a far field. When the program control delay of each transmitter is consistent, the direction angle of the transmitting beam is 0 DEG, and when the direction angle of the transmitting beam needs to be changed, the clock delay amount of the transmitting time sequence control circuit is controlled by the upper computer, so that the direction control of the transmitting beam is realized, and the aim of scanning the transmitting beam is fulfilled.
The antenna spacing of an ultra wideband antenna array is typically set to about 0.05 meters at half the wavelength of the center frequency of the transmitted signal. An antenna is here understood to be an array element. Therefore, when the array element spacing is determined to be d=0.05 meter and the beam pointing angle is determined to be θ, the wave path difference between the adjacent array elements can be calculated to be Δr=dsin θ, and further the delay difference between the adjacent array elements can be calculated to be Δt=dsin θ/c. Where c is the propagation velocity of the electromagnetic wave.
Such as: when the beam pointing angle is 0 degree, signals are emitted between the array elements and radiated outwards, the delay amount between the signals is 0ps, and at the moment, the emitted signals between two adjacent array elements are overlapped in time waveform.
Due to the restriction of engineering delay technology, ideal delay amount is difficult to realize in engineering application, and the delay chip in the current mainstream can achieve delay amount taking 10ps as step. In this embodiment, the correspondence between the delay amount and the beam pointing angle between adjacent array elements of the system is verified, as shown in columns 1 and 2 of table 1.
TABLE 1 comparison of beam pointing angle and delay of adjacent array elements
Meanwhile, the accurate control delay is the core of the verification system in the embodiment capable of working normally, and is also the basis of beam forming and scanning.
In the hardware circuit, the minimum delay step of the delay chip is 10ps, and when a certain beam pointing angle needs to be configured, the delay amount of adjacent array elements is not integer decimal, for example: when the beam pointing angle is-30 degrees, the delay amount of the adjacent array elements is-83.33 ps, and the hardware delay amount can only meet-80 ps or-90 ps, in order to be as close as possible to the theoretically calculated delay amount, a rounding method is adopted in program control delay configuration to reduce the error between the theoretically calculated delay amount and the actual delay amount, and the actual delay amounts of the adjacent array elements corresponding to different beam pointing angles are shown in the 3 rd column of the table 1.
(2) Verification of the present embodiment for receive beamforming and scanning
The verification system of the embodiment changes the sampling pulse position by changing the program-controlled delay amount of the receiving time sequence control circuit, thereby ensuring that the received echo signal can pass through the sampling and holding circuit, and the signal is processed into an intermediate frequency signal.
The intermediate frequency signals received by the five paths of receiving channels are synthesized by an intermediate frequency echo synthesis circuit, one path of synthesized intermediate frequency signals is output, a time domain waveform diagram of the signals is displayed on an oscilloscope or other terminals, and the peak values of the synthesized intermediate frequency signals at different angles can be recorded through scanning of a time-controlled array, so that a receiving beam synthesized direction diagram is obtained.
The verification system of the embodiment can measure amplitude inconsistency and delay inconsistency between each transmitting channel and each receiving channel in advance, compensates and calibrates the amplitude inconsistency and the delay inconsistency by a software method, and ensures the accuracy of subsequent use.
Example 2
The present embodiment is a carrierless ultra wideband time-controlled array technology verification system, and the difference between the present embodiment and embodiment 1 is that:
The ultra-wideband array antenna is mounted on a continuously slidable two-dimensional guide rail.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, or scale changes made within the spirit and principles of the present invention should be included within the scope of the present invention.
Claims (9)
1. The utility model provides a no carrier ultra wide band time control array technique verification system which characterized in that through ps level time control, realized a signal transmission and receipt time control array that can flexibly dispose specifically includes:
The upper computer is used for controlling and monitoring the working state and the execution condition of the verification system in real time, the upper computer is provided with monitoring and control software,
The lower computer central control unit is used for receiving the control instruction of the upper computer and forwarding the control instruction after analyzing, the lower computer central control unit operates on the embedded processor, the lower computer central control unit carries out bidirectional communication with the monitoring and control software through a serial port,
The clock forming circuit is used for determining the working time reference of the lower computer central control unit and carrying out bidirectional communication with the lower computer central control unit through an SPI interface,
An ultra-wideband antenna array for transceiving signals, the ultra-wideband antenna array comprising: the plurality of paths of transmitting channels for transmitting signals and the plurality of paths of receiving channels for receiving signals are arranged in the transmitting channels, the second ps-stage program control delay device is arranged in the receiving channels, the third ps-stage step program control delay chip is arranged in the receiving channels,
The signal transmitting module is electrically connected with the clock forming circuit, and comprises:
A transmitting time sequence control circuit for realizing the time coordination of transmitting signals of the transmitting channels, wherein the transmitting time sequence control circuit is electrically connected with the clock forming circuit and receives the output signals of the clock forming circuit, a multi-path UWB waveform generator electrically connected with the transmitting time sequence control circuit and receiving the output signals of the transmitting time sequence control circuit, a multi-path radio frequency transmitter for generating ultra-wideband impulse pulses, the multi-path radio frequency transmitter is electrically connected with the UWB waveform generator and receives the output signals of the UWB waveform generator, the multi-path radio frequency transmitter is built by a band-pass filter and a radio frequency amplifier,
The signal receiving module is electrically connected with the clock forming circuit, and comprises:
The receiving time sequence control circuit is used for realizing the time coordination of the receiving signals of each receiving channel, the receiving time sequence control circuit is electrically connected with the clock forming circuit and receives the output signals of the clock forming circuit, the sampling and holding circuit is electrically connected with the receiving time sequence control circuit and acquires the output switching pulse signals of the receiving time sequence control circuit, the sampling and holding circuit converts the output of the multipath radio frequency receiver into the intermediate frequency pulse signals by using the switching pulse signals, the multipath radio frequency receiver is electrically connected with the sampling and holding circuit and outputs the signals to the sampling and holding circuit, the intermediate frequency filter amplifying circuit is used for amplifying the intermediate frequency signals output by the sampling and holding circuit and filtering out-of-band interference signals and outputting multichannel intermediate frequency signals, the intermediate frequency filter amplifying circuit is electrically connected with the sampling and holding circuit and receives the output signals of the sampling and holding circuit and is used for carrying out superposition synthesis on the multichannel intermediate frequency signals to form an intermediate frequency echo synthesizing circuit which synthesizes the intermediate frequency signals, the intermediate frequency echo synthesizing circuit is electrically connected with the intermediate frequency filter amplifying circuit,
The high-speed receiving and transmitting switch is used for realizing the multiplexing of the ultra-wideband antenna array and nanosecond switching which is electrically connected with the ultra-wideband antenna array, the high-speed receiving and transmitting switch is electrically connected with the signal transmitting module and the signal receiving module, the multipath radio frequency transmitter transmits the output multipath UWB transmitting signals to the high-speed receiving and transmitting switch, the multipath radio frequency transmitter is electrically connected with the high-speed receiving and transmitting switch,
The high-speed receiving and transmitting switch outputs the received multipath UWB transmitting signals to the ultra-wideband antenna array and transmits the signals through the ultra-wideband antenna array,
The ultra-wideband antenna array outputs the received signals to the high-speed receiving and transmitting switch, the high-speed receiving and transmitting switch inputs the received signals to the multi-path radio frequency receiver, the multi-path radio frequency receiver is electrically connected with the high-speed receiving and transmitting switch,
The lower computer central control unit performs unidirectional control on the clock forming circuit, the transmitting time sequence control circuit, the receiving time sequence control circuit and the high-speed receiving and transmitting switch through control signals.
2. A carrierless ultra-wideband time-controlled-array technology verification system as recited in claim 1, wherein the ps-scale representation is a delay step of no more than 10ps.
3. The carrierless ultra-wideband time-controlled array technology verification system of claim 1, wherein the clock forming circuit comprises: the system comprises a clock circuit, a first clock distributor electrically connected with an output end of the clock circuit, a first ps-stage program-controlled delay device electrically connected with the output end of the first clock distributor, and a second clock distributor electrically connected with the output end of the first ps-stage program-controlled delay device, wherein the clock circuit is built by a free-running oscillator and a clock shaping circuit electrically connected with the electrical output end of the free-running oscillator.
4. The system of claim 1, wherein the intermediate frequency echo synthesis circuit implements analog receive beam synthesis via an adder circuit.
5. The carrierless ultra-wideband time-controlled array technology verification system of claim 1, wherein the high-speed transmit-receive switch is a single pole double throw switch with ns-level switching speed.
6. The system of claim 1 wherein said transmit timing control circuit outputs the operating timing of each transmit channel through a second ps-stage programmable delay in each transmit channel, and said receive timing control circuit outputs the operating timing of each receive channel through a third ps-stage programmable delay chip in each receive channel.
7. The system of claim 1, wherein the process of implementing time coordination of the signals transmitted by each transmission channel by the transmission timing control circuit comprises the following steps:
The transmitting time sequence control circuit executes the control signal of the lower computer central control unit and sets the transmitting time difference of the transmitting signals of the transmitting channels as And differentiating the direction of the transmitting beam, wherein the calculation formula of the direction of the transmitting beam is as follows:
In the above-mentioned method, the step of, In order to transmit the beam pointing angle,In order to transmit the time difference of the time difference,And c is the propagation speed of electromagnetic waves, which is the distance difference between the adjacent 2 transmitting channels.
8. The system of claim 1, wherein the process of the receiving timing control circuit for implementing time coordination of the signals received by each of the receiving channels comprises the following steps:
the receiving time sequence control circuit executes the control signal of the lower computer central control unit and sets the receiving time difference of the signals received by each receiving channel as And differentiating the received beam direction, wherein the calculation formula of the received beam direction is as follows:
In the above-mentioned method, the step of, In order to receive the beam pointing angle,In order to receive the time difference of the time difference,And c is the propagation speed of the electromagnetic wave, which is the distance difference between the adjacent 2 receiving channels.
9. The system of claim 1, wherein the ultra-wideband antenna array is mounted on a one-dimensional or two-dimensional guide rail that is capable of sliding continuously, and each antenna port of the ultra-wideband antenna array is electrically connected to the common port of the high-speed transceiver switch by an equal-length coaxial cable.
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