CN115344493A - System safety and reliability self-testing system and method - Google Patents

Abstract

The invention relates to a system safety and reliability self-testing system and a method. The system comprises a configuration bus module, a nonvolatile memory and a self-test control unit, wherein the self-test control unit comprises a register, a collector, a logic block and a storage block; the register controls the start of self-testing, monitors the running states of the logic block and the storage block and checks the self-testing result; testing the logic block management logic unit; testing the memory block management embedded MEM; the collector collects and updates the execution state of the self-test logic and the self-test result, and carries out different division and processing on the collected result according to the configuration type. Before the main user application program is started, the self-test control unit controls the equipment self-test sequence, so that the normal operation of the system is ensured, and the aim of improving the safety and the reliability of the whole system is fulfilled.

Description

System safety and reliability self-testing system and method

Technical Field

The invention belongs to the technical field of integrated circuit design, and particularly relates to a system safety and reliability self-testing system and method.

Background

With the wide application of integrated circuit technology, the safety and reliability of integrated circuits need to be improved. To achieve this, the logic and critical memory circuits of the integrated circuit need to be tested to meet the required level of safety integrity for the system. The self-testing control unit is a component in the whole safe complete subsystem, runs a self-testing sequence before the main user application program starts to run, and processes collected fault errors according to classification.

Disclosure of Invention

In order to solve the technical problems in the background art, the invention provides a system safety and reliability self-testing system and a method.

The technical solution of the invention is as follows: the invention relates to a system safety and reliability self-testing system, which is characterized in that: the system comprises a configuration bus module, a nonvolatile memory and a self-test control unit, wherein the self-test control unit comprises a register, a collector, a logic block and a storage block; the register controls the self-testing starting, monitors the running states of the logic block and the storage block and checks the self-testing result; testing the logic block management logic unit; testing the memory block management embedded MEM; and the collector collects and updates the execution state of the self-test logic and the self-test result, and carries out different division and processing on the collected result according to the configuration type.

Further, the system also comprises a fault collection control unit, and the collector is connected with the fault collection control unit.

Further, the system also comprises a mode control unit, and the collector is connected with the mode control unit.

Furthermore, the system also comprises a logic unit, and the logic block is connected with the logic unit.

Further, the system also comprises embedded MEMs, and the memory block is connected with the embedded MEMs.

Further, the self-test control unit further comprises a watchdog timer, the watchdog timer is connected with the register, and the watchdog timer provides a prevention mechanism for the following operations: deadlock or runaway occurs in the self-test process; the self-test control unit starts self-test but the self-test logic engine does not run, and the self-test logic is guaranteed to run correctly by exiting in time.

Furthermore, a configuration interface is connected outside the register, the configuration bus module is connected with the configuration bus module through the configuration interface, the configuration interface is used for resetting the operation state of the withdrawn self-test module and classifying the loading, the fault and the error types of the configuration values, and the constant value of the self-test can be loaded through the configuration interface under the condition that no processor participates.

Furthermore, the system also comprises a processor, the register is externally connected with an APB interface, the processor is connected with the register through the APB interface, and the APB interface is used for acquiring the running state and the self-checking result.

The system for realizing the safety and reliability self-test of the system is characterized in that: the method comprises the following steps:

1) And (3) self-checking:

1.1 After the self-test control unit is reset, the configuration bus module detects that the self-test of the equipment is not operated, and reads self-test parameters from the nonvolatile memory;

1.2 A configuration bus module loads self-test parameters into a self-test control unit and transmits control to the self-test control unit, and a register manages a storage block and a logic block and updates the internal state of the storage block and the logic block;

1.3 If a fault is detected, the collector collects fault information from the storage block and the logic block and reports the fault information to the fault collection control unit, and simultaneously informs the mode configuration module that the detection is completed, and the boot sequence enters a function reset phase; if a reset hold failure occurs, the mode control unit keeps the device reset until an application self-test control unit reset event;

2) Function reset phase:

2.1 Mode configuration module triggers a function reset;

2.2 The configuration bus module detects that a device self-test has run and passes control to the processor;

2.3 Integrity software checks the results of the self-test;

2.4 Integrity software self-check is completed and the device may be considered to pass the check and pass control information to the application software.

According to the system safety and reliability self-testing system and method provided by the invention, the key part of the chip is self-tested, the self-testing result is collected, and the self-testing result is divided according to the error and fault types, so that different operations and processing are realized, the normal operation of the system is ensured, and the purpose of improving the safety and reliability of the whole system is achieved. The system of the present invention covers all components of the safety integrity subsystem, with the self-test control unit controlling the device self-test sequence before the main user application is started. The invention also provides integrity software operations: after the self-test, the integrity software operates based on the running status of the self-test control unit. Even if no error is reported, the integrity software needs to confirm that the actual and expected values with the check and the associated registers are error free. Software validation prevents the passing of tests that result from incorrect errors within the self-test control unit.

Drawings

FIG. 1 is a system block diagram of the present invention;

FIG. 2 is a diagram of the self-test phase application of the present invention;

fig. 3 is a functional reset phase application diagram of the present invention.

Detailed Description

The technical solution of the present invention is further described in detail with reference to the accompanying drawings and specific embodiments.

Referring to fig. 1, the structure of the specific embodiment of the system safety and reliability self-testing system of the present invention includes a configuration bus module, a nonvolatile memory, a self-testing control unit, a failure collection control unit, a mode control unit, a logic unit, an embedded MEM, and a processor, where the self-testing control unit includes a register, a collector, a logic block, and a memory block, the configuration bus module is respectively connected with the nonvolatile memory and the register, the register is respectively connected with the logic block and the memory block, the logic block is connected with the logic unit, the memory block is connected with the embedded MEM, and the logic block and the memory block are respectively connected with the collector; the collector is connected with the failure collection control unit and the mode control unit respectively. Wherein:

the register controls the self-testing starting, monitors the running states of the logic block and the storage block and checks the self-testing result; testing a logic block management logic unit; testing the memory block management embedded MEM; the collector collects and updates the execution state of the self-test logic and the self-test result, and carries out different division and processing on the collected result according to the configuration type.

The self-test control unit further comprises a watchdog timer, the watchdog timer being connected to the register, the watchdog timer providing a prevention mechanism for: deadlock or runaway occurs in the self-testing process; the self-test control unit starts self-test but the self-test logic engine does not run, and the self-test logic is ensured to run correctly by exiting overtime.

The register is externally connected with a configuration interface, the configuration bus module is connected with the configuration bus module through the configuration interface, the configuration interface is used for resetting the running state of the withdrawn self-test module and classifying the loading, the fault and the error types of the configuration values, and the constant value of the self-test can be loaded through the configuration interface under the condition that no processor participates.

The APB interface is connected outside the register, the processor is connected with the register through the APB interface, and the APB interface is used for obtaining the running state and the self-checking result.

When a reset event of the self-test control unit occurs, the system of the invention passes through a boot sequence of two phases: a self-checking phase and a function resetting phase.

Referring to fig. 2, the first stage: a self-checking stage;

1.1 After the self-test control unit is reset, the configuration bus module detects that the equipment self-test is not operated, and reads self-test parameters from the nonvolatile memory;

1.2 A configuration bus module loads self-test parameters into a self-test control unit and transfers control to the self-test control unit, and a register manages a storage block and a logic block and updates the internal state thereof;

1.3 If a failure is detected, the collector collects failure information from the memory block and the logic block and reports the failure information to the failure collection control unit while notifying the mode configuration module that the detection is complete and the boot sequence enters functional reset; if a reset hold failure occurs, the mode control unit holds the device in reset until a self-test control unit reset event is applied.

Referring to fig. 3, the second stage: a function resetting stage;

2.1 Mode configuration module triggers a function reset;

2.2 The configuration bus module detects that a device self-test has run and passes control to the processor;

2.3 Integrity software checks the results of the self-test;

2.4 Integrity software self-check is completed and the device may be considered to pass the check and pass control information to the application software.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (9)

1. A system for security and reliability self-test of a system, comprising: the system comprises a configuration bus module, a nonvolatile memory and a self-testing control unit, wherein the self-testing control unit comprises a register, a collector, a logic block and a storage block, the configuration bus module is respectively connected with the nonvolatile memory and the register, the register is respectively connected with the logic block and the storage block, and the logic block and the storage block are respectively connected with the collector; the register controls the self-testing starting, monitors the running states of the logic block and the storage block and checks the self-testing result; the logic block manages the testing of the logic unit; the memory block manages testing of the embedded MEMs; the collector collects and updates the execution state of the self-test logic and the self-test result, and carries out different division and processing on the collected result according to the configuration type.

2. The system security and reliability self-test system of claim 1, wherein: the system also comprises a fault collection control unit, and the collector is connected with the fault collection control unit.

3. The system security and reliability self-test system of claim 2, wherein: the system also includes a mode control unit, the collector being connected to the mode control unit.

4. The system security and reliability self-test system of claim 1, wherein: the system also includes a logic unit, the logic block being connected to the logic unit.

5. The system security and reliability self-test system of claim 4, wherein: the system also includes an embedded MEM to which the memory block is coupled.

6. The system security and reliability self-test system of claim 1, wherein: the self-test control unit further comprises a watchdog timer, the watchdog timer being connected to the register, the watchdog timer providing a preventive mechanism for: deadlock or runaway occurs in the self-testing process; the self-test control unit starts self-test but the self-test logic engine does not run, and the self-test logic is ensured to run correctly by exiting overtime.

7. A system safety and reliability self-test system according to any of claims 1 to 6, wherein: the register is externally connected with a configuration interface, the configuration bus module is connected with the configuration bus module through the configuration interface, the configuration interface is used for resetting the operation state of the withdrawn self-test module and classifying the loading, fault and error types of the configuration values, and the constant value of the self-test can be loaded by using the configuration interface under the condition that no processor participates.

8. The system for security and reliability self-testing of a system according to claim 7, wherein: the system further comprises a processor, wherein an APB interface is externally connected with the register, the processor is connected with the register through the APB interface, and the APB interface is used for obtaining the running state and the self-checking result.

9. A system security and reliability self-test system implementing the system of claim 1, characterized by: the method comprises the following steps:

1) And (3) self-checking:

1.1 After the self-test control unit is reset, the configuration bus module detects that the self-test of the equipment is not operated, and reads self-test parameters from the nonvolatile memory;

1.2 A configuration bus module loads self-test parameters into a self-test control unit and transfers control to the self-test control unit, and a register manages a storage block and a logic block and updates the internal state thereof;

1.3 If a failure is detected, the collector collects failure information from the memory block and the logic block and reports the failure information to the failure collection control unit, while notifying the mode configuration module that the detection is complete and the boot sequence enters a function reset phase; if a reset hold failure occurs, the mode control unit keeps the device reset until an application self-test control unit reset event;

2) Function reset phase:

2.1 Mode configuration module triggers a function reset;

2.2 The configuration bus module detects that a device self-test has run and passes control to the processor;

2.3 Integrity software checks the results of the self-test;

2.4 Integrity software self-check is completed and the device may be considered to pass the check and pass control information to the application software.

Images