CN115333556A - High-speed receiving module based on MIPI protocol and vehicle-mounted video transmission chip - Google Patents
High-speed receiving module based on MIPI protocol and vehicle-mounted video transmission chip Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
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- H—ELECTRICITY
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- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract
The invention provides a high-speed receiving module based on MIPI protocol and a vehicle-mounted video transmission chip, wherein the high-speed receiving module comprises: a second amplifier set composed of a first amplifier and a second amplifier; a signal from a first output terminal of the first-stage amplifier is input from a positive input terminal of the first amplifier and from a negative input terminal of a second amplifier; the signal from the second output terminal of the first-stage amplifier is input from the negative input terminal of the first amplifier and from the positive input terminal of the second amplifier; outputting a first signal from a first amplifier and a second signal from a second amplifier; and a first signal input from the first input end of the inverting structure and a second signal input from the second input end are subjected to phase inverter cross processing to obtain a differential signal, and a forward signal or an inverted signal is output from the output end OUT. The invention obviously optimizes the clock jitter value and improves the product yield.
Description
Technical Field
The invention relates to the technical field of vehicle-mounted video transmission chips, in particular to a high-speed receiving module based on an MIPI (Mobile industry processor interface) protocol and a vehicle-mounted video transmission chip.
Background
In the high-speed transmission process of vehicle-mounted video data, along with the continuous improvement of the precision of the video data, the continuous increase of the pixel quantity and the continuous improvement of the video transmission rate, higher requirements are also put forward on the performance of a receiving module, according to the technical indexes defined by an MIPI protocol, the common-mode voltage VCM range of a high-speed serial signal input signal received by the receiving module is 70 mV-330 mV, the amplitude VID range is 140-260 mV, and the receiving module needs to convert the input signal into output signals with high and low levels of 1.1V and 0V respectively under the condition of the input signal speed of 2.5Gbps, convert the input signal into 8 paths of parallel signals and output the output signals to a digital module for processing after serial conversion.
The conventional high-speed receiving module finds that the jitter value is too large through process corner and Monte Carlo verification, and the product yield is influenced.
Disclosure of Invention
In order to solve the technical problems, the invention provides a high-speed receiving module based on an MIPI protocol and a vehicle-mounted video transmission chip, wherein the jitter value of the high-speed receiving module is obviously optimized by adopting a differential design, so that the jitter value of the high-speed receiving module is less than 0.1UI (one UI represents one bit width) by Monte Carlo verification under the worst condition, and the product yield is obviously improved.
In a first aspect of the present invention, a high-speed receiving module based on MIPI protocol is provided, including:
the first-stage amplifier is used for carrying out small-amplitude gain amplification on input signals input from the positive input end INP and the negative input end INN and converting common-mode voltage of the input signals from low voltage to high voltage; wherein, the input signal comes from the high-speed sending module;
a second-stage amplifier including a first amplifier SEC _ AMP1 and a second amplifier SEC _ AMP2; the signal from the first output terminal of the first-stage amplifier is input from the positive input terminal of the first amplifier SEC AMP1 and from the negative input terminal of the second amplifier SEC AMP2; the signal from the second output terminal of the first-stage amplifier is input from the negative input terminal of the first amplifier SEC AMP1 and from the positive input terminal of the second amplifier SEC AMP2; the first amplifier SEC _ AMP1 and the second amplifier SEC _ AMP2 amplify an input signal at a high gain, and output a first signal from the first amplifier SEC _ AMP1 and a second signal from the second amplifier SEC _ AMP2;
an inverting structure comprising a first input and a second input; and performing phase inverter cross processing on a first signal input from the first input end and a second signal input from the second input end to obtain a differential signal, and outputting one path of forward signal or reverse signal of the differential signal from an output end OUT.
Optionally, the inverting structure includes a cross inverter and a multiplexer MUX;
the cross inverter carries out inverter cross processing on the input first signal and the input second signal, and inputs two paths of differential signals obtained by processing into the multiplexer MUX;
and the multiplexer MUX selects a forward signal or a reverse signal to be output from the output end OUT according to preset parameters.
Optionally, the cross inverter includes:
the input end of the first inverter is a first input end of the inverting structure INV and is connected with the output end of the first amplifier SEC _ AMP 1;
the input end of the second inverter is a second input end of the inverting structure INV and is connected with the output end of the second amplifier SEC _ AMP 1;
the cross-coupled inverter consists of a third inverter and a fourth inverter; the input end of the third inverter is connected with the output end of the fourth inverter to be used as the first end of the cross-coupled inverter; the output end of the third inverter is connected with the input end of the fourth inverter to be used as the second end of the cross-coupled inverter; the first end of the cross-coupled phase inverter is connected with the output end of the second phase inverter, and the second section of the cross-coupled phase inverter is connected with the output end of the second phase inverter;
the input end of the fifth inverter is connected with the second end of the cross-coupled inverter, and the output end of the fifth inverter is connected with one input end of the multiplexer MUX;
and the input end of the sixth phase inverter is connected with the first end of the cross-coupled phase inverter, and the output end of the sixth phase inverter is connected with one input end of the multiplexer MUX.
Optionally, the high-speed sending module includes a triggering unit, a main path unit, and a weighted path unit;
the input end of the main channel unit and the input end of the weighted channel unit are both connected with the output end of the trigger unit so as to respectively receive a high-speed data signal DIN through the trigger unit and respectively optimize the high-speed data signal DIN;
and the output end of the main channel unit and the output end of the emphasis channel unit are connected to perform superposition compensation on the optimized high-speed data signal DIN.
Optionally, the trigger unit includes a first trigger DFF1; a D pin of the first flip-flop DFF1 serves as an input terminal of a trigger unit for receiving the high-speed data signal DIN; the CK pin of the first trigger DFF1 is used for receiving a clock signal HS _ CLK; an RB pin of the first trigger DFF1 is connected with a first power supply VDD so as to provide power support for the first trigger DFF1 through the first power supply VDD; and a Q pin of the first trigger DFF1 is used as an output end of the trigger unit and is connected with input ends of the main path unit and the weighted path unit.
Optionally, the main path unit includes a first signal conversion sub-unit S _ TO _ D1, a first signal optimization sub-unit D _ BUF1, a main signal logic transformation sub-unit REG _ BUF, a high-speed output driving sub-unit HS _ DRIVER, AND a first logic AND gate AND1;
the input end of the first signal conversion sub-unit S _ TO _ D1 is connected with the output end of the trigger unit and used for receiving the single-ended signal DIN _ IN output by the trigger unit and converting the single-ended signal DIN _ IN into a main differential signal for output;
the input end of the first signal optimization subunit D _ BUF1 is connected with the output end of the first signal conversion subunit S _ TO _ D1, and is used for receiving the main differential signal, optimizing the main differential signal TO form a main optimization signal and outputting the main optimization signal;
the input end of the main signal logic conversion subunit REG _ BUF is connected with the output end of the first signal optimization subunit D _ BUF1 and is used for receiving the main optimization signal; the enabling end of the main signal logic transformation subunit REG _ BUF is connected with the output end of the first logic AND gate AND1, so that the main signal logic transformation subunit REG _ BUF carries out logic transformation on the main optimization signal under the control action of the first logic AND gate AND1 to adjust the equivalent resistance output by the sending module;
the input end of the high-speed output drive sub-unit HS _ DRIVER is connected with the output end of the main signal logic transformation sub-unit REG _ BUF, AND is used for receiving the main optimization signal after logic transformation output by the main signal logic transformation sub-unit REG _ BUF AND changing the equivalent impedance output by the sending module under the control of the first logic AND gate AND1; and the output end of the high-speed output driving sub-unit HS _ DRIVER is connected with the output end of the weighted passage unit.
Optionally, the emphasis path unit includes a second trigger DFF2, a second signal conversion sub-unit S _ TO _ D2, a second signal optimization sub-unit D _ BUF2, an emphasis signal logic conversion sub-unit REG _ E _ BUF, a high-speed output emphasis sub-unit HS _ EMP, AND a second logic AND gate AND2;
the input end of the second flip-flop DFF2 is connected with the output end of the trigger unit, and is configured to receive the single-ended signal DIN _ IN output by the trigger unit and convert the single-ended signal DIN _ IN into an emphasized signal DIN _ EMP for output;
the input end of the second signal conversion subunit S _ TO _ D2 is connected TO the output end of the second flip-flop DFF2, and is configured TO receive the emphasized signal DIN _ EMP and convert the emphasized signal DIN _ EMP into an emphasized differential signal for output;
the input end of the second signal optimization subunit D _ BUF2 is connected with the output end of the second signal conversion subunit S _ TO _ D2, and is configured TO receive the emphasized differential signal, optimize the emphasized differential signal TO form an emphasized optimized signal, and output the emphasized optimized signal;
the input end of the weighted signal logic conversion subunit REG _ E _ BUF is connected with the output end of the second signal optimization subunit D _ BUF2 and is used for receiving the weighted optimization signal; the enabling end of the emphasized signal logic transformation sub-unit REG _ E _ BUF is connected with the output end of the second logic AND gate AND2, so that the emphasized signal logic transformation sub-unit REG _ E _ BUF carries out logic transformation on the emphasized optimization signal under the control action of the second logic AND gate AND2 to adjust the equivalent resistance output by the sending module;
the input end of the high-speed output emphasis sub-unit HS _ EMP is connected with the output end of the emphasis signal logic transformation sub-unit REG _ E _ BUF, AND is used for receiving the emphasis optimization signal after logic transformation output by the emphasis signal logic transformation sub-unit REG _ E _ BUF AND changing the equivalent impedance output by the sending module under the control action of the second logic AND gate AND2; and the output end of the high-speed output emphasis sub-unit HS _ EMP is connected with the output end of the main channel unit.
In a second aspect of the present invention, a vehicle-mounted video transmission chip is provided, which includes the high-speed receiving module as described in the first aspect.
According to the embodiment of the invention, the first signal and the second signal in a reverse relation are obtained by adopting a differential design in the second-stage amplifier, so that when the signal input into the second-stage amplifier has certain deviation, the first signal output by the first amplifier has forward deviation jitter, and the second signal output by the second amplifier has reverse deviation jitter, and therefore after the signal is subjected to cross processing by the phase inverter with an inverted structure, complementary offset of jitter errors between the first signal and the second signal is realized, a differential signal with small jitter is obtained, the jitter value of a high-speed receiving module is effectively optimized, and the product yield is improved.
It should be understood that the statements made in this summary are not intended to limit the key or critical features of the embodiments of the present invention, or to limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
The above and other features, advantages and aspects of various embodiments of the present invention will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements, and wherein:
fig. 1 is a circuit configuration diagram of a conventional high-speed receiving module;
fig. 2 is a circuit structure diagram of a high-speed receiving module according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a cross inverter according to an embodiment of the present invention;
FIG. 4 is an eye diagram waveform of a first signal output by a first amplifier according to an embodiment of the present invention;
FIG. 5 is an eye diagram waveform of a second signal output by a second amplifier according to an embodiment of the present invention;
FIG. 6 is an eye diagram waveform of the output signal of the cross inverter according to an embodiment of the present invention;
FIG. 7 is an eye diagram of the conventional high-speed receiver module respectively verifying three different temperature outputs of-40 deg.C, 45 deg.C and 130 deg.C under all process corners TT, FF and SS;
FIG. 8 is an eye diagram of the high-speed receiver module provided in the embodiment of the present invention verifying the outputs at-40 deg.C, 45 deg.C and 130 deg.C respectively at all process corners TT, FF and SS;
FIG. 9 shows Monte Carlo verification results of a conventional high-speed receiving module;
fig. 10 shows the monte carlo verification result of the high speed receiving module according to the embodiment of the invention;
FIG. 11 is a circuit schematic of a high speed transmit module of an embodiment of the present invention;
fig. 12 is a diagram of an equivalent circuit of a resistor network composed of the high-speed output driving sub-unit HS _ DRIVER, the high-speed output emphasis sub-unit HS _ EMP, and the resistor sheet outer R2 according to the embodiment of the present invention (DIN _ IN =1, DIN \uemp = 0);
fig. 13 is a diagram of an equivalent circuit of a resistor network composed of the high speed output driving sub-unit HS _ DRIVER, the high speed output emphasis sub-unit HS _ EMP, and the off-chip resistor R2 according to the embodiment of the present invention (DIN _ IN =1, DIN \uemp = 1);
FIG. 14 is a diagram of DIN _ IN, DIN _ EMP, and VOD timing relationships according to an embodiment of the present invention;
FIG. 15 is a waveform and an eye diagram of an output signal corresponding to a PRBS9 signal with an input signal DIN of 4.5Gbps when no weighted path unit is turned on according to an embodiment of the present invention;
fig. 16 shows waveforms and eye diagrams of corresponding output signals when the input signal DIN is the PRBS9 signal of 4.5Gbps after the weighted path unit is turned on according to the embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In addition, the term "and/or" herein is only one kind of association relationship describing the association object, and means that there may be three kinds of relationships, for example, a and/or B, and may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
As shown in fig. 1, the circuit structure of the conventional high-speed receiving module adopts two-stage amplification, the first-stage amplifier PRE _ AMP provides small gain amplification, and converts the input common-mode voltage from low voltage to high voltage, so as to ensure that the NMOS pair transistor input by the second-stage amplifier SEC _ AMP operates normally; the second stage amplifier SEC AMP provides a higher gain and outputs to and from one inverter. Due to non-ideal factors such as device mismatch and process errors, the final output clock jitter is large.
The invention provides a high-speed receiving module based on MIPI protocol, as shown in figure 2, comprising:
the first-stage amplifier PRE _ AMP is a preamplifier, and a positive input end and a negative input end are respectively a positive input end INP of the high-speed receiving module and a negative input end INN of the high-speed receiving module; the gain amplifier is used for amplifying the input signals input from the positive input end INP and the negative input end INN in a small gain range, wherein the gain range is generally 8 dB-10 dB, and converting the common mode voltage of the input signals from low voltage to high voltage; wherein, the input signal comes from the high-speed sending module; according to the MIPI protocol indexes, the common mode voltage is low, the voltage is 70mV to 330mV, and the amplitude is a signal from plus or minus 70mV to plus or minus 130 mV; the high voltage of the common mode voltage is a signal output by the first-stage amplifier, and the common mode voltage is converted into a signal with about 0.9V and about 200mV of amplitude.
A second-stage amplifier SEC _ AMP including a first amplifier SEC _ AMP1 and a second amplifier SEC _ AMP2; a signal from a first output terminal of the first-stage amplifier PRE _ AMP is input to the first amplifier SEC _ AMP1 from a positive input terminal of the first amplifier SEC _ AMP1, and is input to the second amplifier SEC _ AMP2 from a negative input terminal of the second amplifier SEC _ AMP2; the signal from the second output terminal of the first-stage amplifier PRE _ AMP is input to the first amplifier SEC _ AMP1 from the negative input terminal of the first amplifier SEC _ AMP1, and is input to the second amplifier SEC _ AMP2 from the positive input terminal of the second amplifier SEC _ AMP2; the first amplifier SEC _ AMP1 and the second amplifier SEC _ AMP2 amplify the input signal at a high gain (the gain of the second-stage amplifier is 20dB or more, so that the input signal with a relatively small amplitude can be directly converted into a digital signal from 0 to VDD), and output the first signal from the first amplifier SEC _ AMP1 and the second signal from the second amplifier SEC _ AMP2, where the first signal and the second signal are in an inverse relationship.
The INV comprises a first input end and a second input end, and the output end is the output end OUT of the high-speed receiving module; and the first signal input from the first input end and the second signal input from the second input end are subjected to phase inverter cross processing to realize the complementary offset of the jitter errors of the first signal and the second signal, so that a differential signal with small jitter is obtained, and a forward signal or a reverse signal is output from the output end OUT.
According to the embodiment of the application, the first signal and the second signal in a reverse relation are obtained by adopting a differential design at the SEC-AMP, so that when the signal input into the SEC-AMP has a certain deviation, the first signal output by the first amplifier has forward deviation jitter, and the second signal output by the second amplifier has reverse deviation jitter.
In this embodiment, the inverting structure INV includes a cross inverter INV-C and a multiplexer MUX, and two input ends of the cross inverter INV-C are used as the input end of the inverting structure INV, and an output end of the multiplexer MUX is used as the output end of the inverting structure INV; the cross inverter INV-C performs inverter cross processing on the input first signal and the input second signal, and inputs two paths of processed differential signals into the multiplexer MUX, and the multiplexer MUX selects one path of forward signals or reverse signals to be output from the output end OUT according to preset parameters (namely through digital control); the input signal is in phase with a forward signal and in anti-phase with a reverse signal.
As shown in fig. 3, in some embodiments, the cross inverter INV-C includes six inverters, and the specific structure is as follows:
the input end of the first inverter INV1 is a first input end IP1 of the inverting structure INV and is connected with the output end of the first amplifier SEC _ AMP 1;
the input end of the second inverter INV2 is a second input end IN1 of the inverting structure INV and is connected with the output end of the second amplifier SEC _ AMP 1;
the cross-coupled inverter consists of a third inverter INV3 and a fourth inverter INV 4; the input end of the third inverter INV3 and the output end of the fourth inverter INV4 are connected as the first end of the cross-coupled inverter; the output end of the third inverter INV3 and the input end of the fourth inverter INV4 are connected as the second end of the cross-coupled inverter; the first end of the cross-coupled inverter is connected with the output end of the second inverter INV2, and the second end of the cross-coupled inverter is connected with the output end of the first inverter INV 1;
an input end of the fifth inverter INV5 is connected to the second end of the cross-coupled inverter, and an output end of the fifth inverter INV5 is connected to one input end of the multiplexer MUX;
and the input end of the sixth inverter INV6 is connected with the first end of the cross-coupled inverter, and the output end of the sixth inverter INV is connected with one input end of the multiplexer MUX.
In this embodiment, the first signal and the second signal input from the cross-coupled inverters are inverted by the first inverter and the second inverter, respectively, then the cross-coupled inverters optimize the rise-fall time of the input differential signal, and then the signals are shaped by the fifth inverter and the sixth inverter, respectively, and then the signals are output, so that the jitter errors between the input first signal and the input second signal are complementarily cancelled, thereby achieving the purpose of optimizing the waveform eye jitter value of the input signal. FIG. 4 shows an eye diagram waveform of a first signal output by a first amplifier, FIG. 5 shows an eye diagram waveform of a second signal output by a second amplifier, and FIG. 6 shows an eye diagram waveform of an output signal of a cross inverter; the clock jitter values at VDD/2, with the cross-over of the eye diagram of FIG. 4 biased downward and the cross-over of the eye diagram of FIG. 5 biased upward, are 15.22pS and 14.17pS for the eye diagram at VDD/2, respectively; while fig. 6 is an eye diagram waveform after cross-inverter cancellation, the clock jitter value at VDD/2 is only 1pS, and the optimization is very obvious.
Taking an input signal rate of 2.5Gbps and an input amplitude of plus or minus 50mV as an example, the process corner and monte carlo verification are respectively performed on the circuit structure of the conventional high-speed receiving module and the high-speed receiving module provided by the invention under the condition that the power supply voltage is low (vdd = 0.99V).
And (3) process corner verification:
FIG. 7 is an eye diagram of the conventional high-speed receiver module under all process corners TT, FF, and SS respectively verifying three different temperature outputs of-40 deg.C, 45 deg.C, and 130 deg.C, with the jitter value reaching 22.4pS to the maximum;
FIG. 8 is an eye diagram of the high-speed receiver module provided by the present application for verifying the outputs of three different temperatures of-40 deg.C, 45 deg.C and 130 deg.C respectively under all process corners TT, FF and SS, wherein the jitter value is at most 3.9pS;
therefore, an eye diagram obtained by process corner verification shows that compared with a circuit structure of a traditional high-speed receiving module, the performance of the high-speed receiving module jitter provided by the application is obviously optimized.
Monte Carlo verification:
FIG. 9 shows Monte Carlo verification results of a conventional high-speed receiving module, wherein the jitter value of 3sigma is 60.3pS;
FIG. 10 shows the Monte Carlo validation results of the high-speed receiving module provided in the present application, wherein the jitter value of 3sigma is 39.8pS, which is less than 0.1UI;
therefore, the Monte Carlo verification result shows that the jitter performance of the high-speed receiving module provided by the application is obviously optimized compared with the circuit structure of the traditional high-speed receiving module.
In summary, under the verification of the process corner and the monte carlo, the jitter value of the high-speed receiving module provided by the invention is obviously optimized, and the performance of the high-speed receiving module is greatly improved, so that the yield of products is effectively improved.
In this embodiment, in order to better ensure the performance of the high-speed receiving module, as shown in fig. 11, the high-speed transmitting module includes a triggering unit 10, a main path unit 20, and a weighting path unit 30; the main path unit 20 and the weight path unit 30 are connected in parallel; the input ends of the main path unit 20 and the emphasis path unit 30 are connected to the output end of the trigger unit 10 at the same time, so as to receive the high-speed data signal DIN through the trigger unit 10, respectively, and optimize the high-speed data signal DIN; the output terminal of the main path unit 20 and the output terminal of the emphasis path unit 30 are connected to perform superposition compensation on the optimized high-speed data signal DIN; two connection nodes between the output terminal of the main path unit 20 and the output terminal of the emphasis path unit 30 are connected by an off-chip resistor R2.
In the present invention, the input terminals of the main path unit 20 and the emphasis path unit 30 are simultaneously connected to the output terminal of the trigger unit 10, so as to ensure that the high-speed data signals DIN obtained at the input terminals of the main path unit 20 and the emphasis path unit 30 are the same; the main path unit 20 and the emphasis path unit 30 respectively perform optimization processing on the obtained high-speed data signal DIN, and then superimpose the optimized high-speed data signal DIN to compensate for attenuation of the high-speed data signal DIN during transmission, which is beneficial to optimizing eye diagram quality of damaged signals. By adopting the high-speed sending module with pre-emphasis in the technical scheme, the emphasis path unit 30 capable of being modified and adjusted is added, so that the required emphasis amplitude can be adjusted according to actual conditions in use, the attenuation of high-frequency signals in the transmission process of the high-speed data signal DIN can be effectively compensated, and a receiving terminal can obtain better signal waveforms.
In some embodiments of the present invention, the trigger unit 10 includes a first flip-flop DFF1, where the first flip-flop DFF1 is a D-type flip-flop triggered by a rising clock edge; a D pin of the first flip-flop DFF1 serves as an input terminal of the trigger unit 10, and is configured to receive a high-speed data signal DIN; the CK pin of the first flip-flop DFF1 is used for receiving a clock signal HS _ CLK; the RB pin of the first trigger DFF1 is connected with a first power supply VDD so as to provide power support for the normal operation of the first trigger DFF1 through the first power supply VDD; the Q pin of the first flip-flop DFF1 serves as an output terminal of the trigger unit 10 and simultaneously connects input terminals of the main path unit 20 and the emphasis path unit 30. In the present application, when a rising edge of the clock signal received by the CK pin of the first flip-flop DFF1 arrives, the D pin receiving high-speed data signal DIN is transferred to the Q pin and is output through the Q pin.
In some embodiments of the present invention, the main path unit 20 includes a first signal conversion sub-unit S _ TO _ D1, a first signal optimization sub-unit D _ BUF1, a main signal logic conversion sub-unit REG _ BUF, a high speed output driving sub-unit HS _ DRIVER, AND a first logic AND gate AND1.
Wherein,
the input end of the first signal conversion sub-unit S _ TO _ D1 is connected with a Q pin of the first trigger DFF1, and is used for receiving a single-ended signal DIN _ IN output by the Q pin of the first trigger DFF1 and converting the single-ended signal DIN _ IN into a main differential signal for output;
the input end of the first signal optimizing subunit D _ BUF1 is connected with the output end of the first signal converting subunit S _ TO _ D1, and is used for receiving a main differential signal output by the output end of the first signal converting subunit S _ TO _ D1, optimizing the main differential signal TO form a main optimized signal and outputting the main optimized signal;
the input end of the main signal logic conversion sub-unit REG _ BUF is connected with the output end of the first signal optimization sub-unit D _ BUF1 and is used for receiving a main optimization signal output by the output end of the first signal optimization sub-unit D _ BUF 1; an enabling end (namely a driving enabling signal pin en) of the main signal logic transformation subunit REG _ BUF is connected with an output end of the first logic AND gate AND1, so that the main signal logic transformation subunit REG _ BUF performs logic transformation on the main optimization signal under the control action of the first logic AND gate AND1 to adjust the equivalent resistance output by the sending module (namely the equivalent resistance output by the main path unit 20); the input end of the first logic AND gate AND1 is respectively connected with a drive enabling signal en _ driver AND a drive register signal reg _ driver;
the input end of the high-speed output drive sub-unit HS _ DRIVER is connected to the output end of the main signal logic conversion sub-unit REG _ BUF, and is configured to receive a main optimized signal after logic conversion output by the output end of the main signal logic conversion sub-unit REG _ BUF, and change an equivalent impedance output by the sending module (i.e., an equivalent impedance output by the main path unit 20) under the control action of the drive register signal REG _ DRIVER; the output terminal of the high-speed output drive sub-unit HS _ DRIVER is connected to the output terminal of the emphasis path unit 30.
In some embodiments of the present invention, the emphasis path unit 30 includes a second flip-flop DFF2, a second signal conversion sub-unit S _ TO _ D2, a second signal optimization sub-unit D _ BUF2, an emphasis signal logic conversion sub-unit REG _ E _ BUF, a high-speed output emphasis sub-unit HS _ EMP, AND a second logic AND gate AND2.
Wherein,
the input end of the second flip-flop DFF2 is connected to the output end of the trigger unit 10, and is configured to receive the single-ended signal DIN _ IN output by the trigger unit 10, and convert the single-ended signal DIN _ IN into an emphasized signal DIN _ EMP for output;
the input end of the second signal conversion subunit S _ TO _ D2 is connected TO the output end of the second flip-flop DFF2, and is configured TO receive the emphasis signal DIN _ EMP and convert the emphasis signal DIN _ EMP into an emphasis differential signal for output;
the input end of the second signal optimization subunit D _ BUF2 is connected with the output end of the second signal conversion subunit S _ TO _ D2, and is used for receiving the emphasized differential signal, optimizing the emphasized differential signal TO form an emphasized optimization signal and outputting the signal;
the input end of the weighted signal logic conversion sub-unit REG _ E _ BUF is connected with the output end of the second signal optimization sub-unit D _ BUF2 and used for receiving a weighted optimization signal; the enabling end of the weighted signal logic transformation sub-unit REG _ E _ BUF is connected with the output end of the second logic AND gate AND2, so that the weighted signal logic transformation sub-unit REG _ E _ BUF carries out logic transformation on the weighted optimization signal under the control action of the second logic AND gate AND2 to adjust the equivalent resistance output by the sending module;
the input end of the high-speed output emphasis sub-unit HS _ EMP is connected with the output end of the emphasis signal logic conversion sub-unit REG _ E _ BUF AND is used for receiving an emphasis optimization signal output by the emphasis signal logic conversion sub-unit REG _ E _ BUF after logic conversion AND changing the equivalent impedance output by the sending module under the control action of a second logic AND gate AND2; the output terminal of the high-speed output emphasis sub-unit HS _ EMP is connected to the output terminal of the main path unit 20.
Specifically, the D pin of the second flip-flop DFF2 is used as the input terminal of the weighted pass unit 30 to be connected to the Q pin of the first flip-flop DFF1, so as to receive the single-ended signal DIN _ IN output from the Q pin of the first flip-flop DFF1; the CK pin of the second flip-flop DFF2 is used for receiving a clock signal HS _ CLK; a Q pin of the second flip-flop DFF2 is connected TO an input terminal of the second signal converting subunit S _ TO _ D2, so as TO convert the single-ended signal DIN _ IN into an emphasized signal DIN _ EMP, and transmit the emphasized signal DIN _ EMP TO the second signal converting subunit S _ TO _ D2; an OP pin at the output end of the second signal conversion subunit S _ TO _ D2 is connected with an IP pin at the input end of the second signal optimization subunit D _ BUF 2; the ON pin of the output end of the second signal conversion subunit S _ TO _ D2 is connected with the IN pin of the input end of the second signal optimization subunit D _ BUF 2; an OP pin of the output end of the second signal optimization subunit D _ BUF2 is connected with an IP pin of the input end of the emphasis signal logic conversion subunit REG _ E _ BUF; an ON pin at the output end of the second signal optimization subunit D _ BUF2 is connected with an IN pin at the input end of the emphasis signal logic conversion subunit REG _ E _ BUF; the enable end (namely an enable signal pin en) of the emphasis signal logic transformation subunit REG _ E _ BUF is connected with the output end of the second logic AND gate AND2; the input end of the second logic AND gate AND2 is respectively connected with an emphasis enable signal en _ emp AND an emphasis register signal reg _ emp; an IP pin of an input end of the high-speed output weighted sub-unit HS _ EMP is connected with an OP pin of an output end of the weighted signal logic conversion sub-unit REG _ E _ BUF, and an IN pin of an input end of the high-speed output weighted sub-unit HS _ EMP is connected with an ON pin of an output end of the weighted signal logic conversion sub-unit REG _ E _ BUF; an OP pin at the output end of the high-speed output weighted sub-unit HS _ EMP is connected with an ON pin at the output end of the high-speed output driving sub-unit HS _ DRIVER, and an ON pin at the output end of the high-speed output weighted sub-unit HS _ EMP is connected with an OP pin at the output end of the high-speed output driving sub-unit HS _ DRIVER; a node ON _ PAD is formed between an OP pin of an output end of the high-speed output weighted sub-unit HS _ EMP and an ON pin of an output end of the high-speed output driving sub-unit HS _ DRIVER, a node OP _ PAD is formed between an ON pin of an output end of the high-speed output weighted sub-unit HS _ EMP and an OP pin of an output end of the high-speed output driving sub-unit HS _ DRIVER, and the node ON _ PAD and the node OP _ PAD are connected through an off-chip resistor R2.
In the present invention, the internal circuit structure of the emphasized signal logic conversion sub-unit REG _ E _ BUF is the same as the internal circuit structure of the main signal logic conversion sub-unit REG _ BUF, and the internal circuit structure of the high-speed output emphasized sub-unit HS _ EMP is the same as the internal circuit structure of the high-speed output driving sub-unit HS _ DRIVER, which are not described herein again. And the weighted register signal reg _ EMP is used for respectively controlling the operation and the turn-off of a plurality of groups of tone modifying sub-UNITs UNIT in the high-speed output weighted sub-UNIT HS _ EMP, thereby realizing the effect of controlling the weighted amplitude. Specifically, the emphasis register signal REG _ EMP controls the sub-unit of the high-speed output emphasis sub-unit HS _ EMP through an OP0/1/2/3 pin of the output end of the emphasis signal logic conversion sub-unit REG _ E _ BUF and an ON0/1/2/3 pin of the output end; if the enable terminal en0=0 of the emphasis signal logic conversion subunit REG _ E _ BUF, the output terminal OP0=0, on0=0, and the corresponding trimming subunit UNIT is controlled to be turned off; if the emphasis signal logic transforms the enable terminal en0=1 of the subunit REG _ E _ BUF, and the output terminal OP0=1, on0=0, or OP0=0, on0=1, the corresponding trimming sub-UNIT is controlled to be turned on. It should be noted that, when the enable terminal en0=1 of the emphasis signal logic conversion subunit REG _ E _ BUF controls the corresponding trimming subunit UNIT to be turned ON, the output terminal OP0 is in phase with the delayed input signal, and ON0 is in reverse with the delayed input signal.
In the present invention, after the emphasis path unit 30 is turned on, it is assumed that the equivalent resistance output from the main path unit 20 is Rd and the equivalent resistance output from the emphasis path unit 30 is Re; when the single-ended signal DIN _ IN is pulled high from low, the input IP (i.e., the IP pin of the first signal optimization sub-unit D _ BUF 1) of the main path unit 20 is at high level, the input IN (i.e., the IN pin of the first signal optimization sub-unit D _ BUF 1) is at low level, and since the first flip-flop DFF1 is still before the rising edge of HS _ CLK or before DIN _ IN, the IP _ EMP (i.e., the IP pin of the second signal optimization sub-unit D _ BUF 2) of the emphasis path unit 30 is at low level, and the IN _ EMP (i.e., the IN pin of the second signal optimization sub-unit D _ BUF 2) is at high level; at this time, a resistance network equivalent circuit composed of the high-speed output driving sub-unit HS _ DRIVER, the high-speed output weighting sub-unit HS _ EMP and the off-chip resistor R2 is as shown in fig. 12, and current flows through a parallel branch composed of Rd and Re from VLDO, then flows through the off-chip resistor R2, and then flows through the parallel branch composed of Rd and Re and then is grounded (VSS); the voltage drop across the off-chip resistor R2 is Vh1= R2 VLDO (1 + rd/Re)/[ 2rd + R2 (1 + rd/Re) ]. Note that, when the main path unit 20 is turned on, the resistance from the output node P to 0.4VLDO is Rd; when the emphasis path unit 30 is turned on, the resistance of the output node P to 0.4VLDO is Re, and thus the equivalent resistance of the node P to 0.4VLDO is Rd in parallel with Re; similarly, the resistance of the output node N to VSS is the parallel connection of Rd and Re.
After a high-speed clock period, the HS _ CLK rises, the first trigger DFF1 outputs a signal following DIN _ IN, the IP _ EMP of the emphasis path UNIT 30 is pulled low, the IN _ EMP is pulled high, the first transistor MN1 and the fourth transistor MN4 of the corresponding trimming subunit UNIT IN the high-speed output emphasis subunit HS _ EMP are closed, and the second transistor MN2 and the third transistor MN3 are switched on; at this time, the equivalent circuit of the resistor network composed of the high-speed output driving sub-unit HS _ DRIVER, the high-speed output emphasis sub-unit HS _ EMP and the off-chip resistor R2 is shown in fig. 13, and the voltage drop across the off-chip resistor R2 is Vh2= R2 VLDO (1-Rd/Re)/[ 2rd + R2 (1 + Rd/Re) ]. Output | VOD | is reduced by R2 VLDO (2 Rd/Re)/[ 2Rd + R2 (1 + Rd/Re) ].
Similarly, when the single-ended signal DIN _ IN is pulled high to low, the voltage drop across the off-chip resistor R2 is-Vh 1 and-Vh 2, respectively, and the timing diagrams of the single-ended signal DIN _ IN, the emphasized signal DIN _ EMP, and the signal VOD are shown IN FIG. 14. By adding the emphasis function, the high-frequency part of the signal is emphasized, and the low-frequency signal is attenuated; by adjusting different emphasis amplitudes, the attenuation of the off-chip signal transmission line to the high-frequency part of the signal can be effectively compensated, and the signal output eye diagram is optimized.
When the high-speed data signal DIN is the PRBS9 signal at 4.5Gbps, the waveform and the eye pattern of the output signal are as shown in fig. 15 without turning on the emphasis path unit 30, and the attenuation of the high-frequency part of the waveform of the output signal is severe due to the loss on the output signal line, and the eye pattern jitter value is 52pS. After the emphasis path unit 30 is turned on, the waveform and the eye pattern of the output signal are as shown in fig. 16, and it can be seen that the waveform of the output signal is significantly optimized, the quality of the eye pattern is also improved, and the jitter value of the eye pattern is 3pS.
The embodiment of the invention also provides a vehicle-mounted video transmission chip, which comprises the high-speed receiving module provided by the embodiment of the invention.
According to the vehicle-mounted video transmission chip, the clock jitter value can be obviously optimized through the high-speed receiving module in the embodiment, and the product yield is effectively improved.
The foregoing description is only exemplary of the preferred embodiments of the invention and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the present invention is not limited to the specific combination of the above-mentioned features, and other embodiments formed by any combination of the above-mentioned features or their equivalents may be covered without departing from the spirit of the invention. For example, the above features and the features having similar functions in the present invention are mutually replaced to form the technical solution.
Claims (8)
1. A high-speed receiving module based on MIPI protocol is characterized by comprising:
the first-stage amplifier is used for performing small-amplitude gain amplification on input signals input from the positive input end INP and the negative input end INN and converting the common-mode voltage of the input signals from low voltage to high voltage; wherein, the input signal comes from the high-speed sending module;
a second-stage amplifier including a first amplifier SEC _ AMP1 and a second amplifier SEC _ AMP2; the signal from the first output terminal of the first-stage amplifier is input from the positive input terminal of the first amplifier SEC AMP1 and from the negative input terminal of the second amplifier SEC AMP2; the signal from the second output terminal of the first-stage amplifier is input from the negative input terminal of the first amplifier SEC AMP1 and from the positive input terminal of the second amplifier SEC AMP2; the first amplifier SEC _ AMP1 and the second amplifier SEC _ AMP2 amplify an input signal at a high gain, and output a first signal from the first amplifier SEC _ AMP1 and a second signal from the second amplifier SEC _ AMP2;
an inverting structure comprising a first input and a second input; and performing phase inverter cross processing on a first signal input from the first input end and a second signal input from the second input end to obtain a differential signal, and outputting one path of forward signal or reverse signal of the differential signal from an output end OUT.
2. The high-speed receive module of claim 1, wherein the inverting structure comprises a cross-inverter and a multiplexer MUX;
the cross inverter performs inverter cross processing on the input first signal and the input second signal, and inputs two paths of differential signals obtained by processing into the multi-path selector MUX;
and the multiplexer MUX selects a forward signal or a reverse signal to be output from the output end OUT according to preset parameters.
3. The high-speed receive module of claim 2, wherein the crossed inverter comprises:
the input end of the first inverter is a first input end of the inverting structure INV and is connected with the output end of the first amplifier SEC _ AMP 1;
the input end of the second inverter is a second input end of the inverting structure INV and is connected with the output end of the second amplifier SEC _ AMP 1;
the cross-coupled inverter consists of a third inverter and a fourth inverter; the input end of the third inverter and the output end of the fourth inverter are connected as the first end of the cross-coupled inverter; the output end of the third inverter is connected with the input end of the fourth inverter to be used as the second end of the cross-coupled inverter; the first end of the cross-coupled phase inverter is connected with the output end of the second phase inverter, and the second section of the cross-coupled phase inverter is connected with the output end of the second phase inverter;
the input end of the fifth inverter is connected with the second end of the cross-coupled inverter, and the output end of the fifth inverter is connected with one input end of the multiplexer MUX;
and the input end of the sixth phase inverter is connected with the first end of the cross-coupled phase inverter, and the output end of the sixth phase inverter is connected with one input end of the multiplexer MUX.
4. The high-speed receiving module according to claim 1, wherein the high-speed transmitting module comprises a triggering unit, a main path unit and a weighted path unit;
the input end of the main channel unit and the input end of the weighted channel unit are both connected with the output end of the trigger unit so as to respectively receive a high-speed data signal DIN through the trigger unit and respectively optimize the high-speed data signal DIN;
and the output end of the main channel unit and the output end of the emphasis channel unit are connected to perform superposition compensation on the optimized high-speed data signal DIN.
5. The high-speed reception module according to claim 4, characterized in that the triggering unit comprises a first trigger DFF1; a pin D of the first flip-flop DFF1 serves as an input terminal of a trigger unit, and is configured to receive the high-speed data signal DIN; the CK pin of the first trigger DFF1 is used for receiving a clock signal HS _ CLK; an RB pin of the first trigger DFF1 is connected with a first power supply VDD so as to provide power support for the first trigger DFF1 through the first power supply VDD; and a Q pin of the first trigger DFF1 is used as an output end of the trigger unit and is connected with input ends of the main path unit and the emphasis path unit.
6. The high-speed receiving module of claim 4, wherein the main path unit comprises a first signal conversion sub-unit S _ TO _ D1, a first signal optimization sub-unit D _ BUF1, a main signal logic conversion sub-unit REG _ BUF, a high-speed output driving sub-unit HS _ DRIVER, AND a first logic AND gate AND1;
the input end of the first signal conversion sub-unit S _ TO _ D1 is connected with the output end of the trigger unit and used for receiving the single-ended signal DIN _ IN output by the trigger unit and converting the single-ended signal DIN _ IN into a main differential signal for output;
the input end of the first signal optimization subunit D _ BUF1 is connected with the output end of the first signal conversion subunit S _ TO _ D1, and is used for receiving the main differential signal, optimizing the main differential signal TO form a main optimization signal and outputting the main optimization signal;
the input end of the main signal logic conversion subunit REG _ BUF is connected with the output end of the first signal optimization subunit D _ BUF1 and is used for receiving the main optimization signal; the enabling end of the main signal logic transformation subunit REG _ BUF is connected with the output end of the first logic AND gate AND1, so that the main signal logic transformation subunit REG _ BUF carries out logic transformation on the main optimization signal under the control action of the first logic AND gate AND1 to adjust the equivalent resistance output by the sending module;
the input end of the high-speed output driving sub-unit HS _ DRIVER is connected with the output end of the main signal logic transformation sub-unit REG _ BUF, AND is used for receiving the main optimization signal after logic transformation output by the main signal logic transformation sub-unit REG _ BUF AND changing the equivalent impedance output by the sending module under the control action of the first logic AND gate AND1; and the output end of the high-speed output driving sub-unit HS _ DRIVER is connected with the output end of the emphasis path unit.
7. The high-speed receiving module of claim 4, wherein the emphasis path unit comprises a second flip-flop DFF2, a second signal conversion sub-unit S _ TO _ D2, a second signal optimization sub-unit D _ BUF2, an emphasis signal logic conversion sub-unit REG _ E _ BUF, a high-speed output emphasis sub-unit HS _ EMP, AND a second logic AND gate AND2;
the input end of the second flip-flop DFF2 is connected with the output end of the trigger unit, and is configured to receive the single-ended signal DIN _ IN output by the trigger unit and convert the single-ended signal DIN _ IN into an emphasized signal DIN _ EMP for output;
the input end of the second signal conversion subunit S _ TO _ D2 is connected TO the output end of the second flip-flop DFF2, and is configured TO receive the emphasis signal DIN _ EMP and convert the emphasis signal DIN _ EMP into an emphasis differential signal for output;
the input end of the second signal optimization subunit D _ BUF2 is connected with the output end of the second signal conversion subunit S _ TO _ D2, and is configured TO receive the emphasized differential signal, optimize the emphasized differential signal TO form an emphasized optimized signal, and output the emphasized optimized signal;
the input end of the weighted signal logic conversion sub-unit REG _ E _ BUF is connected with the output end of the second signal optimization sub-unit D _ BUF2 and is used for receiving the weighted optimization signal; the enabling end of the emphasized signal logic transformation sub-unit REG _ E _ BUF is connected with the output end of the second logic AND gate AND2, so that the emphasized signal logic transformation sub-unit REG _ E _ BUF carries out logic transformation on the emphasized optimization signal under the control action of the second logic AND gate AND2 to adjust the equivalent resistance output by the sending module;
the input end of the high-speed output emphasis sub-unit HS _ EMP is connected with the output end of the emphasis signal logic transformation sub-unit REG _ E _ BUF, AND is used for receiving the emphasis optimization signal after logic transformation output by the emphasis signal logic transformation sub-unit REG _ E _ BUF AND changing the equivalent impedance output by the sending module under the control action of the second logic AND gate AND2; and the output end of the high-speed output emphasis sub-unit HS-EMP is connected with the output end of the main channel unit.
8. A vehicle-mounted video transmission chip, characterized by comprising the high-speed receiving module according to any one of claims 1 to 7.
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| CN118316438A (en) * | 2024-06-11 | 2024-07-09 | 核芯互联科技(青岛)有限公司 | Differential clock signal driving circuit |
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