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CN115332239A - POP packaging body structure and process method thereof - Google Patents

POP packaging body structure and process method thereof Download PDF

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Publication number
CN115332239A
CN115332239A CN202211046536.8A CN202211046536A CN115332239A CN 115332239 A CN115332239 A CN 115332239A CN 202211046536 A CN202211046536 A CN 202211046536A CN 115332239 A CN115332239 A CN 115332239A
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China
Prior art keywords
layer
copper
mold seal
bonding
mold
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CN202211046536.8A
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Chinese (zh)
Inventor
李子悦
张力
廖承宇
何洪文
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Payton Technology Shenzhen Co ltd
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Payton Technology Shenzhen Co ltd
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Priority to CN202211046536.8A priority Critical patent/CN115332239A/en
Publication of CN115332239A publication Critical patent/CN115332239A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3731—Ceramic materials or glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention discloses a POP packaging body structure and a process method thereof, wherein the POP packaging body structure comprises a radiating fin, a plurality of crystal grains connected through bonding wires are distributed on the radiating fin; and a second mold seal is arranged between the second PI layer and the first PI layer, the second PI layer is positioned at the top end of the second mold seal, the first mold seal is filled with a covering crystal grain, an opening is formed between the first PI layer and the first mold seal, copper is filled in the opening, the position of the opening corresponds to the PAD potential of a crystal grain bonding wire, the opening exposes a bonding wire, a plurality of copper columns matched with the opening are arranged at the top end of the second PI layer, the copper columns are filled and covered by the second mold seal, and chip particles are arranged at the middle position of the second mold seal. The surface of the chip comprises a radiating fin, so that the integral radiating function of the chip is improved; the substrate of the LPDDR is replaced by the RDL process, the thickness of the substrate is about 100um generally, the thickness of the RDL process is 30-50 um generally, the overall packaging thickness is reduced by 70-50 um, during the preparation process, the LPDDR packaging wafer can be subjected to electrical testing, bad products are screened, good products are reserved, and the fault tolerance rate is increased.

Description

POP packaging body structure and technological method thereof
Technical Field
The invention relates to the technical field of POP (package on package) packaging, in particular to a POP packaging body structure and a process method thereof.
Background
The trend of mobile consumer electronics is to be thinner and smaller, and therefore, it is necessary to reduce the chip area and volume by matching with some more special packaging structures. The chip adopting the POP packaging mode is widely used for devices such as mobile phones and flat panels, and has a large market scale.
The conventional POP package is formed by sealing two packages, i.e., a package POPt on which a chip is stacked and a package poppb on which a chip is stacked.
The POPt is packaged by a conventional substrate, and the interior of the POPt is packaged by a conventional stacking bonding wire bonding process and is used for circuit connection of a plurality of internal chips, wherein the chips are generally LPDDR memory chips.
POPb is generally a CPU or a controller, and there are two common packaging modes, one is a conventional "substrate + chip flip" package, and the other is a chip directly passing through FOWLP package, replacing the substrate with an RDL layer.
The POPt and POPb packaging bodies need to be connected together through high-temperature welding, and the welding process quality can be ensured only by ensuring that parameters such as the warping direction, the deformation size and the like of the POPt and POPb packaging bodies at different temperatures are the same. Therefore, various different types of packaging materials need to be tested to ensure the warping consistency of the POPt and the POPb packaging bodies, the material verification period is long, and the technical difficulty is high.
The disadvantages of the prior art are as follows:
1. the stacked chips are either used with a substrate using conventional bonding processes or stacked with costly wafer level TSV vias.
2. The thickness of the conventional substrate is generally 80-100 um, and the thickness is difficult to be reduced continuously.
3. After the chips are stacked more, the heat dissipation of the whole POPt packaging body is difficult.
4. The warpage parameters of both the POPt and POPb packages are difficult to be completely consistent.
A reasonably designed package structure and process flow are needed to solve the technical problems of package thickness, chip heat dissipation and warpage parameters.
Disclosure of Invention
The invention aims to solve the defects in the prior art and provides a POP packaging body structure and a process method thereof.
In order to achieve the purpose, the invention adopts the following technical scheme:
according to one aspect of the invention, a POP package structure is provided.
A POP packaging body structure comprises a heat radiating fin, wherein a plurality of crystal grains connected through bonding wires are distributed on the heat radiating fin;
the second PI layer is arranged between the second PI layer and the first PI layer, the second PI layer is located at the top end of the second PI layer, the first PI layer is filled and covers the crystal grains, an opening is formed between the first PI layer and filled with copper, the position of the opening corresponds to the PAD potential of the bonding wires of the crystal grains, the opening exposes the bonding wires, a plurality of copper columns matched with the opening are arranged at the top end of the second PI layer and filled and covered by the second PI layer, chip particles are arranged in the middle of the second PI layer, a plurality of Bump copper columns are arranged on the surfaces of the chip particles and inside the second PI layer, the Bump copper columns are connected with the chip particles and the copper column circuits through RDL wiring, and solder balls are arranged at the top ends of the Bump copper columns in the second PI layer.
Furthermore, the types of the crystal grains at least comprise one type, and when the crystal grains are stacked, at least one crystal grain is adopted for stacking.
Further, the height of the mold seal is not lower than the top of the bonding wire of the die, and the height of the mold seal exceeds 30um to 100um of the top of the bonding wire.
Further, the height of copper post is greater than the thickness of chip granule.
Further, the crystal grains and the chip particles are adhered and fixed through an adhesive film or a dispensing process.
According to another aspect of the invention, a fabrication process for a POP package structure is provided.
A process method of a POP packaging body structure comprises the following steps:
s1, placing a radiating fin on a carrier plate, and bonding the carrier plate and the radiating fin together through temporary bonding glue;
s2, selecting a plurality of crystal grains, wherein the crystal grains specifically comprise DIE1, DIE2, DIE3 and DIE4, and sticking and fixing the crystal grains on the radiating fins by using an adhesive film;
s3, adopting a conventional bonding process between every two crystal grains (6), and respectively connecting circuits of DIE1 and DIE2, and circuits of DIE3 and DIE4 by using bonding wires;
s4, performing mould sealing filling on the stacked structure to form a mould seal I;
s5, punching a hole in one surface of the mold seal, aligning PAD positions of bonding wires PAD of DIE2 and DIE4 at the punching position to expose a bonding wire, depositing a UBM seed layer through PVD according to a conventional bumping process, filling copper in the hole through photoetching, electroplating and etching processes, and generating a plurality of layers of RDL circuit layers and a PI layer I;
s6, growing a copper column on the PI layer I according to a bumping process;
s7, selecting chip particles, and pasting the chip particles on the PI layer I through a DAF or dispensing process, wherein the chip particles are the chip particles DIE5 which have already finished the Bumping process in the step S6 and grow Bump copper columns;
s8, performing mold sealing treatment on the Bump copper column and the DIE5 in the step S7 to form a second mold seal, wherein the height of the second mold seal is higher than that of the Bump copper column;
s9, performing CMP grinding and thinning on the top of the packaging body in the step S8, grinding to the same plane with the same height, and exposing the copper column and the Bump copper column;
s10, manufacturing a multilayer RDL circuit layer and a PI layer II again according to a conventional bumping process, and interconnecting the copper columns and the Bump copper columns through RDL wiring;
s11, forming a solder ball at a specified position through an electroplating or ball planting process;
and S12, removing the adhesiveness of the temporary bonding glue of the lower carrier plate in a heating or laser glue-dissolving mode to detach the carrier plate.
Further, in step S1, the carrier is made of glass or silicon wafer, and the heat sink is made of any one of metal, ceramic, or silicon.
Further, in step S3, the step of connecting the circuits of DIE1 and DIE2, and DIE3 and DIE4 respectively is:
a ball mounting bump is made on the PAD position of the bonding wire PAD of each DIE, wherein a gold wire or a silver wire material is used;
wire bonding is performed using the commonly used reverse wire bonding mode.
Further, in step S5, the punching specifically includes the following steps:
adopting laser punching, wherein the punching position needs to be opposite to bonding wire PAD PAD positions of DIE2 and DIE4, each DIEPAD independently punches holes, wherein the size of the bonding wire PAD PAD position is 50-60 um, the diameter of the laser punching is 20-40 um, after a mould sealing layer is removed by laser ablation, independent hole positions are formed,
compared with the prior art, the invention has the beneficial effects that: the surface of the chip comprises the radiating fins which are made of ceramic, metal and other materials which are easy to machine and form, so that the radiating fins have a quick radiating effect and increase the integral radiating effect of the chip;
the substrate of the LPDDR is replaced by the RDL process, the thickness of the substrate is about 100um generally, the thickness of the RDL process is 30-50 um generally, the overall packaging thickness can be reduced by 70-50 um, the cost of the traditional wire bonding process is kept in stacking, and a high-cost packaging mode of the TSV stacking process is not needed;
in addition, the packaged crystal grains can be determined to be the same type of crystal grains or different types of crystal grains according to the actual product design, meanwhile, in the preparation process, the LPDDR packaging wafer can be subjected to electrical test, bad products are screened, good products are reserved, and the fault tolerance rate is increased.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic diagram of an overall structure of a POP package structure according to the present invention;
fig. 2 is a schematic diagram of step 1 of the process method of the POP package structure according to the present invention;
fig. 3 is a schematic diagram of step 2 of the process of the POP package structure according to the present invention;
fig. 4 is a schematic diagram of step 3 of the process of the POP package structure according to the present invention;
fig. 5 is a schematic diagram of step 4 of the process of the POP package structure according to the present invention;
fig. 6 is a schematic diagram of step 5 of the process of POP package structure proposed by the present invention;
fig. 7 is a schematic diagram of step 6 of the process of POP package structure proposed by the present invention;
fig. 8 is a schematic diagram of step 7 of the process of POP package structure proposed by the present invention;
fig. 9 is a schematic diagram of step 8 of the POP package structure process proposed in the present invention;
fig. 10 is a schematic diagram of step 9 of the POP package structure process proposed in the present invention;
fig. 11 is a schematic diagram of step 10 of the process of POP package structure proposed by the present invention;
fig. 12 is a schematic diagram of step 11 of the POP package structure processing method according to the present invention;
fig. 13 is a schematic diagram of the punching step in step 3 of the POP package structure processing method according to the present invention.
In the figure: 1. a heat sink; 2. a first PI layer; 3. a PI layer II; 4. molding and sealing one; 5. molding and sealing II; 6. a crystal grain; 7. and (7) a copper column.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
According to an embodiment of the present application, a POP package structure is provided.
Referring to fig. 1, the POP package structure includes a heat sink 1, wherein a plurality of dies 6 connected by bonding wires are distributed on the heat sink 1;
a first PI layer 2, a first mold seal 4 is arranged between the first PI layer 2 and the radiating fin 1, and the first PI layer 2 is positioned at the top end of the first mold seal 4;
the PI layer II 3, a mold seal II 5 is arranged between the PI layer II 3 and the PI layer I2, the PI layer II 3 is located at the top end of the mold seal II 5, the mold seal I4 is filled to cover the crystal grain 6, an opening is formed between the PI layer I2 and the mold seal I4, copper is filled in the opening, the position of the opening corresponds to the PAD potential of a bonding wire of the crystal grain 6, the opening exposes a bonding wire, a plurality of copper columns 7 matched with the opening are arranged at the top end of the PI layer II 3, the copper columns 7 are filled and covered by the mold seal II 5, 1-2 chip particles are arranged in the middle of the mold seal II 5, a plurality of Bump copper columns are arranged on the surfaces of the chip particles and inside the PI layer II 3, the Bump copper columns are electrically interconnected with the chip particles and the copper columns 7 through RDL wiring, and solder balls are arranged at the top end of the Bump copper columns inside the PI layer II 3.
In a specific embodiment of the present application, the types of the dies 6 include at least one type, and when the dies 6 are stacked, at least one of the dies 6 is used for stacking.
In a specific embodiment of the present application, the first mold seal 4 has a height not lower than the top of the bonding wire of the die 6, and the first mold seal 4 has a height exceeding the top of the bonding wire by 30um to 100um.
In the specific embodiment of this application, the height of copper post 7 is greater than the thickness of chip granule, crystalline grain 6 with the chip granule is all pasted fixedly through adhesive film or some glue technology.
According to the embodiment of the invention, a preparation process for the POP packaging body structure is further provided.
It should be noted that, in this embodiment: the number of the selected crystal grains 6 is 4, the selected crystal grains 6 are the same type of crystal grains 6, the crystal grains 6 are stacked in pairs, and the number of the selected chip particles is 1.
A process method of a POP packaging body structure comprises the following steps:
s1, placing a radiating fin 1 on a carrier plate, and bonding the carrier plate and the radiating fin (1) together through temporary bonding glue; (see FIG. 2 in detail)
Specifically, the heat sink 1 is used as a part of the package body, and is packaged at one time without being additionally added, the thickness of the heat sink 1 is customized according to actual needs, and the thickness range can be from dozens of micrometers to hundreds of micrometers.
S2, selecting a plurality of crystal grains 6, wherein the crystal grains 6 specifically comprise DIE1, DIE2, DIE3 and DIE4, and sticking and fixing the crystal grains 6 on the radiating fin 1 by using an adhesive film; (see FIG. 3 in detail)
S3, adopting a conventional bonding process between every two crystal grains 6, and respectively connecting circuits of DIE1 and DIE2, and circuits of DIE3 and DIE4 by using bonding wires; (see FIG. 4 in detail)
Specifically, the step of connecting the circuits of DIE1 and DIE2, and DIE3 and DIE4 respectively is as follows:
a ball mounting bump is made on the PAD position of the bonding wire PAD of each DIE, wherein a gold wire or a silver wire material is used;
wire bonding is performed using the commonly used reverse wire bonding mode. (see FIG. 4 in detail)
It should be noted that, if the gold ball bump exists, the laser drilling only hits the gold ball, and the chip pad is not damaged.
S4, performing mould sealing filling on the stacked structure to form a mould sealing I4; (see FIG. 5 in detail)
Specifically, after the RDL is completed, the LPDDR package wafer may be electrically tested, a bad product may be screened, and a good product may be retained, where it should be noted that, because the chip particles DIE5 are generally CPU chips, the product value is relatively high, and the electrical test may avoid waste of DIE5 caused by matching the bad product of the previous process with DIE5 crystal grains 6.
S5, punching the surface of the first mold seal 4, aligning the positions of the punched holes with PAD positions of bonding wires PAD of DIE2 and DIE4 to expose bonding wires, depositing a UBM seed layer through PVD according to a conventional bumping process, filling copper into the opened holes through photoetching, electroplating and etching processes, and generating a plurality of layers of RDL circuit layers and a PI layer 2; (see FIG. 6 in detail)
Specifically, the punching specifically comprises the following steps:
and laser punching is adopted, the punching position needs to be right opposite to bonding wire PAD PAD positions of DIE2 and DIE4, each DIEPAD independently punches, wherein the size of the bonding wire PAD PAD position is 50-60 um, the diameter of the laser punching is 20-40 um, and after the DIE sealing layer is removed by laser ablation, independent hole positions are formed.
S6, growing a copper column 7 on the PI layer I2 according to a bumping process; (see FIG. 7 in detail)
S7, selecting chip particles, and pasting the chip particles on the PI layer I2 through a DAF or dispensing process, wherein the chip particles are the chip particles DIE5 which have already finished the Bumping process in the step S6 and grow Bump copper columns; (see FIG. 8 in detail)
S8, performing mold sealing treatment on the Bump copper column and the DIE5 in the step S7 to form a second mold seal 5, wherein the height of the second mold seal 5 is higher than that of the Bump copper column; (see FIG. 9 in detail)
S9, performing CMP grinding and thinning on the top of the packaging body in the step S8, grinding to the same plane with the same height, and exposing the copper column 7 and the Bump copper column; (see FIG. 10 in detail)
S10, manufacturing a plurality of layers of RDL circuit layers and a second PI layer 3 again according to a conventional bumping process, and interconnecting the copper columns 7 and the Bump copper columns through RDL wiring; (see FIG. 11 in detail)
S11, forming a solder ball at a designated position through an electroplating or ball planting process; (see FIG. 12 in detail)
And S12, removing the adhesiveness of the temporary bonding glue of the lower carrier plate in a heating or laser glue-dissolving mode to detach the carrier plate. (see FIG. 1 in detail)
In a specific embodiment of the present application, in step S1, the carrier is made of glass or a silicon wafer, and the heat sink 1 is made of any one of metal, ceramic, or silicon.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.

Claims (9)

1. A POP packaging body structure comprises a heat radiating fin (1), wherein a plurality of crystal grains (6) connected through bonding wires are distributed on the heat radiating fin (1);
a first PI layer (2), wherein a first mold seal (4) is arranged between the first PI layer (2) and the heat sink (1), and the first PI layer (2) is positioned at the top end of the first mold seal (4);
the PI layer II (3), a mold seal II (5) is arranged between the PI layer II (3) and the PI layer I (2), the PI layer II (3) is located at the top end of the mold seal II (5), the mold seal I (4) is filled and covered on the crystal grain (6), an opening is formed between the PI layer I (2) and the mold seal I (4), copper is filled in the opening, the position of the opening corresponds to the PAD potential of the crystal grain (6), the bonding wire is exposed from the opening, a plurality of copper columns (7) matched with the opening are arranged at the top end of the PI layer II (3), the copper columns (7) are filled and covered by the mold seal II (5), 1-2 chip bonding wire particles are arranged in the middle of the mold seal II (5), a plurality of Bump copper columns are arranged on the surface of the chip particles and inside the PI layer II (3), the Bump copper columns are connected with the chip particles and the plurality of the copper columns (7) through RDL wiring, and the Bump copper columns are located at the top end of the PI layer II (3).
2. POP package structure according to claim 1, characterized in that the type of the dies (6) comprises at least one type, and when the dies (6) are stacked, at least one die (6) is used for stacking.
3. The POP package structure of claim 2, wherein the height of the first mold (4) is not lower than the top of the bonding wire of the die (6), and the height of the first mold (4) exceeds the top of the bonding wire by 30-100 um.
4. POP package structure according to claim 3, characterized in that the height of the copper pillars (7) is greater than the thickness of the chip grains.
5. The POP package structure of claim 4, wherein the die (6) and the chip particles are bonded and fixed by an adhesive film or a dispensing process.
6. A process method of a POP packaging body structure is used for the preparation process of the POP packaging body structure of any one of claims 1-5, and is characterized by comprising the following steps:
s1, placing a radiating fin (1) on a carrier plate, and bonding the carrier plate and the radiating fin (1) together through temporary bonding glue;
s2, selecting a plurality of crystal grains (6), wherein the crystal grains (6) specifically comprise DIE1, DIE2, DIE3 and DIE4, and sticking and fixing the crystal grains (6) on the radiating fin (1) by using an adhesive film;
s3, adopting a conventional bonding process between every two crystal grains (6), and respectively connecting circuits of DIE1 and DIE2, and circuits of DIE3 and DIE4 by using bonding wires;
s4, performing mold sealing filling on the stacked structure to form a first mold seal (4);
s5, punching the surface of the first mold seal layer (4), aligning the positions of the punched holes with PAD positions of bonding wires PAD of DIE2 and DIE4 to expose bonding wires, depositing a UBM seed layer through PVD according to a conventional bumping process, filling copper into the holes through photoetching, electroplating and etching processes, and generating a plurality of layers of RDL circuit layers and PI layers I (2);
s6, growing a copper column (7) on the PI layer I (2) according to a bumping process;
s7, selecting chip particles, and pasting the chip particles on the PI layer I (2) through a DAF or dispensing process, wherein the chip particles are the chip particles DIE5 which have completed the Bumping process in the step S6 and grow Bump copper columns;
s8, performing mold sealing treatment on the Bump copper column and the DIE5 in the step S7 to form a second mold seal (5), wherein the height of the second mold seal (5) is higher than that of the Bump copper column;
s9, performing CMP grinding and thinning on the top of the packaging body in the step S8, grinding to the same plane with the same height, and exposing the copper column (7) and the Bump copper column;
s10, manufacturing a multilayer RDL circuit layer and a PI layer II (3) again according to a conventional bumping process, and interconnecting the copper pillar (7) and the Bump copper pillar through RDL wiring;
s11, forming a solder ball at a designated position through an electroplating or ball planting process;
and S12, removing the adhesiveness of the temporary bonding glue of the lower carrier plate in a heating or laser glue-dissolving mode to detach the carrier plate.
7. The process method of the POP package structure according to claim 6, wherein in the step S1, the carrier is made of glass or silicon wafer, and the heat sink (1) is made of any one of metal, ceramic or silicon.
8. The process of POP package structure of claim 7, wherein in step S3, the step of connecting the circuits of DIE1 and DIE2, DIE3 and DIE4 respectively is:
a ball mounting bump is made on the PAD position of the bonding wire PAD of each DIE, wherein a gold wire or a silver wire material is used;
wire bonding is performed using the commonly used reverse wire bonding mode.
9. The process of the POP package structure of claim 8, wherein in step S5, the punching specifically comprises the following steps:
by adopting laser drilling, the drilling position needs to be over against the PAD positions of the bonding wires PAD of DIE2 and DIE4, each DIEPAD independently drills, wherein the size of the PAD position of the bonding wire PAD is 50-60 um, the diameter of the laser drilling is 20-40 um, and after the DIE sealing layer is removed by laser ablation, independent hole positions are formed.
CN202211046536.8A 2022-08-30 2022-08-30 POP packaging body structure and process method thereof Pending CN115332239A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211046536.8A CN115332239A (en) 2022-08-30 2022-08-30 POP packaging body structure and process method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211046536.8A CN115332239A (en) 2022-08-30 2022-08-30 POP packaging body structure and process method thereof

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Publication Number Publication Date
CN115332239A true CN115332239A (en) 2022-11-11

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CN202211046536.8A Pending CN115332239A (en) 2022-08-30 2022-08-30 POP packaging body structure and process method thereof

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