CN115332227A - The method of chip area layout - Google Patents

Abstract

A method for chip area typesetting comprises the following steps: providing a preset wafer area, a process node and a preset chip area; arranging a plurality of rectangular initial chip regions which are mutually independent in a preset wafer region according to the area of a preset chip, wherein the initial chip regions have an initial preset length and an initial preset width; debugging the initial preset length and the initial preset width for a plurality of times according to the preset chip area and the process node so as to arrange a plurality of mutually independent rectangular chip areas in the preset wafer area, wherein the chip areas have the preset chip area, and the number of the chip areas is greater than that of the preset chip areas. The chip area typesetting method can improve the number of chips which can be manufactured on one wafer, reduce the waste of raw materials and improve the productivity and benefit of semiconductor manufacturing.

Description

The method of typesetting the chip area

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method for layout of chip regions.

Background technique

With the rapid development of integrated circuit manufacturing technology, the size of electronic devices in integrated circuits is getting smaller and smaller, and the integration level of integrated circuits is getting higher and higher. Correspondingly, with the integration level of integrated circuits getting higher and higher, the number of chips that can be formed on a wafer (wafer) is increasing.

Usually, in the prior art, before chip design, simulation deduction will be carried out according to the wafer size and several preset chip shapes, roughly in the wafer area corresponding to the wafer, the chip corresponding to each chip shape The area is typesetting several times to form a corresponding chip area typesetting scheme. Through each chip area layout scheme, it is possible to obtain the number of chips that can be manufactured under the corresponding chip shape on a wafer, and the layout methods of multiple chip shapes on the wafer, etc. Next, after selecting a chip layout scheme, follow-up chip design is performed according to the shape of the chip in the chip layout scheme.

As we all know, wafers are disposable raw materials, and each wafer is expensive. Therefore, it is necessary to manufacture as many chips as possible on a wafer to make full use of raw materials and improve the production capacity and efficiency of semiconductor manufacturing.

However, the number of chips that can be manufactured on a single wafer is relatively small in the chip area layout scheme of the prior art, resulting in waste of raw materials and poor productivity and efficiency of semiconductor manufacturing.

Contents of the invention

The technical problem to be solved by the present invention is to provide a method for typesetting chip regions, so as to increase the number of chips that can be manufactured on a wafer, reduce the waste of raw materials, and improve the productivity and efficiency of semiconductor manufacturing.

In order to solve the above technical problems, the technical solution of the present invention provides a method for typesetting a chip area, including: providing a preset wafer area, a process node, and a preset chip area; Lay out a plurality of rectangular initial chip areas that are independent of each other, and the initial chip area has an initial preset length and an initial preset width; perform several times of debugging on the initial preset length and initial preset width according to the preset chip area and process node processing to arrange a plurality of mutually independent rectangular chip areas in a preset wafer area, and the chip areas have a preset chip area, and the number of the chip areas is greater than the number of the preset chip areas.

Optionally, the number of times of the debugging process is more than 2; each time the method of the debugging process includes: adjusting the initial preset length and the initial preset width according to the preset chip area and process node, and obtaining the debugging preset length and Debugging preset width, each debugging preset length is different, and each debugging preset width is different; according to the debugging preset length and debugging preset width, multiple independent rectangular debuggings are arranged in the preset wafer area A chip area, the debugging chip area has a preset chip area.

Optionally, the method for performing several times of debugging includes: providing a preset number of times of debugging; performing the debugging process for the preset number of times of debugging, and obtaining a debugging preset length and a debugging preset width corresponding to each debugging process.

Optionally, the method for performing several debugging processes also includes: providing a preset change percentage, a preset change function or a preset change amount; the method for each debugging process also includes: according to the preset change percentage, the preset change function or The preset change amount is to change the debugging preset length and debugging preset width acquired in the n-1th time to form the debugging preset length and debugging preset width acquired in the nth time, wherein n is a natural number greater than or equal to 2.

Optionally, the initial preset length and the initial preset width are debugged several times according to the preset chip area and process node, so that the method of arranging multiple independent rectangular chip areas in the preset wafer area includes : According to the one with the largest number of debugging chip areas arranged in several debugging processes, a plurality of mutually independent rectangular chip areas are arranged in the preset wafer area, and the chip areas have the corresponding debugging presets for this debugging process. Set length and debug preset width.

Optionally, the initial preset length and the initial preset width are debugged several times according to the preset chip area and process node, so as to arrange a plurality of mutually independent rectangular chip areas in the preset wafer area. Including: when the most and the same number of debug chip areas are arranged for several times in several debugging processes, according to the time when the largest number of debug chip areas is arranged for the first time, arrange multiple independent chips in the preset wafer area. A rectangular chip area, the chip area has a debugging preset length and a debugging preset width corresponding to this debugging process.

Optionally, it also includes: providing a preset scribe width; arranging the initial chip regions according to the preset scribe width, wherein there is the preset scribe width between adjacent initial chip regions; The debugging process is performed several times according to the street width, wherein the preset dicing street width exists between adjacent chip regions.

Optionally, the preset wafer area includes a groove area and a wafer identification area, the groove area is used for fixing the wafer, the groove area is independent from the initial chip area, the groove area The groove area and the chip area are independent of each other. The wafer identification area is used to form marks to distinguish each wafer. The wafer identification area and the initial chip area are independent of each other. The wafer identification area and the chip area independent of each other.

Optionally, it also includes: providing the width of the edge area; arranging the initial chip area according to the width of the edge area, the minimum distance between the edge of the initial chip area and the edge of the predetermined wafer area is greater than or equal to the width of the edge area ; performing the debugging process several times according to the width of the edge area, wherein the minimum distance between the edge of the chip area and the edge of the preset wafer area is greater than or equal to the width of the edge area.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the chip region typesetting method provided by the technical solution of the present invention, since the chip region has a preset chip area and is obtained after adjustment based on the process node, the chip region meets the design requirements of a chip with the preset chip area. On this basis, after the initial chip area is arranged, the initial preset length and the initial preset width are debugged several times according to the preset chip area and process node, so that the arrangement in the preset wafer area is independent of each other. Therefore, through the debugging process, fine debugging can be carried out on the basis of the layout of the initial chip area, and a larger number of chip areas than the initial chip area can be formed in the preset wafer area , Thus, a more optimized chip area layout method and a more reasonable chip area shape are obtained, thereby increasing the number of chips that can be manufactured on a wafer, reducing the waste of raw materials, and improving the productivity and efficiency of semiconductor manufacturing.

Description of drawings

FIG. 1 is a schematic flow chart of a method for typesetting a chip area according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a preset wafer area;

Fig. 3 is a layout schematic diagram of the initial chip area;

FIG. 4 is a schematic flow chart of the debugging process in FIG. 1;

FIG. 5 is a layout diagram of the debug chip area.

Detailed ways

As mentioned in the background art, in the chip area layout scheme of the prior art, the number of chips that can be manufactured on a wafer is small, resulting in waste of raw materials, and poor productivity and efficiency of semiconductor manufacturing.

In order to solve the above-mentioned technical problems, an embodiment of the present invention provides a method for laying out a chip area. By performing several debugging processes on the initial preset length and initial preset width according to the preset chip area and process node, the preset chip area A plurality of mutually independent rectangular chip areas are arranged in the circular area, and the chip area has a preset chip area, and the number of the chip areas is greater than the number of the preset chip areas, which can improve the ability to manufacture on a wafer. The number of chips, reduce the waste of raw materials, improve the production capacity and efficiency of semiconductor manufacturing.

In order to make the above objects, features and beneficial effects of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 1 is a schematic flowchart of a method for laying out chip regions according to an embodiment of the present invention.

Please refer to Figure 1, the method for layout of the chip area includes:

Step S100, providing a preset wafer area, a process node and a preset chip area;

Step S110, arranging a plurality of mutually independent rectangular initial chip areas in the preset wafer area according to the preset chip area, the initial chip areas have an initial preset length and an initial preset width;

Step S120, according to the preset chip area and process node, perform several debugging processes on the initial preset length and initial preset width, so as to arrange a plurality of mutually independent rectangular chip areas in the preset wafer area, and, the The chip area has a preset chip area, and the number of the chip areas is greater than the number of the preset chip areas.

The process node refers to the minimum line width achieved by the semiconductor structure during the processing of the integrated circuit, that is, the feature size achieved by the semiconductor structure.

Since the chip area has a preset chip area and is obtained after adjustment based on a process node, the chip area meets the design requirements of a chip with the preset chip area. On this basis, after the initial chip area is arranged, the initial preset length and the initial preset width are debugged several times according to the preset chip area and process node, so that the arrangement in the preset wafer area is independent of each other. Therefore, through the debugging process, fine debugging can be carried out on the basis of the layout of the initial chip area, and a larger number of chip areas than the initial chip area can be formed in the preset wafer area , Thus, a more optimized chip area layout method and a more reasonable chip area shape are obtained, thereby increasing the number of chips that can be manufactured on a wafer, reducing the waste of raw materials, and improving the productivity and efficiency of semiconductor manufacturing.

Please refer to FIG. 2 . FIG. 2 is a schematic diagram of a predetermined wafer area in FIG. 1 , providing a predetermined wafer area 100 .

In this embodiment, the preset wafer area 100 is provided according to the diameter size D of the wafer that is scheduled to be used during chip manufacturing.

For example, in the chip manufacturing process, when a wafer with a diameter of 200mm is scheduled to be used, the preset wafer area is provided by simulating the area corresponding to the shape of the wafer with this diameter.

It should be understood that the preset wafer area is not limited to being provided based on a wafer with a diameter of 200 mm. For example, when a wafer with a diameter of 300 mm is intended to be used, the preset wafer area 100 is provided based on a wafer with a diameter of 300 mm.

In this embodiment, the preset chip area S is provided according to the occupied area of the chip.

Specifically, before the final detailed design of the chip, the required area of the chip is estimated according to the process node, the functional requirements of the chip, etc., so as to determine the preset chip area S corresponding to the chip.

In this embodiment, the preset wafer area 100 includes a groove area 101 (notch) and a wafer identification area 102 (Id Zone area), and the wafer identification area 102 is used to form marks for distinguishing each wafer .

In this embodiment, the groove area 101 is located in the wafer marking area 102 .

It should be noted that although the preset wafer area 100 , the groove area 101 and the wafer identification area 102 are shown separately in FIG. 2 . However, in the actual process of typesetting the chip area, the preset wafer area 100, the preset groove area 101 and the wafer identification area can be obtained and displayed separately by providing the wafer size (such as the diameter size D of the wafer) 102. It is also possible to acquire the corresponding preset wafer area 100, groove area 101 and wafer identification area 102 during the execution of step S110, and make the preset wafer area 100, groove area 101 and wafer identification area Area 102 is displayed synchronously with the arranged multiple initial chip areas.

Please refer to FIG. 3. FIG. 3 is a schematic diagram of the layout of the initial chip area. According to the preset chip area S, a plurality of mutually independent rectangular initial chip areas 110 are arranged in the preset wafer area 100. The initial chip area 110 has Initial preset length H _X and initial preset width W _X .

Specifically, the area of each initial chip region 110 is the predetermined chip area S.

In this embodiment, the method for arranging a plurality of mutually independent rectangular initial chip regions 110 in the preset wafer region 100 according to the preset chip area S includes: obtaining the initial preset length H _X according to the preset chip area S and the initial preset width W _X , wherein the product of the initial preset length H _X and the initial preset width W _X is equal to the preset chip area S; a plurality of initial preset lengths H _X and initial preset width W _X The rectangular areas are arranged in an array along the first direction X and the second direction Y in the preset wafer area 100, and the rectangular area with an initial preset length H _X and an initial preset width W _X is the initial chip area 110, the first The first direction X and the second direction Y are perpendicular to each other.

In this embodiment, the groove area 101 is independent from the initial chip area, and the wafer identification area 102 is independent from the initial chip area. Specifically, the initial chip area 110 is arranged in areas other than the groove area 101 and the wafer identification area 102 in the predetermined wafer area 100 .

In this embodiment, a preset cutting line width M is provided. Moreover, while arranging the plurality of initial chip regions 110 according to the predetermined chip area S, the initial chip regions 110 are also arranged according to the predetermined scribe line width M. Specifically, there is the preset scribe width M between adjacent initial chip regions 110 , that is, there is a scribe region between adjacent initial chip regions 110 .

In this embodiment, an edge region width W _E (Edge Exclusion) is provided. Moreover, while arranging the plurality of initial chip regions 110 according to the preset chip area _S , the initial chip regions 110 are also arranged according to the edge region width WE. Specifically, the minimum distance between the edge of the initial chip area 110 and the edge of the preset wafer area 100 is greater than or equal to the edge area width W _E .

By making the preset dicing line width M between adjacent initial chip regions 110, and making the minimum distance between the edge of the initial chip region 110 and the edge of the preset wafer region 100 greater than or equal to the edge region width W _E , the layout of the initial chip area 110 and the layout of the debug chip area in the subsequent debugging process can have the same restriction conditions.

It should be noted that, FIG. 3 only schematically shows part of the initial chip area 110 arranged in the predetermined wafer area 100 . At the same time, although in FIG. 3, the preset wafer area 100, the groove area 101, the wafer identification area 102 and the initial chip area 110 are schematically shown for ease of understanding, but the preset wafer area may not be displayed in step S110. The circle area 100, the groove area 101, the wafer identification area 102 and the initial chip area 110, but through the provided wafer size (such as the diameter size D of the wafer), the initial preset length H _X and the initial preset width W The parameters such as _X are calculated, and the parameters related to the layout of the initial chip area 110 such as the number of the initial chip area 110 are output.

In this embodiment, the number of debugging processes in step S120 is 2 or more. Through more than two debug processes, at least two sets of parameters corresponding to the debug processes can be obtained, thereby facilitating the arrangement of a greater number of chip areas in the preset wafer area 100 .

In other embodiments, the number of debugging processes in step S120 is 1 time.

Please refer to FIG. 4. FIG. 4 is a schematic flow chart of the debugging process in FIG. 1, and each method of the debugging process includes:

Step S121, adjust the initial preset length and the initial preset width according to the preset chip area and process node, and obtain the debugging preset length and debugging preset width, each debugging preset length is different, and each debugging preset width is different ;

Step S122 , arranging a plurality of mutually independent rectangular debugging chip areas in the preset wafer area according to the debugging preset length and the debugging preset width, and the debugging chip areas have a preset chip area.

Please refer to Figure 5. Figure 5 is a schematic diagram of the layout of the debug chip area. Adjust the initial preset length H _X and initial preset width W _X according to the preset chip area S and process node, and obtain the debug preset length H _T and debug preset Width W _T , the preset length H _T of debugging is different each time, and the preset width W _T of debugging is different each time; it is arranged in the preset wafer area 100 according to the preset length H _T of debugging and the preset width W _T of debugging Multiple rectangular debug chip areas 120 that are independent from each other, and the debug chip areas 120 have a predetermined chip area S.

Specifically, the debug chip area 120 has a preset debug length H _T and a preset debug width W _T , and the product of the preset debug length H _T and the preset debug width W _T is equal to the preset chip area S.

It should be noted that, for the sake of easy understanding, FIG. 5 schematically shows the layout diagrams of two kinds of debugging chip regions 120, and in the layout diagrams of each debugging chip region 120, they are only schematically shown in the preset Part of the debug chip area 120 arranged in the wafer area 100 . In FIG. 5 , the schematic layout of each debugging chip area 120 corresponds to the result after one debugging process, and in the layout schematic diagrams of the two types of debugging chip areas 120 , the shapes and sizes of the debugging chip areas 120 are different. Specifically, in a typesetting schematic diagram of the debugging chip area 120, the debugging chip area 120 has a debugging preset length H _T1 and a debugging preset width W _T1 ; in another type of layout schematic diagram of the debugging chip area 120, the debugging chip area 120 has a preset length H _T2 and a width W _T2 , and the default length H _T1 is different from the length H _T2 , and the width W _T1 is different from the width W _T2 .

It should be noted that, in the actual debugging process, although the debugging preset length H _T is different each time, the debugging preset width W _T is different each time, that is, the layout of the debugging chip area 120 is different each time. However, after each debugging process, the number of debug chip regions 120 arranged in the preset wafer region 100 may be the same or may not be the same.

It should be understood that the number of debugging processes is not limited to two, and may be performed three or more times according to actual needs.

In this embodiment, the method for performing several debugging processes includes: providing a preset number of times of debugging; performing the debugging process of the preset number of times of debugging, and obtaining a debugging preset length H _T and a debugging preset width corresponding to each debugging process W _T .

In other embodiments, the final number of times of debugging may also be determined during several times of debugging according to actual debugging results.

In this embodiment, the method for performing several debugging processes further includes: providing a preset change percentage, a preset change function, or a preset change amount. Moreover, the method for each debugging process also includes: changing the debugging preset length H _Tn-1 and debugging preset width W _Tn acquired for the n-1th time according to the preset change percentage, preset change function or preset change amount _-1 to form the debugging preset length H _Tn and the debugging preset width W _Tn acquired for the nth time, wherein, n is a natural number greater than or equal to 2.

Specifically, according to the preset change percentage, preset change function or preset change amount, the initial initial preset length H _X and initial preset width W _X are changed to form the first debugging preset length H _T1 and debugging preset Width W _T1 .

For example, the initial preset length H _X and the initial preset width W _X are multiplied by the preset change percentage respectively to form the first debugging preset length H _T1 and debugging preset width W _T1 for the first debugging deal with. On this basis, starting from the second debugging process, the debugging preset length H _Tn-1 and the debugging preset width W _Tn-1 acquired in the n-1th time are multiplied by the preset change percentage respectively to form the nth The debugging preset length H _Tn and the debugging preset width W _Tn acquired for the second time.

In this embodiment, according to the preset chip area S and the process node, the initial preset length _HX and the initial preset width _WX are debugged several times, so as to arrange mutually independent multiple chips in the preset wafer area 100. The method for a rectangular chip area includes: arranging a plurality of mutually independent rectangular chip areas in the preset wafer area 100 according to the one in which the number of debug chip areas 120 is the largest in several debugging processes, the chips The area has a preset debugging length H _T and a preset debugging width W _T corresponding to the debugging process. Thus, the typesetting of the chip area can be better optimized, the number of chips that can be manufactured on a wafer can be further increased, the waste of raw materials can be reduced, and the productivity and efficiency of semiconductor manufacturing can be improved.

Specifically, through each debugging process, the debugging results corresponding to this debugging process can be obtained: the number of debugging chip areas 120, the debugging preset length H _T and the debugging preset width W related to the layout of the debugging chip area 120 _T and other parameters. After obtaining the debugging results corresponding to several debugging processes, select a debugging process with the largest number of debugging chip areas 120, and use the layout method of the debugging chip area 120 corresponding to this debugging process as the layout method in the preset wafer area 100. The method of laying out the chip area. That is, the typesetting method of the debugging chip area 120 corresponding to this debugging process is used as the typesetting method of the chip area, and correspondingly, the debugging chip area 120 in this debugging process is used as the chip area.

In this embodiment, according to the preset chip area S and the process node, the initial preset length _HX and the initial preset width _WX are debugged several times, so as to arrange mutually independent multiple chips in the preset wafer area 100. The method for a rectangular chip area also includes: when the most and the same number of debug chip areas 120 are arranged for several times in several debugging processes, according to the first arrangement of the largest number of debug chip areas 120, in the preset A plurality of mutually independent rectangular chip areas are arranged in the wafer area 100 , and the chip areas have a debugging preset length H _Tn and a debugging preset width W _Tn corresponding to this debugging process.

In other embodiments, when the largest and the same number of debug chip areas are arranged multiple times in several debug processes, according to any one of them, a plurality of mutually independent rectangular chips are arranged in the preset wafer area area, the chip area has a debugging preset length H _Tn and a debugging preset width W _Tn corresponding to the debugging process.

It should be noted that, according to actual manufacturing requirements, chip regions of the same shape can be arranged in the entire preset wafer region 100 to manufacture the same chip on a wafer. Alternatively, in at least two non-overlapping areas of the predetermined wafer area 100, the debugging process may be performed separately and chip areas of different shapes may be arranged to manufacture at least two different types of chips on one wafer.

In this embodiment, the groove area 101 and the debug chip area 120 are independent from each other, and the wafer identification area 102 and the debug chip area 120 are independent from each other. Specifically, the debug chip area 120 is arranged in areas other than the groove area 101 and the wafer identification area 102 in the preset wafer area 100 . Correspondingly, the chip areas are arranged in areas other than the groove area 101 and the wafer identification area 102 in the predetermined wafer area 100 .

In this embodiment, the method for layout of the chip area further includes: performing the debugging process several times according to the width M of the scribe line. In each debugging process, the preset scribe width M exists between adjacent debug chip regions 120 , that is, there is also a scribe region between adjacent debug chip regions 120 . Correspondingly, there is the preset scribe width M between adjacent chip regions, that is, there is also a scribe region between adjacent chip regions.

By having the preset scribe lane width M between adjacent chip areas, that is, having a scribe lane area between adjacent chip areas, a space for a scribe lane (Scribe Lane) is reserved for manufacturing chips to cut The wafer forms a plurality of chips.

It should be understood that, during each debugging process, the shape of the dicing line region between adjacent debugging chip regions 120 changes as the size of the debugging chip region 120 changes.

In this embodiment, the method for layout of the chip area further includes: performing the debugging process several times according to the width W _E of the edge area. In each debugging process, the minimum distance between the edge of the debugging chip area 120 and the edge of the preset wafer area 100 is greater than or equal to the edge area width W _E . Correspondingly, the minimum distance between the edge of the chip area and the edge of the preset wafer area 100 is greater than or equal to the edge area width W _E .

Due to the greater risk of defects such as deformation occurring in the edge area of the wafer, the edge area is reduced by making the minimum distance between the edge of the chip area and the edge of the preset wafer area 100 greater than or equal to the edge area width W _E The impact of deformation and other defects on the chip improves the performance and reliability of the chip.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (9)

1. A method for typesetting a chip region, characterized in that it comprises: Provide preset wafer area, process node and preset chip area; Arranging a plurality of independent rectangular initial chip areas in the predetermined wafer area according to the predetermined chip area, the initial chip area has an initial predetermined length and an initial predetermined width; According to the preset chip area and process node, the initial preset length and the initial preset width are debugged several times, so as to arrange a plurality of mutually independent rectangular chip areas in the preset wafer area, and the chip area It has a preset chip area, and the number of the chip areas is greater than the number of the preset chip areas. 2. The method for layout of chip area according to claim 1, characterized in that, the number of times of the debugging process is more than 2 times; each time the method of the debugging process comprises: adjusting the initial chip area and the process node according to the preset The preset length and initial preset width are used to obtain the preset length for debugging and the preset width for debugging. It is assumed that a plurality of mutually independent rectangular debug chip areas are arranged in the wafer area, and the debug chip areas have a preset chip area. 3. The method for typesetting a chip area as claimed in claim 2, wherein the method for performing several debugging processes comprises: providing a preset number of times of debugging; performing the debugging process of the preset number of times of debugging, and obtaining the same number of times as each debugging process The corresponding debug preset length and debug preset width. 4. The method for typesetting a chip area as claimed in claim 2, characterized in that, the method for performing several debugging processes also includes: providing a preset change percentage, a preset change function or a preset change amount; The method also includes: according to the preset change percentage, preset change function or preset change amount, changing the debugging preset length and debugging preset width acquired in the n-1th time to form the debugging preset length and debugging width acquired in the nth time. Preset width, where n is a natural number greater than or equal to 2. 5. The method for typesetting a chip area as claimed in claim 2, characterized in that, according to the preset chip area and process node, the initial preset length and the initial preset width are debugged several times, so that in the preset wafer area The method for arranging a plurality of mutually independent rectangular chip areas includes: arranging a plurality of mutually independent rectangular chip areas in a preset wafer area according to the one with the largest number of debug chip areas arranged in several debugging processes area, the chip area has a debugging preset length and a debugging preset width corresponding to the debugging process. 6. The method for typesetting a chip area according to claim 5, characterized in that, according to the preset chip area and the process node, the initial preset length and the initial preset width are debugged several times, so that in the preset wafer area The method for arranging a plurality of mutually independent rectangular chip areas also includes: when the largest and the same number of debugging chip areas are arranged for several times in several debugging processes, according to the number of the largest number of debugging chip areas arranged for the first time Once, a plurality of mutually independent rectangular chip areas are arranged in the preset wafer area, and the chip areas have a debugging preset length and a debugging preset width corresponding to the debugging process. 7. The method for typesetting a chip region according to claim 1, further comprising: providing a preset scribe width; arranging the initial chip regions according to the preset scribe width, wherein adjacent initial There is the preset scribe width between the chip regions; the debugging process is performed several times according to the scribe width, wherein the preset scribe width exists between adjacent chip regions. 8. The method for typesetting a chip area according to claim 1, wherein the preset wafer area includes a groove area and a wafer identification area, the groove area is used for fixing the wafer, and the The groove area and the initial chip area are independent of each other, the groove area and the chip area are independent of each other, the wafer identification area is used to form marks to distinguish each wafer, and the wafer identification area and the initial chip area are independent of each other. The areas are independent of each other, and the wafer identification area and the chip area are independent of each other. 9. The method for typesetting a chip area according to claim 1, further comprising: providing the width of the edge area; The minimum distance between the edges of the circle area is greater than or equal to the width of the edge area; the debugging process is performed several times according to the width of the edge area, wherein the minimum distance between the edge of the chip area and the edge of the preset wafer area is greater than or equal to the margin area width.

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