CN115329935A - Pulse neural network accelerator - Google Patents

Abstract

The application discloses a pulse neural network accelerator.A controller drives a time step generator to generate a time step t after receiving input data; the pulse encoding unit encodes the input data into pulse data of the next time step t +1 based on the time step t; the scheduler decodes the pulse data and stores the decoded pulse data into the FIFO array; the controller reads a pulse source address from the FIFO array based on the current time step and sends the pulse source address to the neuron computing unit; the neuron computing unit reads corresponding neuron state data from the state memory according to the pulse source address so as to update the state of the neurons of the corresponding layer, writes the updated state data back to the state memory, and sends the output pulse data to the scheduler for storage, so that the neurons of the next layer can update the state, and the technical problem that the existing accelerator cannot determine whether unprocessed events remain at the current time in terms of hardware implementation and the performance of the accelerator is low is solved.

Description

A Spiking Neural Network Accelerator

technical field

The present application relates to the technical field of spiking neural network acceleration, in particular to a spiking neural network accelerator.

Background technique

Artificial intelligence technology and applications play an important role in daily life. Among them, the model based on spiking neural network shows extremely high accuracy and performance in the fields of classification, regression and target detection, and can more accurately simulate the human brain. The operating mechanism of the network, and as the number of network layers deepens, the consumption of system resources is less, which is conducive to promoting the development of artificial intelligence applications.

The existing hardware spiking neural network driving algorithms are generally event-driven, and it is impossible to determine whether the current time is an unprocessed event in hardware implementation, resulting in low performance of the accelerator.

Contents of the invention

The present application provides a spiking neural network accelerator, which is used to improve the technical problem that the existing accelerator cannot determine whether there are unprocessed events at the current time in terms of hardware implementation, resulting in low performance of the accelerator.

In view of this, the first aspect of the present application provides a spiking neural network accelerator method, including:

The controller is configured to drive the time step generator to generate a time step t after receiving the input data, and send the time step t and the input data to the pulse encoder unit;

The pulse encoding unit is configured to encode the input data into the pulse data of the next time step t+1 based on the time step t, and send the pulse data to the controller, and the controller converts the pulse sending data to the scheduler;

The scheduler is used to decode the pulse data to obtain the pulse source address and time step t+1, and store the pulse source address and time step t+1 in the FIFO array;

The controller is further configured to read the pulse source address from the FIFO array based on the current time step, and send the pulse source address to the neuron computing unit;

The neuron calculation unit is configured to read corresponding neuron state data from the state memory according to the pulse source address, update the state of the neurons of the corresponding layer according to the neuron state data, and update the updated state The data is written back into the state memory, and the output pulse data is sent to the scheduler for storage, so that the next layer of neurons can update the state.

Optionally, the pulse encoding unit includes: a pseudo-random number generator and a Poisson encoder;

The pseudo-random number generator is used to randomly generate a random number between 0 and 1 after receiving the time step;

The Poisson encoder is configured to perform Poisson encoding on the input data based on the random number to generate pulse data at the next time step t+1.

Optionally, the pulse encoding unit is further configured to trigger the time step generator to generate the next time step t+1 after encoding the input data of the next time step t+1.

Optionally, it also includes: a delay storage unit and a synaptic delay calculation unit;

The delay storage unit is used to store the synaptic delay time of the target neuron;

The synaptic delay calculation unit is configured to calculate a target time step according to the synaptic delay of the target neuron and the current time step, and send the target time step of the target neuron to the scheduler, and the scheduler The device stores according to the pulse source address of the target neuron and the target time step.

Optionally, the neuron computing unit is specifically used for:

When the neuron is an IF or LIF neuron, based on the four-stage pipeline, the corresponding neuron state data is read from the state memory according to the pulse source address, and the pulse neural network parameters are calculated according to the neuron state data. The network parameters update the neuron state, and write the updated neuron state back into the state memory;

When the neuron is an Izhikevich neuron, based on the six-stage pipeline, the corresponding neuron state data is read from the state memory according to the pulse source address, and the pulse neural network parameters are calculated according to the neuron state data, based on the pulse neural network parameters updating the neuron state, and writing the updated neuron state back into the state memory.

Optionally, when the neuron is a LIF neuron, the spiking neural network parameters include the membrane potential voltage of the LIF neuron calculated based on the first-order Euler method, and the calculation formula is:

β ₁ =α·V[n],

为采用一阶欧拉方法求得的膜电位电压，t_n为计算时的第n个离散时间步，v_n为输入膜电位大小，α为神经元膜电阻产生的电压受神经元此时膜电位的影响大小，f₁(t,v)为第一目标方程，f₂(t,v)为第二目标方程，β₁、β₂为不同阶段V的大小偏置，V_reset为神经元静息电位，h为时间步，τ_m为时间常数。In the formula, V[n] is the membrane state at the current moment, V[n+1] is the required membrane potential,

is the membrane potential voltage obtained by the first-order Euler method, t _n is the nth discrete time step in the calculation, v _n is the input membrane potential, α is the voltage generated by the neuron membrane resistance affected by the neuron membrane at this time The influence of potential, f ₁ (t,v) is the first objective equation, f ₂ (t,v) is the second objective equation, β ₁ and β ₂ are the biases of V in different stages, V _reset is the neuron Resting potential, h is the time step, τ _m is the time constant.

Optionally, when the neuron is an Izhikevich neuron, the pulse neural network parameters include the membrane potential voltage of the Izhikevich neuron calculated based on the first-order Euler method, and the calculation formula is:

V[n+1]=(0.04V ² +5V+140-U+I) h;

U[n+1]=[a(bV-U)] h;

In the formula, V is the required membrane potential voltage, U is the membrane potential recovery variable, I is the input current of the neuron, h is the time step, a, b, c, d are the model parameters of the neuron, and V _threshold is the membrane voltage threshold.

Optionally, the state memory includes a weight memory for storing weights of neurons and a neuron parameter storage unit for storing neuron parameters.

Optionally, the FIFO arrays in the scheduler are 16 parallel FIFO arrays.

As can be seen from the above technical solutions, the present application has the following advantages:

The application provides a spiking neural network accelerator, including: a spiking unit, a controller, a time step generator, a scheduler, a state memory, and a neuron computing unit; the controller is used to drive the time step after receiving input data The generator generates a time step t, and sends the time step t and input data to the pulse encoder unit; the pulse encoding unit is used to encode the input data into the pulse data of the next time step t+1 based on the time step t, and sends The pulse data is sent to the controller, and the controller sends the pulse data to the scheduler; the scheduler is used to decode the pulse data to obtain the pulse source address and time step t+1, and the pulse source address and time step t+1 Stored in the FIFO array; the controller is also used to read the pulse source address from the FIFO array based on the current time step, and send the pulse source address to the neuron computing unit; the neuron computing unit is used for according to the pulse source address Read the corresponding neuron state data from the state memory, update the state of the neurons in the corresponding layer according to the neuron state data, write the updated state data back to the state memory, and send the output pulse data to the scheduler Stored so that the next layer of neurons can update the state.

In this application, the time step using pulse encoding is delayed by one time step than the time step generated by the time step generator, so that when the neuron calculation unit calculates the input pulse at time t, the pulse encoding unit encodes the pulse at time t+1, Thus, the neuron calculation unit can directly obtain the pulse to be calculated at time t without waiting for encoding, which improves the calculation efficiency, and can determine whether the calculation of the pulse at the current time is completed through the time step, thereby improving the existing accelerator. Hardware implementation cannot determine whether there are unprocessed events left at the current time, resulting in a technical problem of low performance of the accelerator.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present application. Those skilled in the art can also obtain other drawings based on these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of a spiking neural network accelerator provided in an embodiment of the present application;

Fig. 2 is a schematic structural diagram of a pseudo-random number generator provided by the embodiment of the present application;

FIG. 3 is a schematic structural diagram of a spiking neural network accelerator provided in an embodiment of the present application;

FIG. 4 is a schematic diagram of the calculation method of the LIF neuron pipeline provided by the embodiment of the present application;

Fig. 5 is a schematic diagram of the Izhikevich neuron neuron pipeline calculation method provided by the embodiment of the present application;

FIG. 6 is a schematic diagram of parallel buffering and forwarding provided by an embodiment of the present application.

Detailed ways

In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiment of the application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the application. Obviously, the described embodiment is only It is a part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

For ease of understanding, please refer to FIG. 1. The embodiment of the present application provides a pulse neural network accelerator, including: a pulse encoding unit, a controller, a time step generator, a scheduler, a state memory, and a neuron computing unit;

A controller is used to drive the time step generator to generate a time step t after receiving the input data, and send the time step t and the input data to the pulse encoder unit;

a pulse encoding unit, configured to encode the input data into pulse data of the next time step t+1 based on the time step t, and send the pulse data to the controller, and the controller sends the pulse data to the scheduler;

The scheduler is used to decode the pulse data to obtain the pulse source address and time step t+1, and store the pulse source address and time step t+1 in the FIFO array;

The controller is also used to read the pulse source address from the FIFO array based on the current time step, and send the pulse source address to the neuron computing unit;

The neuron computing unit is used to read the corresponding neuron state data from the state memory according to the pulse source address, update the state of the neurons of the corresponding layer according to the neuron state data, and write the updated state data back into the state memory , and send the output pulse data to the scheduler for storage, so that the next layer of neurons can update the state.

The core module of the spiking neural network accelerator in this application is the controller. After receiving the input data, the controller drives the time step generator to run to generate the time step t, and then sends the time step t and the input data to the pulse encoding unit. After receiving the time step t and the input data, the pulse encoding unit adds one to the time step t, encodes the input data into pulse data, obtains the pulse data of the next time step t+1, and sends the pulse data to the control The controller sends the pulse data to the scheduler; the pulse encoding unit is also used to trigger the time step generator to generate the next time step t+1 after encoding the input data of the next time step t+1.

Further, in order to solve the problem of converting input data into pulse data, the embodiment of the present application designs a Poisson encoder based on pseudo-random numbers. The pulse encoding unit in the embodiment of the present application includes: a pseudo-random number generator and a Poisson encoder;

A pseudo-random number generator, used to randomly generate a random number between 0 and 1 after receiving time step t;

Poisson encoder, which is used to Poisson encode the input data based on random numbers to generate the pulse data of the next time step t+1.

Please refer to FIG. 2, the embodiment of the present application uses a 12bit linear feedback shift register (LSFR) to generate a random number rand between 0 and 1, and the encoding formula of the Poisson encoder is:

if rand<c×I _ijk , then spike;

In the formula, c is a control parameter, which is used to control the maximum pulse emission frequency, preferably setting c=1, that is, the maximum emission pulse frequency is 1Khz, I _ijk is input data, and the input data can be normalized data, according to the above It can be seen from the formula that when c=1, as long as the generated random number is smaller than the input data, a pulse will be generated.

The controller receives the pulse data sent by the pulse encoding unit through the AER bus and forwards it to the scheduler. The scheduler decodes the pulse data to obtain the pulse source address and time step, and stores the pulse source address and time step in the FIFO array.

Further, the spiking neural network accelerator in the embodiment of the present application also includes: a delay storage unit and a synaptic delay calculation unit;

The delay storage unit is used to store the synaptic delay time of the target neuron; the delay storage unit stores the delay required for each post-synaptic neuron to send a pulse, and the delay will only act on the scheduler when a pulse is generated ;

The synaptic delay calculation unit is used to calculate the target time step according to the synaptic delay of the target neuron and the current time step, and send the target time step of the target neuron to the scheduler, and the scheduler uses the pulse source address of the target neuron and The target time step is stored.

The FIFO array in the scheduler is 16 parallel FIFO arrays, as shown in Figure 3, which can realize 16 different synaptic delays, and 16 parallel FIFO arrays form a ring array to realize the pulse source under different time steps address read.

After the pulse coding unit finishes encoding the input data, the controller reads the pulse source address from the FIFO array based on the current time step, and sends the pulse source address to the neuron computing unit, and the neuron computing unit Read the corresponding neuron state data from the state memory, update the state of the neurons of the corresponding layer according to the neuron state data, write the updated state data back to the state memory, and send the generated pulse data to the scheduler Stored so that the next layer of neurons can update the state. After the current time step completes the corresponding neuron state update, the output pulse data is stored in the scheduler, so as to update the state of the next layer of neurons.

When the accelerator in the embodiment of the present application completes the encoding of the input picture data and the processing of the pulse event corresponding to the neuron time unit (that is, the pulse event to be processed under the current neuron unit, one of the pulse events represents the need to update the corresponding After the membrane potentials of all neurons in the neural network layer, N means updating N times), the update of the neuron time unit can be completed, and the neuron state update of the next time unit can be started. Using an accelerator designed with Poisson encoder, time step and ring FIFO, 16 parallel FIFO arrays form a ring array to realize the reading of pulse source addresses at different time steps. The accelerator can not only complete the pulse of external data Coding can also reduce the waiting time for neuron state updates, effectively improving the speed at which hardware performs spiking neural network calculations.

Further, the neuron computing unit is specifically used for:

When the neuron is an IF or LIF neuron, based on the four-stage pipeline, the corresponding neuron state data is read from the state memory according to the pulse source address, the pulse neural network parameters are calculated according to the neuron state data, and the neural network parameters are updated based on the pulse neural network parameters. neuron state, and write the updated neuron state back into the state memory;

When the neuron is an Izhikevich neuron, read the corresponding neuron state data from the state memory according to the pulse source address based on the six-stage pipeline, calculate the pulse neural network parameters according to the neuron state data, and update the neuron state based on the pulse neural network parameters , and write the updated neuron state back into the state memory.

In this application, the state memory includes a weight memory for storing weights of neurons and a neuron parameter storage unit for storing neuron parameters. The neuron calculation unit reads the weight and neuron parameters from the state memory according to the pulse source address, and updates the neuron state according to the weight and neuron parameters, that is, updates the neuron membrane potential, and needs to rewrite the updated neuron state Back to state memory. In this embodiment of the present application, the update of the state of the neuron is realized by using parallel and pipeline technology. 16 neuron computing units working in parallel are used, so 16 neuron states can be updated at the same time. For IF neurons/LIF neurons with relatively simple calculations, as shown in Figure 4, the update method is a four-stage pipeline. When each neuron is updated, it is divided into reading (R), model parameter calculation (O), neuron state calculation (C) and write back (W). The calculated model parameters include LIF calculated based on the first-order Euler method Membrane potential voltage and refractory period update value of neuron, neuron state calculation includes membrane potential update and refractory period update. As for the Izhikevich neurons with complex calculations, as shown in Figure 5, the update method is a six-stage pipeline, including reading (R), model parameter calculation and neuron state calculation (A, B, C and D) and Write back (W). The use of pipeline technology to accelerate calculation changes the combination logic of the calculation part in the traditional read-write separation method to pipeline processing, which can not only increase the working clock frequency of the system circuit, but also improve the simplicity of circuit debugging.

When the neuron is a LIF neuron, the spiking neural network parameters include the membrane potential voltage of the LIF neuron calculated based on the first-order Euler method. LIF neurons simulate the membrane voltage leakage of biological neurons in an exponential process, as shown in the following formula:

In the formula, V _m is the current membrane potential voltage of the neuron, V _m+1 is the membrane potential voltage after leakage, Δt is the time difference of leakage, and τ _m is the time constant. When presynaptic neuron i generates an output spike, the synaptic weights are updated to the membrane potential of postsynaptic neuron j after a set propagation delay. According to the above calculation formula, it can be seen that there is an exponential operation in the calculation of LIF neurons, and the first-order Euler method is used to eliminate the exponential calculation of the solution, and the arithmetic shift is used to replace the multiplication calculation. The optimized calculation formula is:

β ₁ =α·V[n],

为采用一阶欧拉方法求得的膜电位电压，t_n为计算时的第n个离散时间步，v_n为输入膜电位大小，α为神经元膜电阻产生的电压受神经元此时膜电位的影响大小，f₁(t,v)为第一目标方程，f₂(t,v)为第二目标方程，β₁、β₂为不同阶段V的大小偏置，V_reset为神经元静息电位，h为时间步，τ_m为时间常数。In the formula, V[n] is the membrane state at the current moment, V[n+1] is the required membrane potential,

is the membrane potential voltage obtained by the first-order Euler method, t _n is the nth discrete time step in the calculation, v _n is the input membrane potential, α is the voltage generated by the neuron membrane resistance affected by the neuron membrane at this time The influence of potential, f ₁ (t,v) is the first objective equation, f ₂ (t,v) is the second objective equation, β ₁ and β ₂ are the biases of V in different stages, V _reset is the neuron Resting potential, h is the time step, τ _m is the time constant.

设置为0.125，简化后的计算公式为：Fix some of the above parameters, where V _reset is set to 0, α is set to 0.5,

Set to 0.125, the simplified calculation formula is:

V[n+1]=V[n]-(y ₁ +y ₂ );

y ₁ =(V[n]-β ₁ )>>4;

In the formula, >>4 is a logical left shift of 4 bits, >>3 is a logical left shift of 3 bits, and y ₁ and y ₂ are intermediate parameters.

When the neuron is an Izhikevich neuron, the spiking neural network parameters include the membrane potential voltage of the Izhikevich neuron calculated based on the first-order Euler method. Compared with LIF neurons, Izhikevich neurons have higher biological authenticity, so the computational complexity will increase accordingly. The calculation formula is as follows:

if V＞V _threshold , Spike and V=c, U=U+d;

In the formula, V is the membrane voltage, U is the membrane potential recovery variable, I is the input current of the neuron, a, b, c, d are the model parameters of the neuron, and V _threshold is the membrane voltage threshold;

For Izhikevich neurons, the optimization process is similar to the process of optimizing LIF neurons. The first-order Euler method is used to realize the dV/dt and dU/dt in the formula. Although there are still multiplication calculations in Izhikevich neurons after optimization, they are extremely The index calculation is greatly reduced, and the calculation formula of the optimized Izhikevich neuron is:

V[n+1]=(0.04V ² +5V+140-U+I) h;

U[n+1]=[a(bV-U)] h;

In the embodiment of the present application, a is set to 6, b is set to 2, c is set to 1.0, and d is set to 0.01.

The first-order Euler method is used to eliminate the differential calculation of the LIF/IZH neuron solution, which reduces the complexity of the solution and makes it hardware-friendly. Using the first-order Euler method to eliminate the optimized neurons obtained by the differential calculation of LIF neurons and Izhikevich neurons, optimize the calculation process of LIF neurons and Izhikevich neurons, reduce the computational complexity, and make the neuron calculation The unit updates the neuron membrane potential faster, takes up less hardware resources, and can support the spiking neural network of different spiking neurons, which improves the existing technology that has a single neuron model and cannot support the construction of multiple different spiking neurons. The SNN, and the hardware resources occupied by the computing unit, the amount of calculation and the power consumption are very large technical problems.

When the pulse data received by the scheduler is an internal pulse, that is, the pulse data output by the neuron after the state update, the neuron computing unit sends the updated pulse data to the scheduler for storage, and uses 16 FIFO arrays to send pulses The address of the FIFO is cached, and the empty signal of the FIFO is combined and passed to the arbitrator, as shown in Figure 6. The arbitrator will take out the neuron address of the pulse neuron from the FIFO according to the set priority. The main advantages of this processing are: ① There is no need to suspend the pipeline of the above calculation, which improves the calculation efficiency. ② It can flexibly complete the buffering of sixteen parallel pulses and record the pulse source address, and complete the update of the next layer of neurons without address conversion, shortening the conversion time.

The embodiment of the present application uses two data sets (MNIST and Fashion-MNIST) to verify the spiking neural network accelerator, both of which prove that the accelerator in the embodiment of the present application has better acceleration performance.

In the embodiment of the present application, the time step using pulse encoding is delayed by one time step than the time step generated by the time step generator, so that when the neuron calculation unit calculates the input pulse at time t, the pulse encoding unit encodes the time step at time t+1 Pulse, so that the neuron calculation unit can directly obtain the pulse to be calculated at time t without waiting for encoding, which improves the calculation efficiency, and can determine whether the calculation of the pulse at the current time is completed through the time step, thereby improving the existing The hardware implementation of the accelerator cannot determine whether there are unprocessed events left at the current time, resulting in a technical problem of low performance of the accelerator. In addition, the parallel and configurable variable-length pipeline architecture is used to update the membrane potential of IF, LIF and IZH neurons, and the time-division multiplexing technology is used to effectively improve the scale of the accelerator and the efficiency of data processing.

The terms "first", "second", "third", "fourth", etc. (if any) in the description of the present application and the above drawings are used to distinguish similar objects and not necessarily to describe specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein, for example, can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or device comprising a sequence of steps or elements is not necessarily limited to the expressly listed instead, may include other steps or elements not explicitly listed or inherent to the process, method, product or apparatus.

It should be understood that in this application, "at least one (item)" means one or more, and "multiple" means two or more. "And/or" is used to describe the association relationship of associated objects, indicating that there can be three types of relationships, for example, "A and/or B" can mean: only A exists, only B exists, and A and B exist at the same time , where A and B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one item (piece) of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c ", where a, b, c can be single or multiple.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

If the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions for executing all or part of the steps of the methods described in the various embodiments of the present application through a computer device (which may be a personal computer, a server, or a network device, etc.). The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (English full name: Read-OnlyMemory, English abbreviation: ROM), random access memory (English full name: Random Access Memory, English abbreviation: RAM), disk Or various media such as CDs that can store program codes.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still understand the foregoing The technical solutions described in each embodiment are modified, or some of the technical features are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the application.

Claims (9)

1. A pulse neural network accelerator, is characterized in that, comprises: pulse encoding unit, controller, time step generator, scheduler, state memory and neuron computing unit; The controller is configured to drive the time step generator to generate a time step t after receiving the input data, and send the time step t and the input data to the pulse encoder unit; The pulse encoding unit is configured to encode the input data into the pulse data of the next time step t+1 based on the time step t, and send the pulse data to the controller, and the controller converts the pulse sending data to the scheduler; The scheduler is used to decode the pulse data to obtain the pulse source address and time step t+1, and store the pulse source address and time step t+1 in the FIFO array; The controller is further configured to read the pulse source address from the FIFO array based on the current time step, and send the pulse source address to the neuron computing unit; The neuron calculation unit is configured to read corresponding neuron state data from the state memory according to the pulse source address, update the state of the neurons of the corresponding layer according to the neuron state data, and update the updated state The data is written back into the state memory, and the output pulse data is sent to the scheduler for storage, so that the next layer of neurons can update the state. 2. The pulse neural network accelerator according to claim 1, wherein the pulse encoding unit comprises: a pseudo-random number generator and a Poisson encoder; The pseudo-random number generator is used to randomly generate a random number between 0 and 1 after receiving the time step t; The Poisson encoder is configured to perform Poisson encoding on the input data based on the random number to generate pulse data at the next time step t+1. 3. The pulse neural network accelerator according to claim 1, wherein the pulse encoding unit is further configured to trigger the time step generator to generate Next time step t+1. 4. The spiking neural network accelerator according to claim 1, further comprising: a delay storage unit and a synaptic delay calculation unit; The delay storage unit is used to store the synaptic delay time of the target neuron; The synaptic delay calculation unit is configured to calculate a target time step according to the synaptic delay of the target neuron and the current time step, and send the target time step of the target neuron to the scheduler, and the scheduler The device stores according to the pulse source address of the target neuron and the target time step. 5. The pulse neural network accelerator according to claim 1, wherein the neuron computing unit is specifically used for: When the neuron is an IF or LIF neuron, based on the four-stage pipeline, the corresponding neuron state data is read from the state memory according to the pulse source address, and the pulse neural network parameters are calculated according to the neuron state data. The network parameters update the neuron state, and write the updated neuron state back into the state memory; When the neuron is an Izhikevich neuron, based on the six-stage pipeline, the corresponding neuron state data is read from the state memory according to the pulse source address, and the pulse neural network parameters are calculated according to the neuron state data, based on the pulse neural network parameters updating the neuron state, and writing the updated neuron state back into the state memory. 6. The spiking neural network accelerator according to claim 5, wherein when the neuron is a LIF neuron, the spiking neural network parameters include the membrane potential voltage of the LIF neuron calculated based on the first-order Euler method, The calculation formula is:

β ₁ =α·V[n],

In the formula, V[n] is the membrane state at the current moment, V[n+1] is the required membrane potential,

is the membrane potential voltage obtained by the first-order Euler method, t _n is the nth discrete time step in the calculation, v _n is the input membrane potential, α is the voltage generated by the neuron membrane resistance affected by the neuron membrane at this time The influence of potential, f ₁ (t,v) is the first objective equation, f ₂ (t,v) is the second objective equation, β ₁ and β ₂ are the biases of V in different stages, V _reset is the neuron Resting potential, h is the time step, τ _m is the time constant. 7. spiking neural network accelerator according to claim 5, is characterized in that, when neuron is Izhikevich neuron, described spiking neural network parameter comprises the membrane potential voltage of Izhikevich neuron calculated based on first-order Euler method, The calculation formula is: V[n+1]=(0.04V ² +5V+140-U+I) h; U[n+1]=[a(bV-U)] h; In the formula, V is the required membrane potential voltage, U is the membrane potential recovery variable, I is the input current of the neuron, h is the time step, a, b, c, d are the model parameters of the neuron, and V _threshold is the membrane voltage threshold. 8. The spiking neural network accelerator according to claim 1 or 5, wherein the state memory comprises a weight memory for storing weights of neurons and a neuron parameter storage unit for storing neuron parameters. 9. The spiking neural network accelerator according to claim 1, wherein the FIFO array in the scheduler is 16 parallel FIFO arrays.

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