CN115313864B - Logic control circuit applied to DC-DC converter mode switching - Google Patents

Abstract

The present invention claims protection for a logic control circuit used in a DC-DC converter mode switching. The circuit mainly includes a logic control circuit, a modulation signal selection circuit, a buck core circuit, and a pulse width modulation loop. Since the output of the error amplifier will change significantly when the DC-DC mode is switched, the mode switching is achieved by comparing V _EA with V ₁ to generate a mode selection signal CHOOSE. However, the output of the error amplifier is easily affected by the noise of the circuit, so the mode selection signal CHOOSE may be unstable. In order to solve these problems, some logic controls can be used to improve this situation. The logic control circuit of the present invention is as follows. V _EA is compared with V ₁ to generate Q ₀ , Q ₁ , Q ₂ signals. When Q ₀ , Q ₁ , Q ₂ = 111, the mode selection signal CHOOSE = 1, or when Q ₀ , Q ₁ , Q ₂ = 000, the mode selection signal CHOOSE = 0, and the mode switching will be performed. When Q ₀ , Q ₁ , Q ₂ is in other states (001-110), the mode selection signal CHOOSE signal maintains the state of the previous moment.

Description

A logic control circuit used in DC-DC converter mode switching

Technical Field

The invention belongs to the technical field of analog integrated circuit design, and in particular relates to a logic control circuit used in mode switching of a DC-DC converter.

Background technique

With the development of modern science and technology, the large-scale development and use of portable electronic products and consumer electronic products have put forward higher and higher requirements for power management chips. How to meet the growing demands has become a new challenge for power management IC designers. Traditional power management chips mainly include low-voltage dropout linear regulators and DC-DC converters. Linear regulators are a type of regulator that maintains a low voltage drop between input and output. They do not require external inductors, have simple peripheral circuits, and have relatively small ripples. Compared with linear regulators, although the peripheral devices of switching power supplies are more complex and the ripple is larger, their excellent conversion efficiency makes them still the mainstream design method of power management chips today. They have been widely used in occasions with high efficiency requirements. Higher conversion efficiency has become the main trend and core indicator of today's switching power supply chip research.

The common point of synchronous rectification switching power converters is that the freewheeling switch tube is used to replace the freewheeling diode to reduce power loss and improve conversion efficiency. When the switching power converter is under heavy load, it is in the inductor current continuous mode (CCM). When the load is light, the duty cycle decreases, the inductor current decreases, and it is in the inductor current discontinuous mode (DCM). When the load is heavy, the DC-DC is modulated using the PWM (pulse width modulation) mode. At the same time, in order to provide a large current and reduce the on-resistance of the power tube, the gate width should be larger. When the load is light, PSM/PFM modulation is often used to improve the efficiency of the DC-DC, while reducing the gate width of the power tube. If the selection of the switching point is not very reliable, the DC-DC circuit will constantly change between light load and heavy load, greatly reducing the efficiency and increasing the power consumption of the chip. Therefore, a correct switching signal is very important.

Patent CN111740569A is a floating gate width switching circuit used in a DC-DC converter. The pulse width modulation loop is used to generate a PWM (pulse width modulation) signal with a constant duty cycle that changes with the output load. The gate width determination circuit changes the level logic of the three pairs of drive signals QP and QN, QP1 and QN1, and QP2 and QN2 according to the load conditions to change the switch state of the three pairs of power MOS tubes in the buck core module. The level logic of the three pairs of drive signals QP and QN, QP1 and QN1, and QP2 and QN2 is directly generated by the output of the error amplifier in the pulse width modulation loop and two reference voltages. When the comparator state changes, the state of the entire circuit will also change immediately, but the output voltage of the error amplifier is easily disturbed when the mode is switched, resulting in the state of the three pairs of drive signals QP and QN, QP1 and QN1, and QP2 and QN2 changing back and forth, affecting the working state of the circuit. The logic control circuit of the present invention generates _Q0 , _Q1 , and _Q2 signals by comparing _VEA with _V1 . The mode switching is performed only when the mode selection signal CHOOSE=1 when _Q0 , _Q1 , and _Q2 =111, or when the mode selection signal CHOOSE=0 when _Q0 , _Q1 , and _Q2 =000. When _Q0 , _Q1 , and _Q2 are in other states (001-110), the mode selection signal CHOOSE keeps the state of the previous moment. It can be seen that the logic control circuit of the present invention needs at least three clock cycles to perform a mode switching, which can make the mode switching process more stable and is conducive to generating a very accurate mode switching signal CHOOSE.

Summary of the invention

The present invention aims to solve the above problems of the prior art. A logic control circuit applied to the mode switching of a DC-DC converter is proposed. The technical solution of the present invention is as follows:

A logic control circuit used in DC-DC converter mode switching, comprising: a logic control circuit, a buck core circuit, a modulation signal selection circuit and a pulse width modulation loop, wherein:

The pulse width modulation loop is used to generate a PWM pulse width modulation signal with a constant period and a duty cycle that changes with the output load;

The logic control circuit is used to generate a correct mode selection signal CHOOSE according to the load condition, specifically including:

The logic control circuit compares the output voltage V _EA of the operational amplifier EA in the pulse width modulation loop with V ₁ , where V ₁ represents the reference voltage, to generate the output signals Q ₀ , Q ₁ and Q ₂ of the D flip-flop. When Q ₀ , Q ₁ , Q ₂ = 111, the mode selection signal CHOOSE = 1, or when Q ₀ , Q ₁ , Q ₂ = 000, the mode selection signal CHOOSE = 0, and the mode switching is performed. When Q ₀ , Q ₁ , Q ₂ are in other states (001 to 110), the mode selection signal CHOOSE maintains the state of the previous moment.

The modulation signal selection circuit is composed of a NOT gate, two OR gates, an AND gate and a dead time control, and is used to determine the modulation mode of the DC-DC circuit through the mode selection signal CHOOSE;

The buck core circuit consists of two pairs of power MOS tubes, a NOT gate, a two-input AND gate, and a two-input OR gate. The mode selection signal CHOOSE is used to select the appropriate gate width to provide energy to the load.

Further, the logic control circuit is composed of three D flip-flops, a 4-to-1 data selector, a three-input NOR gate, and a three-input AND gate; the input signal of the three-input NOR gate comes from the output signals Q ₀ , Q ₁ , Q ₂ of the three D flip-flops, and the output signal is the control signal A ₀ of the 4-to-1 data selector; the input signal of the three-input AND gate also comes from the output signals Q ₀ , Q ₁ , Q ₂ of the three D flip-flops, and the output signal is the control signal A ₁ of the 4-to-1 data selector; the negative terminal of the comparator COMP is connected to the output voltage V _EA of the error amplifier EA in the pulse width modulation loop, and the positive terminal is connected to the reference voltage V ₁ ; the CLK signals of the three D flip-flops DFF are connected to the drive signal VH of the switch tube M1 in the buck core circuit; the three D flip-flops DFF are triggered by the rising edge of the drive signal VH to store the output voltage of the comparator COMP; the two input terminals D ₀ and D ₃ of the data selector are connected to the mode selection signal CHOOSE, the input terminal D ₁ is connected to GND, and the input terminal D ₂ Connect to VDD.

Furthermore, control signals _A1 and _A0 are generated by the states of outputs _Q0 , _Q1 , _Q2 of three D flip-flops. When the circuit changes from light load to heavy load, _VEA < _V1 , the output of the comparator is 1. When the first rising edge of the drive signal VH arrives, _Q0 , _Q1 , _Q2 = 100, _A1 , _A0 = 00, and the mode selection signal CHOOSE remains unchanged. When the second rising edge of the drive signal VH arrives, _Q0 , _Q1 , _Q2 = 110, _A1 , _A0 = 00, and the mode selection signal CHOOSE remains unchanged. When the third rising edge of the drive signal VH arrives, _Q0 , _Q1 , _Q2 = 111, _A1 , _A0 = 10, and the mode selection signal CHOOSE = 1 (VDD), the circuit will enter the PWM pulse width modulation mode, and _Q0 , _Q1 , _Q2 =001~110, the logic control circuit pushes out that the mode selection signal CHOOSE=1(VDD), and the modulation mode of the circuit will not change; when the circuit is in a light load condition, V _EA >V ₁ , the output of the comparator is 0, when the first rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ =011, A ₁ , A ₀ =00, the mode selection signal CHOOSE remains unchanged, when the second rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ =001, A ₁ , A ₀ =00, the mode selection signal CHOOSE remains unchanged, when the third rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ =000, A ₁ , A ₀ =01, the mode selection signal CHOOSE=0(GND), at this time the mode selection signal CHOOSE=0, the circuit enters PSM (pulse skipping cycle) modulation, at this time Q ₀ , Q _1. When Q ₂ = 001-110, it can be deduced from the logic control circuit that the mode selection signal CHOOSE = 0, and the modulation mode of the circuit will not change.

Furthermore, the pulse width modulation loop includes an error amplifier EA, a comparator COMP, an RS trigger, and a triangular wave generator V _RAMP . The triangular wave generator V _RAMP is used to generate a triangular wave and a clock signal V _CLK with a fixed period. The positive terminal of the error amplifier is connected to the feedback voltage VOUT fed back from the output end of the DC-DC converter, and the negative terminal is connected to the reference voltage V _REF . The positive terminal of the comparator COMP is connected to the V _RAMP signal, and the negative terminal is connected to the error amplifier output V _EA . After rectification by the RS trigger, the output signal is a PWM pulse width modulation signal with a constant period and a duty cycle that changes according to the load.

Furthermore, the step-down core circuit is composed of two pairs of large-size power MOS tubes M1 and M3, M2 and M4, an inverter, two two-input OR gates, and a two-input AND gate; the gates of M1 and M3 are respectively connected to drive signals VH and VL (VH and VL are a pair of modulation signals to drive MOS tubes M1 and M3 respectively), and the gates of M2 and M4 are respectively connected to drive signals VH1 and VL1 (VH1 and VL1 are a pair of modulation signals to drive MOS tubes M2 and M4 respectively); the input signal of the inverter comes from the mode selection signal CHOOSE, the input signal of the two-input OR gate is the output signal of the inverter and the drive signal VH of the power MOS tube M1, and the output signal is the drive signal VH1 of the power MOS tube M2; the input signal of the two-input AND gate is the mode selection signal CHOOSE and the drive signal VL of the power MOS tube M3, and the output signal is the drive signal VL1 of the power MOS tube M4.

Furthermore, when the buck core circuit is in a heavy load condition, the mode selection signal CHOOSE=1, the drive signal VH=VHI, VL=VL1, and both pairs of power MOS are turned on to provide energy for the load. When the circuit is in a light load condition, the mode selection signal CHOOSE=0, the drive signal VHI=1, the drive signal VL1=0, and the power MOS tubes M1 and M3 are turned on to provide energy for the load.

Furthermore, the modulation signal selection circuit is composed of two two-input OR gates, a two-input AND gate, an inverter, and a dead time control module. The input signal of the NOT gate comes from the mode selection signal CHOOSE, and the output signal is connected to the input end of the two-input OR gate OR2. The input of the two-input OR gate OR1 comes from the pulse width modulation PWM and the mode selection signal CHOOSE, and the output signal is connected to the input end of the AND gate. The input of the two-input OR gate OR2 comes from the pulse skipping modulation PSM and the output signal of the NOT gate, and the output signal is connected to the input end of the AND gate. The two-input AND gate inputs the output signals from the two OR gates, and the input signal of the dead time control module comes from the two-input AND gate, and the output is a non-overlapping control signal VH and VL.

Furthermore, in the modulation signal selection circuit, when the mode selection signal CHOOSE=1, the drive signal VH=PWM (pulse width modulation), PWM pulse width modulation is used, and both pairs of power MOS in the buck core circuit are turned on to provide energy for the load; when the mode selection signal CHOOSE=0, VH=PSM (pulse skipping cycle), PSM pulse skipping cycle modulation is used, and power MOS tubes M1 and M3 are turned on to provide energy for the load.

Furthermore, the inverter is composed of a PMOS device and an NMOS device, wherein the source of the PMOS device is connected to the power supply voltage, the drain is connected to the drain of the NMOS device, the gate is connected to the gate of the NMOS device, and the source of the NMOS device is grounded, and its main function is to reverse the input signal. The dead time control module is composed of two NOR gates and 9 NOT gates. The input signal comes from the output of the AND gate in the modulation signal selection circuit, and the output signal is a pair of non-overlapping drive signals VH and VL. Its main function is to avoid the large-size power MOS tubes in the buck core circuit from being turned on at the same time, directly grounding the power supply voltage, generating a large current, and causing damage to the circuit.

The advantages and beneficial effects of the present invention are as follows:

1. In order to provide a precise mode switching signal for the DC-DC converter, the present invention registers the output voltage of the comparator through three D flip-flops, and uses an adaptive VH signal as the CLK signal of the D flip-flop, and proposes a logic control circuit for mode switching of the DC-DC converter. When the circuit changes from light load to heavy load, the drive signal VH=PSM (pulse skipping period), V _EA <V ₁ , the output of the comparator is 1, when the first rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ =100, when the second rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ =110, when the third rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ =111, at this time the mode selection signal CHOOSE=1, the circuit enters the PWM (pulse width modulation) mode, and the drive signal VH=PWM (pulse width modulation). Similarly, when the circuit changes from heavy load to light load, the drive signal VH = PWM (pulse width modulation), V _EA > V ₁ , after 3 clock cycles, the mode selection signal CHOOSE = 0, the circuit enters PSM (pulse skipping cycle) modulation, and the drive signal VH = PSM (pulse skipping cycle). It can be seen that the frequency of the DFF clock signal VH changes when the circuit is in different states, because the power consumption of the digital circuit is proportional to the frequency, using the adaptive VH signal as the CLK signal of the D flip-flop can reduce power consumption.

2. The logic control circuit for mode switching of a DC-DC converter proposed by the present invention has the advantage of improving the anti-interference ability of the mode selection signal CHOOSE. When the mode selection signal CHOOSE=1, if Q ₀ , Q ₁ , Q ₂ = 001-110, it can be deduced by the logic control circuit that the mode selection signal CHOOSE=1, and the modulation mode of the circuit will not change. When the mode selection signal CHOOSE=0, if Q ₀ , Q ₁ , Q ₂ = 001-110, it can be deduced by the logic control circuit that the mode selection signal CHOOSE=0, and the modulation mode of the circuit will not change. In this way, it can avoid the generation of an erroneous mode selection signal CHOOSE due to external interference, causing the entire circuit to switch back and forth between PWM/PSM modes, affecting the efficiency of the circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a mode switching signal circuit of a conventional DC-DC converter according to a preferred embodiment of the present invention.

FIG. 2 is a mode switching logic control circuit of a DC-DC converter of the present invention.

FIG. 3 shows a specific structure of a mode switching logic control circuit of a DC-DC converter of the present invention.

FIG4 is a transient simulation diagram of the adaptive clock signal VH.

FIG5 is a transient simulation diagram of the mode selection signal CHOOSE.

Figure 6: Transient simulation diagram of anti-interference capability.

Detailed ways

The following will describe the technical solutions in the embodiments of the present invention in detail in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention.

The technical solution of the present invention to solve the above technical problems is:

A logic control circuit for switching the modes of a DC-DC converter mainly includes a logic control circuit, a voltage reduction core circuit, a modulation signal selection circuit, and a pulse width modulation loop.

The pulse width modulation loop is used to generate a PWM pulse width modulation signal with a constant period and a duty cycle that changes with the output load;

The logic control circuit is used to generate a correct mode selection signal CHOOSE according to the load condition, specifically including:

The logic control circuit compares the output voltage V _EA of the operational amplifier EA in the pulse width modulation loop with V ₁ , where V ₁ represents the reference voltage, to generate the output signals Q ₀ , Q ₁ and Q ₂ of the D flip-flop. When Q ₀ , Q ₁ , Q ₂ = 111, the mode selection signal CHOOSE = 1, or when Q ₀ , Q ₁ , Q ₂ = 000, the mode selection signal CHOOSE = 0, and the mode switching is performed. When Q ₀ , Q ₁ , Q ₂ are in other states (001 to 110), the mode selection signal CHOOSE maintains the state of the previous moment.

The modulation signal selection circuit is composed of a NOT gate, two OR gates, an AND gate and a dead time control, and is used to determine the modulation mode of the DC-DC circuit through the mode selection signal CHOOSE;

The buck core circuit consists of two pairs of power MOS tubes, a NOT gate, a two-input AND gate, and a two-input OR gate. The mode selection signal CHOOSE is used to select the appropriate gate width to provide energy to the load.

Preferably, the logic control circuit is composed of three D flip-flops, a 4-to-1 data selector, a three-input NOR gate, and a three-input AND gate; the input signal of the three-input NOR gate comes from the output signals Q ₀ , Q ₁ , Q ₂ of the three D flip-flops, and the output signal is the control signal A ₀ of the 4-to-1 data selector; the input signal of the three-input AND gate also comes from the output signals Q ₀ , Q ₁ , Q ₂ of the three D flip-flops, and the output signal is the control signal A ₁ of the 4-to-1 data selector; the negative terminal of the comparator COMP is connected to the output voltage V _EA of the error amplifier EA in the pulse width modulation loop, and the positive terminal is connected to the reference voltage V ₁ ; the CLK signals of the three D flip-flops DFF are connected to the drive signal VH of the switch tube M1 in the buck core circuit; the three D flip-flops DFF are triggered by the rising edge of the drive signal VH to store the output voltage of the comparator COMP; the two input terminals D ₀ and D ₃ of the data selector are connected to the mode selection signal CHOOSE, the input terminal D ₁ is connected to GND, and the input terminal D ₂ is connected to VDD.

Preferably, the control signals _A1 and _A0 are generated by the states of the outputs _Q0 , _Q1 , _Q2 of the three D flip-flops. When the circuit is in a light load to heavy load situation, _VEA < _V1 , the output of the comparator is 1, when the first rising edge of the drive signal VH arrives, _Q0 , _Q1 , _Q2 = ₁₀₀ , A1, _A0 = 00, the mode selection signal CHOOSE remains unchanged, when the second rising edge of the drive signal VH arrives, _Q0 , _Q1 , _Q2 = 110, _A1 , _A0 = 00, the mode selection signal CHOOSE remains unchanged, when the third rising edge of the drive signal VH arrives, _Q0 , _Q1 , _Q2 = 111, _A1 , _A0 = 10, the mode selection signal CHOOSE = 1 (VDD), then the circuit will enter the PWM pulse width modulation mode, and _Q0 , _Q1 , _Q2 =001~110, the logic control circuit pushes out that the mode selection signal CHOOSE=1(VDD), and the modulation mode of the circuit will not change; when the circuit is in a light load condition, V _EA >V ₁ , the output of the comparator is 0, when the first rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ =011, A ₁ , A ₀ =00, the mode selection signal CHOOSE remains unchanged, when the second rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ =001, A ₁ , A ₀ =00, the mode selection signal CHOOSE remains unchanged, when the third rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ =000, A ₁ , A ₀ =01, the mode selection signal CHOOSE=0(GND), at this time the mode selection signal CHOOSE=0, the circuit enters PSM (pulse skipping cycle) modulation, at this time Q ₀ , Q _1. When Q ₂ = 001-110, it can be deduced from the logic control circuit that the mode selection signal CHOOSE = 0, and the modulation mode of the circuit will not change.

Preferably, the pulse width modulation loop includes an error amplifier EA, a comparator COMP, an RS trigger, and a triangular wave generator V _RAMP . The triangular wave generator V _RAMP is used to generate a triangular wave and a clock signal V _CLK with a fixed period. The positive terminal of the error amplifier is connected to the feedback voltage VOUT fed back from the output end of the DC-DC converter, and the negative terminal is connected to the reference voltage V _REF . The positive terminal of the comparator COMP is connected to the V _RAMP signal, and the negative terminal is connected to the error amplifier output V _EA . After rectification by the RS trigger, the output signal is a PWM pulse width modulation signal with a constant period and a duty cycle that changes according to the load.

Preferably, the step-down core circuit is composed of two pairs of large-size power MOS tubes M1 and M3, M2 and M4, an inverter, two two-input OR gates, and a two-input AND gate; the gates of M1 and M3 are connected to the drive signals VH and VL respectively, and the gates of M2 and M4 are connected to the drive signals VH1 and VL1 respectively; the input signal of the inverter comes from the mode selection signal CHOOSE, the input signal of the two-input OR gate is the output signal of the inverter and the drive signal VH of the power MOS tube M1, and the output signal is the drive signal VH1 of the power MOS tube M2; the input signal of the two-input AND gate is the mode selection signal CHOOSE and the drive signal VL of the power MOS tube M3, and the output signal is the drive signal VL1 of the power MOS tube M4.

Preferably, when the buck core circuit is in a heavy load condition, the mode selection signal CHOOSE=1, the drive signal VH=VHI, VL=VL1, and both pairs of power MOS are turned on to provide energy for the load; when the circuit is in a light load condition, the mode selection signal CHOOSE=0, the drive signal VHI=1, the drive signal VL1=0, and the power MOS tubes M1 and M3 are turned on to provide energy for the load.

Preferably, the modulation signal selection circuit is composed of two two-input OR gates, a two-input AND gate, an inverter, and a dead time control module. The input signal of the NOT gate comes from the mode selection signal CHOOSE, and the output signal is connected to the input end of the two-input OR gate OR2. The input of the two-input OR gate OR1 comes from the pulse width modulation PWM and the mode selection signal CHOOSE, and the output signal is connected to the input end of the AND gate. The two-input OR gate OR2 inputs the output signal from the pulse skipping modulation PSM and the NOT gate, and the output signal is connected to the input end of the AND gate. The two-input AND gate inputs the output signals from the two OR gates, the input signal of the dead time control module comes from the two-input AND gate, and the output is a non-overlapping control signal VH and VL.

Preferably, in the modulation signal selection circuit, when the mode selection signal CHOOSE=1, the drive signal VH=PWM (pulse width modulation), PWM pulse width modulation is used, and both pairs of power MOS in the buck core circuit are turned on to provide energy for the load; when the mode selection signal CHOOSE=0, VH=PSM (pulse skipping cycle), PSM pulse skipping cycle modulation is used, and power MOS tubes M1 and M3 are turned on to provide energy for the load.

Preferably, the inverter is composed of a PMOS device and an NMOS device, wherein the source of the PMOS device is connected to the power supply voltage, the drain is connected to the drain of the NMOS device, the gate is connected to the gate of the NMOS device, and the source of the NMOS device is grounded, and its main function is to reverse the input signal. The dead time control module is composed of two NOR gates and 9 NOT gates. The input signal comes from the output of the AND gate in the modulation signal selection circuit, and the output signal is a pair of non-overlapping drive signals VH and VL. Its main function is to avoid the large-size power MOS tubes in the buck core circuit from being turned on at the same time, directly grounding the power supply voltage, generating a large current, and causing damage to the circuit.

FIG3 shows a logic control circuit for mode switching of a DC-DC converter. The function of the logic control circuit is to generate a mode selection signal CHOOSE according to the load condition. When the circuit is in a heavy load condition, V _EA <V ₁ , the output of the comparator is 1, when the first rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ = 100, when the second rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ = 110, when the third rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ = 111, at this time the mode selection signal CHOOSE = 1, the drive signal VH = PWM (pulse width modulation), the circuit enters the PWM (pulse width modulation) mode, at this time Q ₀ , Q ₁ , Q ₂ = 001 to 110, it can be inferred from the modulation signal selection circuit that the mode selection signal CHOOSE = 1, the modulation mode of the circuit will not change, so as to avoid external interference and cause the generation of an erroneous mode selection signal CHOOSE, causing the entire circuit to switch back and forth between different modes, affecting the efficiency of the circuit.

Similarly, when the circuit is in a light load condition, V _EA >V ₁ , the output of the comparator is 0, when the first rising edge of the driving signal VH arrives, Q ₀ , Q ₁ , Q ₂ = 011, when the second rising edge of the driving signal VH arrives, Q ₀ , Q ₁ , Q ₂ = 001, when the third rising edge of the driving signal VH arrives, Q ₀ , Q ₁ , Q ₂ = 000, at this time the mode selection signal CHOOSE = 0, the driving signal VH = PSM (pulse skipping period), the circuit enters PSM mode modulation, at this time Q ₀ , Q ₁ , Q ₂ = 001-110, it can be inferred from the modulation signal selection circuit that the mode selection signal CHOOSE = 0, the modulation mode of the circuit will not change, so as to avoid external interference and cause the generation of an erroneous mode selection signal CHOOSE, causing the entire circuit to switch back and forth between different modes, affecting the efficiency of the circuit.

When the circuit is in a heavy load condition, the mode selection signal CHOOSE=1, the drive signal VH=VHI, VL=VL1, and both pairs of power MOS are turned on to provide energy for the load. When the circuit is in a light load condition: the mode selection signal CHOOSE=0, the power MOS tubes M1 and M3 are turned on to provide energy for the load.

Simulation results

1. The transient simulation results of the adaptive clock signal VH are shown in Figure 4. It can be seen from Figure 4 that when the mode selection signal CHOOSE=1, the drive signal VH=PWM (pulse width modulation), that is, the clock signal CLK of the three D flip-flops DFF is a PWM (pulse width modulation) waveform. When the mode selection signal CHOOSE=0, the drive signal VH=PSM (pulse skipping period), the clock signal CLK of the D flip-flop DFF is PSM (pulse skipping period), and the frequency drops significantly.

2. The transient simulation results of the mode selection signal CHOOSE are shown in Figure 5. When the load current changes from 100mA to 5mA, the first rising edge of the drive signal VH arrives, Q ₀ = 0, the second rising edge of the drive signal VH arrives, Q ₁ = 0, and when the third rising edge of the drive signal VH arrives, Q ₂ = 0. At this time, the mode selection signal CHOOSE = 0, the drive signal VH = PSM (pulse skipping cycle), and the circuit enters PSM (pulse skipping cycle) modulation. When the load current changes from 100mA to 5mA, the first rising edge of the drive signal VH arrives, Q ₀ = 1, the second rising edge of the drive signal VH arrives, Q ₁ = 1, and the third rising edge of the drive signal VH arrives, Q ₂ = 1. At this time, the mode selection signal CHOOSE = 1, the drive signal VH = PWM (pulse width modulation), and the circuit enters PWM mode modulation.

3. The transient simulation results of anti-interference ability are shown in Figure 6. In Figure 6(a), when in heavy load, the load current is 100mA, the first rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ = 011, the second rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ = 001, when the third rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ = 100, because Q ₀ , Q ₁ , Q ₂ = 000 does not appear, the mode selection signal CHOOSE still maintains the original state, so as to avoid external interference and cause the generation of the wrong mode selection signal CHOOSE, so that the whole circuit switches back and forth between different modes, affecting the efficiency of the circuit.

It can be seen from the above results that the mode switching signal circuit applied to a DC-DC converter of the present invention can provide an accurate mode switching signal for the DC-DC converter and avoid generating an erroneous mode selection signal CHOOSE due to external interference.

The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims (8)

1. A logic control circuit used in DC-DC converter mode switching, characterized in that it includes: a logic control circuit, a buck core circuit, a modulation signal selection circuit and a pulse width modulation loop, wherein: The pulse width modulation loop is used to generate a PWM pulse width modulation signal with a constant period and a duty cycle that changes with the output load; The logic control circuit is used to generate a correct mode selection signal CHOOSE according to the load condition, specifically including: The logic control circuit compares the output voltage V _EA of the operational amplifier EA in the pulse width modulation loop with V ₁ , where V ₁ represents the reference voltage, to generate the output signals Q ₀ , Q ₁ and Q ₂ of the D flip-flop. When Q ₀ , Q ₁ , Q ₂ = 111, the mode selection signal CHOOSE = 1, or when Q ₀ , Q ₁ , Q ₂ = 000, the mode selection signal CHOOSE = 0, the mode switching will be performed, and when Q ₀ , Q ₁ , Q ₂ are in other states 001 to 110, the mode selection signal CHOOSE maintains the state of the previous moment; The modulation signal selection circuit is composed of a NOT gate, two OR gates, an AND gate and a dead time control, and is used to determine the modulation mode of the DC-DC circuit through the mode selection signal CHOOSE; The buck core circuit consists of two pairs of power MOS tubes, a NOT gate, a two-input AND gate, and a two-input OR gate. The mode selection signal CHOOSE is used to select the appropriate gate width to provide energy to the load. The logic control circuit is composed of three D flip-flops, a 4-to-1 data selector, a three-input NOR gate, and a three-input AND gate; the input signal of the three-input NOR gate comes from the output signals Q ₀ , Q ₁ , Q ₂ of the three D flip-flops, and the output signal is the control signal A ₀ of the 4-to-1 data selector; the input signal of the three-input AND gate also comes from the output signals Q ₀ , Q ₁ , Q ₂ of the three D flip-flops, and the output signal is the control signal A ₁ of the 4-to-1 data selector; the negative terminal of the comparator COMP is connected to the output voltage V _EA of the error amplifier EA in the pulse width modulation loop, and the positive terminal is connected to the reference voltage V ₁ ; the CLK signals of the three D flip-flops DFF are connected to the drive signal VH of the switch tube M1 in the buck core circuit; the three D flip-flops DFF are triggered by the rising edge of the drive signal VH to store the output voltage of the comparator COMP; the two input terminals D ₀ and D ₃ of the data selector are connected to the mode selection signal CHOOSE, the input terminal D ₁ is connected to GND, and the input terminal D ₂ is connected to VDD. 2. A logic control circuit for mode switching of a DC-DC converter according to claim 1, characterized in that control signals _A1 and _A0 are generated by the states of outputs _Q0 , _Q1 , _Q2 of three D flip-flops; when the circuit is in a light load to heavy load situation, _VEA < _V1 , the output of the comparator is 1; when the first rising edge of the drive signal VH arrives, _Q0 , _Q1 , _Q2 =100, _A1 , _A0 =00, the mode selection signal CHOOSE remains unchanged; when the second rising edge of the drive signal VH arrives, _Q0 , _Q1 , _Q2 =110, _A1 , _A0 =00, the mode selection signal CHOOSE remains unchanged; when the third rising edge of the drive signal VH arrives, _Q0 , _Q1 , _Q2 =111, _A1 , _{A0 =} 10, the mode selection signal CHOOSE=1(VDD), then the circuit will enter the PWM pulse width modulation mode, and ... When Q ₁ , Q ₂ = 001~110, the logic control circuit pushes out that the mode selection signal CHOOSE = 1 (VDD), and the modulation mode of the circuit will not change; when the circuit is in a light load condition, V _EA > V ₁ , the output of the comparator is 0, when the first rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ = 011, A ₁ , A ₀ = 00, the mode selection signal CHOOSE remains unchanged, when the second rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ = 001, A ₁ , A ₀ = 00, the mode selection signal CHOOSE remains unchanged, when the third rising edge of the drive signal VH arrives, Q ₀ , Q ₁ , Q ₂ = 000, A ₁ , A ₀ = 01, the mode selection signal CHOOSE = 0 (GND), at this time the mode selection signal CHOOSE = 0, the circuit enters PSM (pulse skipping cycle) modulation, at this time Q ₀ , Q _1. When _Q2 = 001~110, it can be deduced from the logic control circuit that the mode selection signal CHOOSE = 0, and the modulation mode of the circuit will not change. 3. A logic control circuit for use in a DC-DC converter mode switching according to claim 1, characterized in that the pulse width modulation loop comprises an error amplifier EA, a comparator COMP, an RS trigger, and a triangular wave generator V _RAMP , wherein the triangular wave generator V _RAMP is used to generate a triangular wave and a clock signal V _CLK with a fixed period, the error amplifier is connected to a feedback voltage VOUT fed back from the output end of the DC-DC converter at a positive terminal, and to a reference voltage V _REF at a negative terminal, the comparator COMP is connected to the V _RAMP signal at a positive terminal, and to the error amplifier output V _EA at a negative terminal, and the output signal after rectification by the RS trigger is a PWM pulse width modulation signal with a constant period and a duty cycle that changes according to the load. 4. A logic control circuit for use in a DC-DC converter mode switching according to claim 1, characterized in that the step-down core circuit is composed of two pairs of large-size power MOS tubes M1 and M3, M2 and M4, an inverter, two two-input OR gates, and a two-input AND gate; the gates of M1 and M3 are respectively connected to drive signals VH and VL, VH and VL are a pair of modulation signals to drive the MOS tubes M1 and M3 respectively, the gates of M2 and M4 are respectively connected to drive signals VH1 and VL1, VH1 and VL1 are a pair of modulation signals to drive the MOS tubes M2 and M4 respectively; the input signal of the inverter comes from the mode selection signal CHOOSE, the input signal of the two-input OR gate is the output signal of the inverter and the drive signal VH of the power MOS tube M1, and the output signal is the drive signal VH1 of the power MOS tube M2, the input signal of the two-input AND gate is the mode selection signal CHOOSE and the drive signal VL of the power MOS tube M3, and the output signal is the drive signal VL1 of the power MOS tube M4. 5. A logic control circuit for mode switching of a DC-DC converter according to claim 4, characterized in that when the buck core circuit is in a heavy load condition, the mode selection signal CHOOSE=1, the drive signal VH=VHI, VL=VL1, and the two pairs of power MOS are all turned on to provide energy for the load; when the circuit is in a light load condition, the mode selection signal CHOOSE=0, the drive signal VHI=1, the drive signal VL1=0, the power MOS tubes M1 and M3 are turned on to provide energy for the load. 6. A logic control circuit for mode switching of a DC-DC converter according to claim 1, characterized in that the modulation signal selection circuit is composed of two two-input OR gates, a two-input AND gate, an inverter, and a dead time control module, the input signal of the NOT gate comes from the mode selection signal CHOOSE, and the output signal is connected to the input end of the two-input OR gate OR2, the input of the two-input OR gate OR1 comes from the pulse width modulation PWM and the mode selection signal CHOOSE, the output signal is connected to the input end of the AND gate, the two-input OR gate OR2 inputs the output signal from the pulse skipping modulation PSM and the NOT gate, the output signal is connected to the input end of the AND gate, the two-input AND gate inputs the output signals from the two OR gates, the input signal of the dead time control module comes from the two-input AND gate, and the output is a non-overlapping control signal VH and VL. 7. A logic control circuit for use in mode switching of a DC-DC converter according to claim 6, characterized in that, in the modulation signal selection circuit, when the mode selection signal CHOOSE=1, the drive signal VH=PWM pulse width modulation, PWM pulse width modulation modulation is used, and both pairs of power MOS in the buck core circuit are turned on to provide energy for the load; when the mode selection signal CHOOSE=0, VH=PSM pulse skipping cycle, PSM pulse skipping cycle modulation is used, and power MOS tubes M1 and M3 are turned on to provide energy for the load. 8. A logic control circuit for use in a DC-DC converter mode switching according to claim 6, characterized in that the inverter is composed of a PMOS device and an NMOS device, wherein the source of the PMOS device is connected to the power supply voltage, the drain is connected to the drain of the NMOS device, the gate is connected to the gate of the NMOS device, and the source of the NMOS device is grounded, and its function is to reverse the input signal, and the dead time control module is composed of two NOR gates and 9 NOT gates; The input signal comes from the output of the AND gate in the modulation signal selection circuit, and the output signal is a pair of non-overlapping drive signals VH and VL. Its function is to prevent the large-size power MOS tubes in the buck core circuit from being turned on at the same time, directly grounding the power supply voltage, generating a large current, and causing damage to the circuit.