CN115296671A - Digital-to-analog conversion circuit with mixed structure - Google Patents
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Abstract
The application relates to a digital-to-analog conversion circuit with a mixed structure, which comprises a coarse quantization module, a fine quantization + input stage fusion module and an output stage module, wherein the coarse quantization module is of a resistance type structure and is used for performing coarse quantization processing and outputting coarse quantization voltage under the control of a high-order digital code in a DAC input signal. The positive end of the differential input stage of the fine quantization + input stage fusion module is connected with the output end of the coarse quantization module, the negative end of the differential input stage of the fine quantization + input stage fusion module is connected with the output end of the output stage module, and the output end of the fine quantization + input stage fusion module is connected with the input end of the output stage module. The fine quantization + input stage fusion module is an MOS tube type structure of a multiplexing input stage and is used for performing fine quantization processing on the coarse quantization voltage under the control of a low-order digital code in a DAC input signal, outputting the fine quantization voltage and obtaining the DAC output voltage through the output stage module. The comprehensive performance of the DAC is greatly improved.
Description
Technical Field
The invention belongs to the technical field of digital-to-analog conversion circuits, and relates to a digital-to-analog conversion circuit with a mixed structure.
Background
Digital-to-Analog Converter (DAC) is used as a bridge for connecting Digital signals and Analog signals, is a main channel for information exchange between a Digital system and an external Analog world, and has wide application in the fields of communication, medical treatment, industrial control and the like. DACs are various in kind, and are classified into resistive DACs, capacitive DACs, and current DACs according to their structures.
The resistive DAC has difficulty in achieving high resolution and poor linearity. If the Kelvin structure is adopted, the DAC of N bits needs
A series connection of equivalent resistors
For the DAC with high resolution ratio, a large number of resistors and switches are needed for switch control, a large amount of circuit area is occupied, and cost is overlarge. Due to physical size constraints, resistive DACs have limited resolution, typically 8-bits to 10-bits. The natural accuracy of the resistor is not high, which has an effect on performance.
In order to reduce the circuit area and cost, a segmented resistor structure has been proposed in the market, which implements a DAC function by coarse quantization and fine quantization, which can reduce the circuit area compared to a conventional structure. However, in the process of implementing the present invention, the inventor finds that the matching problem of two sections of resistors in coarse quantization and fine quantization of the DAC with the segmented resistor structure is also obvious, which affects the precision of the DAC, and during the coarse quantization, the second section of resistor is connected in parallel with the first section of resistor, which changes the equivalent resistance of the resistor string, which causes the coarse quantization to be inaccurate and affects the linearity of the DAC, so that compared with other types of DACs, the indexes such as precision, linearity, power consumption and the like of the resistor-type DAC are still obviously lagged behind, and the technical problem of low comprehensive performance still exists.
Disclosure of Invention
Aiming at the problems in the traditional method, the invention provides the digital-to-analog conversion circuit with the mixed structure, which can effectively reduce the area, the circuit complexity and the power consumption of a DAC circuit, effectively improve the precision and the linearity of the DAC and greatly improve the comprehensive performance of the DAC.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
on one hand, the digital-to-analog conversion circuit with the mixed structure comprises a coarse quantization module, a fine quantization + input stage fusion module and an output stage module, wherein the coarse quantization module is of a resistance type structure and is used for performing coarse quantization processing under the control of a high-order digital code in a DAC input signal and outputting a coarse quantization voltage;
the positive end of a differential input stage of the fine quantization + input stage fusion module is connected with the output end of the coarse quantization module, the negative end of the differential input stage of the fine quantization + input stage fusion module is connected with the output end of the output stage module, and the output end of the fine quantization + input stage fusion module is connected with the input end of the output stage module;
the fine quantization + input stage fusion module is an MOS tube type structure of a multiplexing input stage and is used for performing fine quantization processing on the coarse quantization voltage under the control of a low-order digital code in a DAC input signal, outputting the fine quantization voltage and obtaining the DAC output voltage through the output stage module.
In one embodiment, the differential input stage of the fine quantization + input stage fusion module is a differential input stage of a buffer, a comparator or a PGA.
In one embodiment, the differential input stage of the fine quantization + input stage fusion module is a differential input stage of a buffer, and the differential input stage includes a cascode differential structure, a source follower differential structure, or a cascode differential structure.
In one embodiment, the differential input stage positive end of the fine quantization + input stage fusion module comprises L MOS tube basic units of which the drain sources are respectively connected in parallel, the structures of the MOS tube basic units are the same, the channel lengths of the MOS tubes are the same, and the channel widths are in binary proportional relation; l is the total digit of the low-digit numerical code;
the MOS tube grid of each MOS tube basic unit is selectively connected into a coarse quantization voltage under the control of each bit of the low-bit digital code; the coarse quantization voltage includes a high quantization voltage or a low quantization voltage.
In one embodiment, the MOS transistor basic unit includes a selection switch and an MOS transistor, a control terminal of the selection switch is used for accessing the low-bit digital code, an input terminal of the selection switch is connected to an output terminal of the coarse quantization module, an output terminal of the selection switch is connected to a gate of the MOS transistor, a source of the MOS transistor is grounded, and a drain of the MOS transistor is connected to a negative input terminal of the output stage module.
In one embodiment, the differential input stage positive end of the fine quantization + input stage fusion module further comprises a terminal compensation unit, the terminal compensation unit comprises a control switch and a basic MOS transistor, a control end of the control switch is used for accessing a fixed low potential, an input end of the control switch is connected with an output end of the coarse quantization module, an output end of the control switch is connected with a gate of the basic MOS transistor, a source of the basic MOS transistor is grounded, and a drain of the basic MOS transistor is connected with a negative input end of the output stage module;
the channel length of the basic MOS tube is the same as that of the MOS tube of the basic unit of the MOS tube, the channel width of the MOS tube of the basic unit of each MOS tube is m times of the channel width of the basic MOS tube, wherein,
，
)。
in one embodiment, the negative terminal of the differential input stage of the fine quantization + input stage fusion module comprises 2 with drain and source respectively connected in parallel L The MOS tubes have the same basic structure, and L is the total digit of the low-order digital code;
the grid electrode of each basic MOS tube is respectively connected with the output end of the output stage module, the source electrode of each basic MOS tube is grounded, and the drain electrode of each basic MOS tube is connected with the positive input end of the output stage module.
In one embodiment, the MOS transistor is an NMOS transistor or a PMOS transistor.
In one embodiment, the coarse quantization module includes a resistor string circuit formed by serially connecting a plurality of resistors and a plurality of matched control switches, and each control switch is respectively used for selecting and outputting a voltage across the corresponding resistor as a coarse quantization voltage.
In one embodiment, the high order digital codes in the DAC input signal are decoded using 7-128.
One of the above technical solutions has the following advantages and beneficial effects:
according to the digital-to-analog conversion circuit with the mixed structure, a new DAC framework is designed, the second section of the segmented DAC and the input stage of the post-stage circuit are fused together, and the design complexity and the circuit complexity of the framework are reduced; because the resistance area often will be bigger than the MOS pipe area in the physics realization, and come the thin quantization precision that the thin quantization voltage of thin quantization voltage can be than resistance through the MOS pipe high, one is because first section resistance is when the quantization in the segmentation resistance structure, second section resistance can connect in parallel on first section resistance, make the quantization precision receive the influence, another one is resistance and can be followed parasitic resistance in the physics realization, lead to matching not well, thereby also can influence the quantization precision, comparatively speaking, the quantization precision who uses the MOS pipe then can accomplish very high. Therefore, the fine quantization function of the segmented DAC (such as the fine quantization of a resistance type second segment) is realized by multiplexing the MOS tube of the input stage, so that the circuit area can be effectively reduced, and in the fine quantization process, the MOS tube is used for replacing a resistor, the influence of insufficient resistor precision on the DAC precision can be reduced, so that the aims of more effectively reducing the DAC circuit area, the circuit complexity and the power consumption, improving the precision and the linearity of the DAC and greatly improving the comprehensive performance of the DAC are fulfilled.
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In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a DAC architecture of a conventional segmented resistor structure;
FIG. 2 is a block diagram of a mixed-structure DAC circuit according to an embodiment;
FIG. 3 is a schematic diagram of the circuit structure of the fine quantization + input stage fusion module in one embodiment;
FIG. 4 is a schematic diagram of the differential input stage positive side circuit structure of the fine quantization + input stage fusion module in one embodiment;
FIG. 5 is an enlarged schematic diagram of a partial circuit structure of the fine quantization + input stage fusion module in one embodiment;
FIG. 6 is a diagram illustrating a digital-to-analog conversion circuit with a hybrid structure according to another embodiment;
FIG. 7 is a diagram showing simulation results of static parameters of the DAC according to an embodiment, wherein (a) is a differential non-linearity result, and (b) is an integral non-linearity result.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It should be appreciated that reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
One skilled in the art will appreciate that the embodiments described herein can be combined with other embodiments. The term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items and includes such combinations. It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element and be integral therewith, or intervening elements may also be present. The terms "one end," "the other end," and the like are used herein for illustrative purposes only.
As shown in fig. 1, the DAC of the conventional segmented resistor structure mainly includes four parts: in fig. 1, a decoding module 1 (may be denoted as Decode 1) is used for decoding MSB digital codes into control codes for directly controlling the switching of the switches of the coarse quantization module, a decoding module 2 (may be denoted as Decode 2) is used for decoding LSB digital codes into digital codes for directly controlling the switching of the switches of the fine quantization module, a trigger (may be denoted as Deglitch), CLK is used for indicating clock, V, and the like REF Denotes the value of the reference voltage VREF, V OUT Representing the output voltage of the buffer.
Aiming at the technical problem that the DAC of the traditional segmented resistor structure is not high in comprehensive performance, the fine quantization module and the input stage of the buffer are fused together, the four original parts of the DAC are reduced into three parts, namely the coarse quantization module, the fine quantization module, the input stage of the buffer and the output stage of the buffer, so that the area and the circuit complexity of the DAC are further reduced, the output of the first section cannot be influenced by the second section, the coarse quantization result is accurate, and the DAC has good linearity.
The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.
In one embodiment, as shown in fig. 2, the present application provides a digital-to-analog conversion circuit 100 with a hybrid structure, a coarse quantization module 10, a fine quantization + input stage fusion module 20, and an output stage module 30. The coarse quantization module 10 is of a resistor type structure, and is configured to perform coarse quantization processing under the control of a high-order digital code in the DAC input signal and output a coarse quantization voltage. The positive end of the differential input stage of the fine quantization + input stage fusion module 20 is connected with the output end of the coarse quantization module 10, the negative end of the differential input stage of the fine quantization + input stage fusion module 20 is connected with the output end of the output stage module 30, and the output end (V) of the fine quantization + input stage fusion module 20 op And V on ) Connected to the input of the output stage block 30. The fine quantization + input stage fusion module 20 is a multiplexing input stage MOS tube type structure, and is configured to perform fine quantization processing on the coarse quantization voltage under the control of the low-order digital code in the DAC input signal, output the fine quantization voltage, and obtain a DAC output voltage V after passing through the output stage module 30 OUT 。
It can be understood that the design concept of the digital-to-analog conversion circuit 100 with the hybrid structure is as follows: aiming at the traditional resistance type segmented DAC circuit structure, a fine quantization module is fused to the input stage of the circuit at the rear stage to form a new circuit module, namely the fine quantization + input stage fusion module 20, and the module quantizes the lower part of the DAC by multiplexing MOS (the number of the added parallel MOS tube units can be determined according to the quantizing requirement of the lower part of the DAC) of the original input stage and simultaneously cooperates with an output stage module 30 to ensure the driving capability of the DAC. Therefore, the circuit structures of the coarse quantization module 10 and the output stage module 30 and the operation principles thereof can be understood by referring to the same principle of the corresponding coarse quantization module 10 and the output stage module 30 in the conventional resistor-type segmented DAC circuit structure in the field, and the detailed description thereof is not repeated in this specification.
Specifically, for a DAC conversion process with N bits, the DAC conversion process can be divided into two parts, i.e., an upper H bit and a lower L bit, and values of H and L can be selected according to actual conversion requirements (N = H + L). The coarse quantization module 10 is a resistor-type DAC structure, and is responsible for quantizing the high H bits of the DAC, which mainly consists ofThe resistor string voltage divider circuit is composed of a DAC input signal, and different high quantization/low quantization voltages (marked as V) can be obtained through different digital codes (marked as MSB, also called as high-order digital code) of high H bits in the DAC input signal H And V L Collectively referred to as coarsely quantized voltages.
The fine quantization + input stage fusion module 20 splits the MOS transistor of the input stage into MOS transistor parallel units of different sizes (for example, the MOS transistor parallel units can be split into L or L +1 MOS transistor unit parallel branches), and the low-L-bit digital code (marked as LSB, also called as low-bit digital code) in the DAC input signal controls the gate of the parallel MOS transistor unit to be connected to the high quantization/low quantization voltage, so as to change the output voltage of the fine quantization + input stage fusion module 20, thereby implementing the fine quantization processing. The output voltage of the fine quantization + input stage fusion module 20 passes through the output stage module 30 to obtain the output voltage of the DAC. In fig. 2, S represents a control switch connected to a high quantization/low quantization voltage in the fine quantization + input stage fusion module 20, and a clock control module directly provides a clock required for normal operation for the decoding module of the digital code.
In the digital-to-analog conversion circuit 100 with the hybrid structure, a new DAC architecture is designed, and the second section of the segmented DAC is fused with the input stage of the post-stage circuit, so that the design complexity and the circuit complexity of the architecture are reduced; because the resistance area often will be bigger than the MOS pipe area in the physics realization, and come the thin quantization precision that the thin quantization voltage of subtotal resistance can be higher through the MOS pipe, firstly because first section resistance is when the quantization in the segmentation resistance structure, second section resistance can connect in parallel on first section resistance, make quantization precision receive the influence, secondly resistance can be followed parasitic resistance in the physics realization, lead to matching not good, thereby also can influence quantization precision, comparatively speaking, quantization precision that uses the MOS pipe then can accomplish very high. Therefore, the fine quantization function of the segmented DAC (such as the fine quantization of the resistance type second segment) is realized by multiplexing the MOS tube of the input stage, so that the circuit area can be effectively reduced, and the MOS tube is used for replacing the resistance during the fine quantization, so that the influence of insufficient resistance precision on the DAC precision can be reduced, the circuit area, the circuit complexity and the power consumption of the DAC can be effectively reduced, the precision and the linearity of the DAC are improved, and the comprehensive performance of the DAC is greatly improved.
In one embodiment, the differential input stage of the fine quantization + input stage fusion module 20 is a buffer, a comparator or a differential input stage of a PGA (Programmable Gain Amplifier).
It can be understood that the subsequent stage circuit of the DAC may be a connected buffer, a comparator, or a circuit module in the field such as PGA, and the output of the DAC is used as the input of the circuit modules, that is, the fine quantization module may be fused with the input stages of the circuit modules, and the principles thereof are the same, as long as the input stage is guaranteed to be a differential structure, so that the circuit design of the fine quantization + input stage fusion module 20 is adopted, which may make the DAC have a strong applicability.
In one embodiment, the differential input stage of the fine quantization + input stage fusion module 20 is a differential input stage of a buffer. The differential input stage comprises a cascode differential structure, a source follower differential structure or a cascode differential structure.
Further, in this embodiment, the post-stage circuit of the DAC is a connected buffer, so that the differential input stage of the fine quantization + input stage fusion module 20 is the differential input stage of the buffer, and the differential structure thereof may be a common-source amplification differential structure in the field, a common-source follower differential structure in the field, or a common-source cascode amplification differential structure in the field, and the principles of the differential structures are the same, and the differential input stage is a positive terminal (which may be denoted as an M positive terminal) Left side of ) The input is the output voltage of the coarse quantization module 10, the high quantization voltage or the low quantization voltage is selected and accessed through changing the control value of the low-order digital code in the DAC input signal, the difference of the output voltages of the differential input stage is realized, the purpose of fine quantization is achieved, and the negative terminal (which can be recorded as M) of the differential input stage Right side ) The input is fed back from the output voltage of the output stage module 30.
By merging the input stage of the buffer with the fine quantization, the fine quantization function of the lower portion of the DAC can be realized while increasing the driving capability of the DAC.
In one embodiment, as shown in fig. 3, the differential input stage positive terminal 202 of the fine quantization + input stage fusion module 20 includes L MOS transistor basic units 2021 with drains and sources respectively connected in parallel, where the MOS transistor basic units 2021 have the same structure, the MOS transistors have the same channel length, and the channel widths are in binary proportional relationship; l is the total number of low-order digital codes. The MOS transistor gates of the MOS transistor basic units 2021 are selectively connected to the coarse quantization voltages under the control of each bit of the low-bit digital codes respectively; the coarse quantization voltage includes a high quantization voltage or a low quantization voltage.
It will be appreciated that the differential input stage positive terminal 202 (which may be denoted as M) of the fine quantization + input stage fusion module 20 Left side of The negative end can be correspondingly marked as M Right side ) In the circuit of (3), L MOS transistors of the positive terminal 202 of the original differential input stage are multiplexed to form L MOS transistor basic units 2021, and each MOS transistor basic unit 2021 is controlled by a different corresponding digital code to support the realization of the fine quantization and the input stage function. The circuit structure of each MOS transistor basic unit 2021 is the same, and the channel length of the MOS transistor included in each MOS transistor basic unit 2021 is also the same, so as to better implement circuit layout matching and facilitate circuit design. However, the channel widths of the MOS transistors in each MOS transistor basic unit 2021 are different, and a binary proportional relationship is formed between the channel widths of the MOS transistors in all the MOS transistor basic units 2021.
Specifically, the width-to-length ratio of the MOS transistors in the basic unit 2021 of the MOS transistors affects transconductance (i.e., the ratio of the variation of the drain current to the variation of the gate-to-source voltage), and the channel lengths of the MOS transistors are set to be the same, and when the widths of the MOS transistors are in a binary proportional relationship, the transconductance of the MOS transistors in the basic unit 2021 of the MOS transistors also changes in a binary proportional relationship, and finally the transconductance of the MOS transistors also changes in a binary proportional relationship in response to the output voltage, that is, the change of the gate access voltage (V) of each MOS transistor is changed (i.e., the change of the gate access voltage of each MOS transistor is changed) (i.e., the change of the gate access voltage of each MOS transistor is reflected) H Or V L ，V H Representing high quantization voltage, V L Representing low quantization voltages) to realize that the output voltage of the output stage of the buffer changes according to the rule of the required binary proportional relationship, and then different output voltages can be obtained through different low-bit digital codes, which is also the working principle of the DAC.
Through the design of the basic unit 2021 of the L MOS transistors with the drains and sources respectively connected in parallel, a simpler circuit structure design can be achieved, and a required fine quantization and input stage fusion design can be realized.
In one embodiment, as shown in fig. 4, the MOS transistor basic unit 2021 includes a selection switch S i And MOS tube M jN Selection switch S i The control end is used for accessing a low-bit digital code and selecting a switch S i Is connected to the output of the coarse quantization module 10, a selection switch S i The output end of the MOS tube M is connected with the MOS tube M jN A gate electrode of (1). MOS transistor M jN Source-level grounded MOS transistor M jN Is connected to the negative input of the output stage module 30. Wherein,
，
。
further, in the present embodiment, each MOS transistor basic unit 2021 is formed by a MOS transistor M jN And its input voltage selection controlled selection switch S i Composition, selection switch S i Controlled by a low digit code of the corresponding bit, which is high (D = 1) and controls the MOS transistor M jN Grid of is connected with V H If the low digit code is low (D = 0), the MOS transistor M is controlled jN Grid of (C) is connected with V L . According to the difference of the L value, different numbers of MOS tube basic units 2021 can be connected in parallel, and the MOS tube M in each MOS tube basic unit 2021 jN The channel lengths are the same (the MOS channel lengths are the same, so that layout matching can be better realized, circuit design is facilitated, and the channel width only needs to be changed when the binary proportional relation is set subsequently), so that the channel widths are in the binary proportional relation.
It should be noted that the circuit of the differential input stage shown in fig. 4 is a schematic diagram of a buffer input stage of a common-source amplification differential structure as an example, and the principle of the rest types of differential structures is the same. Besides the modified basic MOS transistor unit 2021 as described above, it may include existing resistors, a power supply VDD, and a constant current source, etc. as shown in fig. 4, and those skilled in the art may refer to the operation principle of the same devices included in the input stage of the buffer of the conventional common source amplification differential structure, and understand the same principle for the aforementioned existing components included in fig. 4, and the same principle also applies for the same parts in the remaining drawings.
Through the specific structural design of the MOS transistor basic unit 2021, the circuit structure is simple and efficient, and the circuit area can be reduced better and the design and production cost can be reduced.
In one embodiment, as shown in fig. 4, the differential input stage positive terminal 202 of the fine quantization + input stage fusion module 20 further comprises a termination compensation unit 204. The terminal compensation unit 204 includes a control switch S 00 And a basic MOS tube M 0 Control switch S 00 The control terminal is used for accessing a fixed low potential (marked as D) 00 ) Low-digit digital code, control switch S 00 Is connected with the output end of the coarse quantization module 10, controls the switch S 00 The output end of the MOS transistor is connected with a basic MOS transistor M 0 A gate electrode of (2). Basic MOS tube M 0 Source-level grounded, basic MOS transistor M 0 Is connected to the negative input of the output stage module 30. Basic MOS tube M 0 The channel length of the MOS transistor M is the same as that of the MOS transistor basic unit 2021, and the channel width of the MOS transistor of each MOS transistor basic unit 2021 is the basic MOS transistor M 0 M times the channel width, where m =2 i ，i∈[0，L)。
Further, in this embodiment, the differential input stage positive terminal 202 of the fine quantization + input stage fusion module 20 is further provided with a terminal compensation unit 204, so as to form L +1 MOS transistor units with the same structure and different MOS transistor sizes in parallel with each MOS transistor basic unit 2021, and the MOS transistor M in the terminal compensation unit 204 is used as the basic MOS transistor 0 The channel width ratio of all MOS transistor basic units 2021 can be expressed as 1 L-1 In combination with the circuit layout implementation, the value of the proportionality coefficient M of each MOS transistor basic unit 2021 can be set to be M 0 2 of (2) i Therefore, the channel width ratio of the MOS transistor can meet the binary requirement.
Specifically, for example, in circuit design, it is often necessary to provide proportional variation (generally, integral multiple ratio, according to the channel width of the MOS transistor)DAC requirements, to vary in binary proportion) such as M 1 =2*M 0 In the circuit, M can be added 0 Setting as basic MOS tube, and then setting M 1 M can be realized by setting the M value of the tube to be 2 1 =2*M 0 . The m value can be regarded as m copies of m basic MOS transistors, and the source and drain are respectively connected in parallel, as illustrated in the circuit part at the upper right corner in fig. 5 below, and illustrated in fig. 5 as m =4, because a binary relation needs to be obtained in the application, the m value only needs to be 2 i That is, the value of i is a positive integer, i<L, for example, lower 5 bits, may realize a 1.
Fixed low potential D 00 =0 for controlling the switch S 00 At control terminal D 00 Under the control of (2), the control switch S is kept 00 Is connected to the low quantization voltage V output by the coarse quantization module 10 L So that M is 0 The grid of the grid is kept connected to a low quantization voltage V L Thereby ensuring the realization of terminal compensation.
The terminal compensation unit 204 plays a terminal compensation role, such as the following ratio 1.
Further, theoretical derivation regarding the detailed implementation of the above-mentioned fine quantization can be shown as follows:
assuming that the transconductance (the ratio of the variation of the drain current to the variation of the gate-source voltage) of the MOS transistor in each basic cell can be approximately regarded as not varying with the variation of the input voltage (the gate-source voltage),
note M in termination compensation unit 204 0 Has a transconductance of
. Due to the positive terminal 202 (M) of the differential input stage Left side of ) Is composed of 2 L Each M0 is composed of Left side of Transconductance of (2)G m And
the relationship is as follows:
so M 0 (introduction of M) 0 To better illustrate the difference in width of each tube, M 0 It shall mean that the pipe with M =1, i.e. the terminal compensating unit 204 in fig. 4 and 5, the rest M not being 1 cannot be called M 0 ）
The transconductance of (a) is:
suppose M Left side of Is an equivalent input voltage ofV X From fig. 4, it can be seen that:
M left side of The total current of (1) is equal to the sum of the branch currents, and the following results are obtained:
wherein
Are each M 0 ，M N0 ，…，M NL-1 The gate inputs a voltage. Then:
in the above formula
Represents a reference voltage。
M can be obtained by bringing formula (5) into formula (4) Left side of Total current of (c):
the DAC output voltage (DAC transfer function) is then:
as can be seen from the above equation (7), the fine quantization + input stage fusion module 20 can correctly implement the fine quantization function and has good linearity. From the coarse quantization module 10, it can be seen that:
the combined simplification of the above three equations (7), (8) and (9) can obtain the DAC transfer function as:
according to the DAC transfer function of the above equation (10), the DAC structure of the present application can realize the DAC quantization function and ensure good monotonicity.
In one embodiment, as shown in FIG. 4, the negative terminal of the differential input stage of the fine quantization + input stage fusion module 20 comprises 2 with the drain and the source connected in parallel respectively L And L is the total digit of the low-order digit codes. The gate of each basic MOS transistor is connected to the output terminal of the output stage module 30, the source of the basic MOS transistor is grounded, and the drain of the basic MOS transistor is connected to the positive input terminal of the output stage module 30.
It can be understood that the negative terminal of the differential input stage of the fine quantization + input stage fusion module 20 also designs a unit structure similar to the positive terminal, so as to cooperate with the positive terminal 202 of the differential input stage of the fine quantization + input stage fusion module 20 to realize the complete input stage function.
In an embodiment, the MOS transistor in the above-mentioned fine quantization + input stage fusion module 20 may be an NMOS transistor or a PMOS transistor.
In one embodiment, as shown in fig. 6, the coarse quantization module 10 includes a resistor string circuit formed by serially connecting a plurality of resistors R and a plurality of matched control switches, and each control switch is respectively configured to select and output a voltage across a corresponding resistor R as a coarse quantization voltage. It can be understood that the coarse quantization module 10 adopts the classical structure of the conventional resistor string and its control switch, and the decoding module 1 in fig. 6 is used to decode the MSB digital code into the control code that directly controls the switch switching of the coarse quantization module 10; the decoding module 2 is used for decoding the LSB digital code into a digital code which directly controls the switch switching of the fine quantization + input stage fusion module 20;
representing the reference voltage and S represents the selection switch in the fine quantization + input stage fusion module 20.
In one embodiment, to facilitate understanding of the above scheme of the present application, the following is an example of a 12 (7 + 5) bit DAC design according to the above scheme. High H bit (MSB, note D) 11 -D 5 ) And low L bit (LSB, D) 4 -D 0 ) As shown in fig. 5 and 6, the coarse quantization module 10 is a resistor string circuit composed of 128 resistors with a resistance value R, a control switch for selecting high quantization voltage and low quantization voltage outputs is respectively arranged between every two resistors, one end of the resistor string is connected to ground, and the other end is connected to a reference voltage VREF. The resistor string divides the reference voltage VREF equally, and the corresponding potential expression of the division (H =7 in this example):
wherein,
，V REF the value of the reference voltage VREF.
Further, the high-order digital codes in the DAC input signals are decoded by 7-128. Specifically, the MSB (here, decoding from 7 to 128) controls the switch to select different divided potentials of the resistor string (the voltage across one of the resistors in the resistor string is selected as the voltage across the MSBV H AndV L the calculation of the following equations (12) and (13) yields the high quantization voltage(s) output by the coarse quantization module 10V H ) And low quantization voltage: (V L ) By calculation, we can obtain:
the fine quantization + input stage fusion module 20 continuously quantizes the high quantization/low quantization voltage obtained by the coarse quantization, as shown in fig. 6, the fine quantization + input stage fusion module 20 and the output stage module 30 are connected in the form of a follower, the output end of the output stage module 30 is connected to the negative terminal of the differential input stage of the fine quantization + input stage fusion module 20, and it is assumed that the equivalent voltage of the positive terminal 202 of the differential input stage of the fine quantization + input stage fusion module 20 is the equivalent voltageV X Then:
output voltageV OUT Equivalent voltage of the differential input stage positive terminal 202 of the integration module 20 with the refinement + input stageV X And changes accordingly.
The fine quantization + input stage fusion module 20 is responsible for implementing the fine quantization and input stage functions, and the specific circuit is shown in fig. 5, which includes a differential input stage positive terminal 202 (M) Left side of ) The input is the output voltage of the coarse quantization module 10, and the high quantization voltage and the low quantization voltage are selected and accessed through changing the digital code LSB control value, so that the difference of the output voltage is realized, and the purpose of fine quantization is achieved; negative terminal (M) of differential input stage Right side ) The input is fed back from the output of the output stage module 30.
The differential input stage positive terminal 202 of the fine quantization + input stage fusion module 20 is composed ofL+1 basic units similar to the terminal compensation unit 204 are connected in parallel, each basic unit includes an MOS transistor and its corresponding switch, each basic unit is controlled by different low-bit digital codes, and different numbers of basic units can be connected in parallel according to different L values. The channel length of the MOS tube in each basic unit is the same, the channel width is in a binary proportional relation, namely the ratio of the channel width of each MOS tube is 1 L-1 Considering the layout implementation, the m value of each basic unit is set to be 2 i Therefore, the channel width ratio of the MOS transistor can meet the binary requirement, wherein the termination compensation unit 204 plays a role of termination compensation and participates in actual DAC conversion.
Right side (i.e., negative terminal of differential input stage) NMOS transistor M of fine quantization + input stage fusion module 20 Right side Is composed of 2 L Basic MOS tube M with source and drain respectively connected in parallel 0 Composition (in this example)L= 5) i.e. m has a value of 2 L Remember M Right side Has a total transconductance of G m Since the differential pairs are equal in current and equal in aspect ratio in the balanced state, the transconductances are the same, i.e., M Left side of The transconductance of the tube is likewise G m 。
Suppose for each basic cell NMOS transistor, no matter what the gate voltage isV H Or alsoV L No transconductance will followV H AndV L changes occur. Memory NMOS tube M in basic unit 0 Has a transconductance of g m0 . Due to M Left side of Is composed of 2 L The basic MOS tube is composed of the following components:
so M N0 -M NL-1 The transconductance of (a) is:
suppose M Left side of Has an equivalent input voltage ofV X From fig. 6, it can be seen that:
M left side of The total current of (1) is equal to the sum of the branch currents, and the following results are obtained:
wherein
Are each M 0 ，M N0 ，…，M NL-1 The gate inputs a voltage. Then:
the above formula is substituted into the former formula to obtain M Left side of Total current of (c):
the DAC output voltage (DAC transfer function) is then:
in the case of this example, the user is,H=7，L=5, substituting the above formula:
the derivation of the DAC conversion of this example has been completed, and the derivation analysis proves that the DAC structure can realize the DAC function. The 12-bit DAC circuit is built in Cadence application and static parameter simulation is performed, and the result is shown in fig. 7, where the Differential Nonlinearity (DNL) in fig. 7 (a) is-0.06 LSB/+0.039LSB, and the Integral Nonlinearity (INL) in fig. 7 (b) is-0.287 LSB/+1.063LSB. Practice proves that the design scheme is suitable for the segmented DAC, and has no requirement on the number of bits, for example, the design scheme is suitable for 8-16 bit DACs.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features. The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, without departing from the concept of the present application, several variations and modifications can be made without departing from the spirit of the present application. Therefore, the protection scope of the present patent should be subject to the appended claims.
Claims (9)
1. A digital-to-analog conversion circuit with a mixed structure is characterized by comprising a coarse quantization module, a fine quantization + input stage fusion module and an output stage module, wherein the coarse quantization module is of a resistance type structure and is used for performing coarse quantization processing under the control of a high-order digital code in a DAC input signal and outputting a coarse quantization voltage;
the positive end of the differential input stage of the fine quantization and input stage fusion module is connected with the output end of the coarse quantization module, the negative end of the differential input stage of the fine quantization and input stage fusion module is connected with the output end of the output stage module, and the output end of the fine quantization and input stage fusion module is connected with the input end of the output stage module;
the fine quantization + input stage fusion module is an MOS tube type structure of a multiplexing input stage and is used for performing fine quantization processing on the coarse quantization voltage under the control of a low-order digital code in the DAC input signal, outputting the fine quantization voltage and obtaining the DAC output voltage through the output stage module;
the positive end of the differential input stage of the fine quantization + input stage fusion module comprises L MOS tube basic units with drain sources respectively connected in parallel, the structures of the MOS tube basic units are the same, the channel lengths of the MOS tubes are the same, and the channel widths are in binary proportional relation; l is the total number of digits of the low-digit digital code;
the MOS tube grid of each MOS tube basic unit is selectively connected to the coarse quantization voltage under the control of each digit code in the low-digit codes; the coarse quantization voltage includes a high quantization voltage or a low quantization voltage.
2. The hybrid digital-to-analog conversion circuit of claim 1, wherein the differential input stage of the fine quantization + input stage fusion module is a differential input stage of a buffer, a comparator or a PGA.
3. The digital-to-analog conversion circuit with the hybrid structure as claimed in claim 1 or 2, wherein the differential input stage of the fine quantization + input stage fusion module is a differential input stage of a buffer, and the differential input stage comprises a cascode differential structure, a source follower differential structure or a cascode differential structure.
4. The digital-to-analog conversion circuit with the hybrid structure according to claim 3, wherein the basic unit of the MOS transistor comprises a selection switch and an MOS transistor, a control terminal of the selection switch is used for accessing the low-order digital code, an input terminal of the selection switch is connected to an output terminal of the coarse quantization module, an output terminal of the selection switch is connected to a gate of the MOS transistor, a source of the MOS transistor is grounded, and a drain of the MOS transistor is connected to a negative input terminal of the output stage module.
5. The digital-to-analog conversion circuit with the hybrid structure according to claim 4, wherein the positive end of the differential input stage of the fine quantization + input stage fusion module further comprises a terminal compensation unit, the terminal compensation unit comprises a control switch and a basic MOS transistor, a control end of the control switch is used for accessing a fixed low potential, an input end of the control switch is connected with an output end of the coarse quantization module, an output end of the control switch is connected with a gate of the basic MOS transistor, a source of the basic MOS transistor is grounded, and a drain of the basic MOS transistor is connected with a negative input end of the output stage module;
the channel length of the basic MOS tube is the same as that of the MOS tubes of the basic units of the MOS tubes, the channel width of the MOS tube of each basic unit of the MOS tube is m times of that of the basic MOS tube, wherein,
，
。
6. the mixed-structure digital-to-analog conversion circuit of claim 3, wherein the negative terminal of the differential input stage of the fine quantization + input stage fusion module comprises drain-source electrodes connected in parallel respectively
The MOS tubes are identical in basic, and L is the total digit of the low-digit digital code;
the grid electrode of each basic MOS tube is respectively connected with the output end of the output stage module, the source electrode of the basic MOS tube is grounded, and the drain electrode of the basic MOS tube is connected with the positive input end of the output stage module.
7. The mixed structure DAC circuit of claim 6 wherein the MOS transistor is an NMOS transistor or a PMOS transistor.
8. The dac circuit of claim 1, wherein the coarse quantization module comprises a resistor string circuit formed by serially connecting a plurality of resistors and a plurality of control switches, and each control switch is configured to selectively output a voltage across a corresponding resistor as the coarse quantization voltage.
9. The mixed-structure digital-to-analog conversion circuit of claim 8, wherein the high-order digital codes in the DAC input signal are decoded by 7-128.
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