CN115296662A - Multiphase clock generating circuit and method - Google Patents

Abstract

The present application discloses a multiphase clock generation circuit and method, belonging to the technical field of signal processing, and used to solve the problems of complex structure and high power consumption of the existing multiphase clock generation circuit. The circuit includes: a frequency dividing module, the signal input terminal of the frequency dividing module receives a connected clock source signal, and is used to divide the frequency of the clock source signal by two to generate a first reference clock signal and a second reference clock signal that intersect with each other a clock signal; a multi-phase clock generation module, the multi-phase clock generation module is connected to the output end of the frequency division module for receiving the first reference clock signal and the second reference clock signal, and the output has a predetermined phase Differential relationship of the four-phase clock signal.

Description

A multi-phase clock generation circuit and method

technical field

The application belongs to the technical field of signal processing, and in particular relates to a multi-phase clock generation circuit and method.

Background technique

In signal processing systems, such as time-interleaved analog-to-digital converter (Time-Interleaved Analog-to-Digital Converter, TIADC), multi-channel time-to-digital converter (Time-to-Digital Converter, TDC) design, etc., need Using multiple clocks with a fixed clock phase difference relationship, such multiple clocks are called multi-phase clocks.

Most of the existing multi-phase clocks are generated by technologies such as phase-locked loops (Phase Locked Loops, PLL) or delay-locked loops (Delay Loop Lock, DLL). No-way filter and external reference clock, there are problems such as complex circuit and high power consumption.

Contents of the invention

The purpose of the embodiment of the present application is to provide a multi-phase clock generation circuit and method, which can solve the problems of complex structure and high power consumption of the existing multi-phase clock generation circuit.

In order to solve the above-mentioned technical problems, the application is implemented as follows:

In the first aspect, the embodiment of the present application provides a multi-phase clock generation circuit, the circuit includes: a frequency division module, the signal input terminal of the frequency division module receives the connection clock source signal, and is used to generate the clock source signal Perform frequency division by two to generate a first reference clock signal and a second reference clock signal intersecting with each other; a multiphase clock generation module, the multiphase clock generation module is connected to the output end of the frequency division module for receiving the The first reference clock signal and the second reference clock signal output four-phase clock signals with a predetermined phase difference relationship.

In the second aspect, the embodiment of the present application provides a method for generating a multi-phase clock, the method is applied to the multi-phase clock generation circuit described in the first aspect above, and the method includes: performing a clock source signal through a frequency division module Divide by two to generate a first reference clock signal and a second reference clock signal intersecting with each other, wherein the signal input terminal of the frequency division module receives the clock source signal; the first reference is received by the multi-phase clock generation module The clock signal and the second reference clock signal output a four-phase clock signal with a predetermined phase difference relationship, wherein the multi-phase clock generation module is connected to the frequency division module.

In a third aspect, an embodiment of the present application provides an electronic device, the electronic device includes a processor, a memory, and a program or instruction stored in the memory and operable on the processor, and the program or instruction is The processor implements the steps of the method for generating a multi-phase clock as described in the second aspect when executed.

In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the multi-phase clock as described in the second aspect is implemented Generate method steps.

In the fifth aspect, the embodiment of the present application provides a chip, the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run programs or instructions, so as to implement the second aspect The steps of the multi-phase clock generation method.

In the embodiment of the present application, through the frequency division module, the signal input terminal of the frequency division module receives the connection clock source signal, and is used to divide the frequency of the clock source signal by two to generate the first reference clock signal and the intersecting first reference clock signal and The second reference clock signal: a multi-phase clock generation module, the multi-phase clock generation module is connected to the output of the frequency division module, used to receive the first reference clock signal and the second reference clock signal, and output The four-phase clock signal with a predetermined phase difference relationship can solve the problems of complex structure and high power consumption of the existing multi-phase clock generation circuit.

Description of drawings

FIG. 1 is a schematic structural diagram of a multi-phase clock generation circuit provided by an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a multi-phase clock generation module of another multi-phase clock generation circuit provided in an embodiment of the present application;

3 is a schematic structural diagram of a multi-phase clock generation module of another multi-phase clock generation circuit provided by an embodiment of the present application;

FIG. 4 is a schematic flowchart of a method for generating a multi-phase clock provided in an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a multi-phase clock generating device provided in an embodiment of the present application;

FIG. 6 is a schematic structural diagram of an electronic device provided by the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

The terms "first", "second" and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific sequence or sequence. It should be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application can be practiced in sequences other than those illustrated or described herein, and that references to "first," "second," etc. distinguish Objects are generally of one type, and the number of objects is not limited. For example, there may be one or more first objects. In addition, "and/or" in the specification and claims means at least one of the connected objects, and the character "/" generally means that the related objects are an "or" relationship.

A multi-phase clock generation circuit and method provided in the embodiments of the present application will be described in detail below through specific embodiments and application scenarios with reference to the accompanying drawings.

FIG. 1 is a schematic structural diagram of a multi-phase clock generation circuit provided by an embodiment of the present application. The multi-phase clock generating circuit 100 includes: a frequency division module 110, the signal input terminal of the frequency division module receives the connection clock source signal, and is used to divide the frequency of the clock source signal by two to generate first references intersecting each other. A clock signal and a second reference clock signal; a multiphase clock generation module 120, the multiphase clock generation module is connected to the output end of the frequency division module for receiving the first reference clock signal and the second reference The clock signal outputs a four-phase clock signal with a predetermined phase difference relationship.

In an implementation manner, the multi-phase clock generating circuit 100 transmits signals in a differential manner.

It should be noted that the transmission of signals in a differential manner can enhance the ability of the circuit to resist common-mode interference. The differential transmission means that the transmitting end transmits electrical signals with equal amplitude and opposite phase on the two signal lines, and the receiving end performs subtraction operation on the received signals of the two lines to obtain a signal with double the amplitude. The principle of anti-interference is: if the two signal lines are subjected to the same (in-phase, equal-amplitude) interference signal, since the receiving end subtracts the received signals of the two lines, the interference signal is basically cancelled.

As shown in FIG. 1, the input terminals VIP and VIN of the frequency division module 110 are used as the differential input terminals of the overall circuit, and the input clock source signal CLKIN is used to divide the frequency of the clock source signal by two to generate the first reference that intersects with each other. The clock signal Ref_CLK1 and the second reference clock signal Ref_CLK2 have a phase difference of 90°, which are respectively connected to the two differential input terminals VIP_1/VIN_1 and VIP_2/VIN_2 of the multiphase clock generation module 120, and the four pairs of differential inputs of the multiphase clock generation module 120 The output ports A_VOP/A_VON, B_VOP/B_VON, C_VOP/C_VON, D_VOP/D_VON are the four-phase clock signal output ports of the overall circuit, which respectively output the clock signals A_CLK, B_CLK, C_CLK, and D_CLK of the four channels.

The multi-phase clock generation circuit provided by this application can realize the output of the four-phase clock through the combination of the frequency division module and the multi-phase clock generation module, and does not require the feedback loop and The large-area loop filter and external reference clock are simple in structure, easy to design and produce, and have great advantages in area and power consumption.

In the multi-phase clock generation circuit provided by the embodiment of the present application, the signal input terminal of the frequency division module receives and connects the clock source signal through the frequency division module, and is used to divide the frequency of the clock source signal by two to generate mutual intersection The first reference clock signal and the second reference clock signal; a multi-phase clock generation module, the multi-phase clock generation module is connected to the output of the frequency division module for receiving the first reference clock signal and the The second reference clock signal outputs a four-phase clock signal with a predetermined phase difference relationship, which can solve the problems of complex structure and high power consumption of the existing multi-phase clock generation circuit.

In an implementation manner, the multi-phase clock generation module includes: a plurality of multiplexing modules, wherein each of the multiplexing modules is used to directly output or reverse the output of the first reference clock signal to obtain A signal of at least one channel in the four-phase clock signal; and/or, each of the multiplexing modules is used to directly output or invert the second reference clock signal to obtain the four-phase clock signal at least one channel of the signal.

In an implementation manner, each of the multiplexing modules includes a plurality of signal input terminals and a signal selection terminal, wherein each of the signal input terminals receives the first reference clock signal or the second reference clock signal Clock signal, the signals received by the multiple signal input terminals are not completely the same, and the signal selection terminal is used to control the multiplexing module to select from the first reference clock signal and the second reference clock signal An input obtains a signal of at least one channel of the four-phase clock signal.

The multi-phase clock generation module includes a mode selection terminal, and the mode selection terminal receives a mode control signal for controlling the generation of the four-phase clock signal in different modes, wherein the different modes correspond to different predetermined phase difference relationships .

In an implementation manner, the multi-phase clock generation module further includes: a buffer module, configured to directly output the first reference clock signal to obtain at least one channel of the four-phase clock signal Signal.

FIG. 2 is a schematic structural diagram of a multi-phase clock generation module of a multi-phase clock generation circuit provided by an embodiment of the present application. A multi-phase clock generation circuit provided by an embodiment of the present application includes: a frequency division module, the signal input terminal of the frequency division module receives a connected clock source signal, and is used to divide the frequency of the clock source signal by two to generate A first reference clock signal and a second reference clock signal intersecting each other; a multiphase clock generation module 220, the multiphase clock generation module is connected to the output end of the frequency division module for receiving the first reference clock signal and the second reference clock signal, output a four-phase clock signal with a predetermined phase difference relationship, wherein, as shown in Figure 2, the multi-phase clock generation module 220 includes: a buffer module 221 and 3 multiplexing modules 222, 223 and 224. Wherein, the differential input terminal VIP/VIN of the buffer module 221 is connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN, and its differential output terminal VOP/VON is used as the A channel differential output terminal of the circuit, and the output signal A_CLK can be seen from FIG. 1 The phase is 0°.

The VIP_1/VIN_1 terminal of the differential input channel 1 of the multiplexing module 222 is connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN; the VIP_2/VIN_2 terminal of the differential input channel 2 is connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN inversely; S< 0>Connect the strobe signal MODE_SELECT<0>, and the phase of 1 or 2 channels can be selected for output; its differential output terminal VOP/VON is used as the B-channel differential output terminal of the overall circuit, and the output signal B_CLK, its output phase can be seen from Figure 1 0° or 180°.

The VIP_1/VIN_1 end of the differential input path 1 of the multiplexing module 223 is connected to the second reference clock signal Ref_CLK2_VIP/Ref_CLK2_VIN; the VIP_2/VIN_2 end of the differential input path 2 is connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN; S<0 >Connect the strobe signal MODE_SELECT<1>, and the phase of 1 or 2 channels can be selected for output; its differential output terminal VOP/VON is used as the C channel differential output terminal of the overall circuit, and the output signal C_CLK, as shown in Figure 1, its output phase is 90° or 0°.

The VIP_1/VIN_1 terminal of the differential input channel 1 of the multiplexing module 224 is connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN; the VIP_2/VIN_2 terminal of the differential input channel 2 is connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN inversely; the differential input The VIP_3/VIN_3 terminal of channel 3 is reversely connected to the second reference clock signal Ref_CLK2_VIP/Ref_CLK2_VIN; S<0> is connected to the strobe signal MODE_SELECT<2>, and the phase of channel 1, 2 or 3 can be selected for output, and its differential output terminal VOP/ As the D-channel differential output terminal of the overall circuit, VON outputs the signal D_CLK. It can be seen from Figure 1 that its output phase is 0°, 180° or 270°.

In summary, through the selection of the control signal MODE_SELECT<2:0>, the main available outputs of this circuit are: 0°, 90°, 180°, 270°; 0°, 0°, 0°, 0°; 0°, 180°, 0°, 180° three output modes.

In an implementation manner, the frequency division module includes a synchronization signal terminal, and the synchronization signal terminal receives a synchronization control signal for synchronously controlling the generation of the first reference clock signal and the second reference clock signal .

In the embodiment of the present application, the frequency division module with a synchronization function can synchronize the four-phase clock, so as to realize the determination of the timing relationship. At the same time, through the parallel connection of multiple multiplexing modules, the clock source signal can be converted and output to obtain a four-phase clock signal with a predetermined phase difference relationship with fewer circuits. The circuit structure is simple and the power consumption is low. The design also has certain advantages in delay, temperature drift and phase noise.

In the multi-phase clock generation circuit provided by the embodiment of the present application, the signal input terminal of the frequency division module receives and connects the clock source signal through the frequency division module, and is used to divide the frequency of the clock source signal by two to generate mutual intersection The first reference clock signal and the second reference clock signal; a multi-phase clock generation module, the multi-phase clock generation module is connected to the output of the frequency division module for receiving the first reference clock signal and the The second reference clock signal outputs a four-phase clock signal with a predetermined phase difference relationship, which can solve the problems of complex structure and high power consumption of the existing multi-phase clock generation circuit.

In the multi-phase clock generation circuit provided by the embodiment of the present application, the multi-phase clock generation module includes: a plurality of multiplexing modules, wherein each of the multiplexing modules is used to generate the first reference clock signal directly outputting or inverting the output to obtain the signal of at least one channel of the four-phase clock signal; and/or, each of the multiplexing modules is used to directly output or invert the output of the second reference clock signal to obtain the The signal of at least one channel in the four-phase clock signal, each of the multiplexing modules includes a plurality of signal input terminals and a signal selection terminal, wherein each signal input terminal receives the first reference clock signal Or the second reference clock signal, the signals received by the multiple signal input terminals are not completely the same, and the signal selection terminal is used to control the multiplexing module from the first reference clock signal and the second reference clock signal Inputting one of the two reference clock signals to obtain the signal of at least one channel of the four-phase clock signals can solve the problems of complex structure and high power consumption of the existing multi-phase clock generation circuit.

In an implementation manner, the circuit further includes:

A plurality of registers, wherein each of the registers is connected to a signal selection terminal of a multiplexing module, and the numbers stored in each of the registers are used to control the corresponding multiplexing module from the first reference clock signal and Selecting one of the second reference clock signals to input a signal of at least one channel of the four-phase clock signal;

Or a decoder, the decoder is respectively connected to a plurality of the multiplexers, and is used to encode the mode control signal to obtain different numbers, wherein the different numbers are used to control the corresponding multiplexer The multiplexing module selects one of the first reference clock signal and the second reference clock signal to obtain a signal of at least one channel of the four-phase clock signal.

In one implementation, the multiple multiplexing modules include: multiple primary multiplexing modules and multiple secondary multiplexing modules, wherein each of the primary multiplexing modules The module is used to output one of the first reference clock signal and the second reference clock signal to obtain a third reference clock signal or a fourth reference clock signal, and each of the secondary multiplexing modules is used to combine The third reference clock signal or the fourth reference clock signal is output directly or inverted to obtain a signal of at least one channel of the four-phase clock signal.

FIG. 3 is a schematic structural diagram of a multi-phase clock generation module of another multi-phase clock generation circuit provided by an embodiment of the present application. Another embodiment of the present application provides a multi-phase clock generation circuit including: a frequency division module, the signal input terminal of the frequency division module receives a connected clock source signal, and is used to divide the frequency of the clock source signal by two, Generate a first reference clock signal and a second reference clock signal that intersect with each other; a multiphase clock generation module 320, the multiphase clock generation module is connected to the output end of the frequency division module for receiving the first reference clock signal and the second reference clock signal, and output a four-phase clock signal with a predetermined phase difference relationship. Wherein, as shown in FIG. 3 , the multi-phase clock generation module 320 includes: 6 multiplexing modules and a decoder 327, wherein, 6 multiplexing modules include 2 primary multiplexing modules 321, 322 and 4 secondary multiplexing modules 323, 324, 325 and 326, and the input terminal of the decoder 327 is connected Control signal MODE_SELECT<2:0>, output 6-bit control signal S<5:0>, used to control each multiplexing module to choose one of the first reference clock signal and the second reference clock signal The input obtains a signal of at least one channel of the four-phase clock signal.

Specifically, the VIP_1/VIN_1 end of the differential input path 1 of the first-level multiplexing module 321 is connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN; the VIP_2/VIN_2 end of the differential input path 2 is connected to the second reference clock signal Ref_CLK2_VIP/Ref_CLK2_VIN; The S<0> terminal is connected to the output signal S<0> of the decoder 327, and the phase of 1 or 2 channels can be selected for output; its differential output terminal VOP/VON outputs the third reference clock signal Ref_CLK3 to the subsequent circuit, and its output The phase is 0° or 90°.

The VIP_1/VIN_1 terminal of the differential input channel 1 of the first-level multiplexing module 322 is connected to the second reference clock signal Ref_CLK2_VIP/Ref_CLK2_VIN; the VIP_2/VIN_2 terminal of the differential input channel 2 is connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN; S<0 >The output signal S<1> of the terminal is connected to the decoder, and the phase of 1 or 2 channels can be selected for output; its differential output terminal VOP/VON is connected to the subsequent circuit as a differential signal, and its output phase is also 90° or 0° .

The VIP_1/VIN_1 terminal of the differential input channel 1 of the secondary multiplexing module 323 is directly connected to the output terminal VOP/VON of the primary multiplexing module 321; the VIP_2/VIN_2 terminal of the differential input channel 2 is reversely connected to the primary multiplexing Use the output terminal VOP/VON of the module 321; S<0> to connect the output signal S<2> of the decoder, and the phase of 1 or 2 channels can be selected for output; its differential output terminal VOP/VON is used as the A channel of the circuit Differential output, the output phase can be any phase of 0°, 90°, 180° or 270°.

The VIP_1/VIN_1 terminal of the differential input channel 1 of the secondary multiplexing module 324 is directly connected to the output terminal VOP/VON of the primary multiplexing module 322; the VIP_2/VIN_2 terminal of the differential input channel 2 is reversely connected to the primary multiplexing channel The output terminal VOP/VON of the multiplexing module 322; the S<0> terminal is connected to the output signal S<3> of the decoder, and the phase of 1 or 2 channels can be selected for output; its differential output terminal VOP/VON is used as the B of the circuit Channel differential output, the output phase can be any phase of 0°, 90°, 180° or 270°.

The VIP_1/VIN_1 terminal of the differential input channel 1 of the secondary multiplexing module 325 is directly connected to the output terminal VOP/VON of the primary multiplexing module 321; the VIP_2/VIN_2 terminal of the differential input channel 2 is reversely connected to the primary multiplexing Use the output terminal VOP/VON of the module 321; S<0> is connected to the output signal S<4> of the decoder, and the phase of 1 or 2 channels can be selected for output; its differential output terminal VOP/VON is used as the C channel of the circuit Differential output, the output phase can be any phase of 0°, 90°, 180° or 270°.

The VIP_1/VIN_1 terminal of the differential input path 1 of the secondary multiplexing module 326 is directly connected to the output terminal VOP/VON of the primary multiplexing module 322; the VIP_2/VIN_2 terminal of the differential input path 2 is reversely connected to the primary multiplexing Use the output terminal VOP/VON of the module 322; S<0> is connected to the output signal S<5> of the decoder, and the phase of 1 or 2 channels can be selected for output; its differential output terminal VOP/VON is used as the D channel of the circuit Differential output, the output phase can be any phase of 0°, 90°, 180° or 270°.

To sum up, through reasonable control of the decoder 327, the circuit can generate a four-phase output clock with any phase combination of 0°, 90°, 180°, and 270°.

In this embodiment, a plurality of multiplexing modules are cascaded in two stages, and the first-stage multiplexing module realizes outputting one of the first reference clock signal and the second reference clock signal, and the second-stage multiplexing module The multiplexing module realizes the direct output or reverse output of the signal on the basis of the first-level multiplexing module, so that the four-phase output clock of any phase combination can be output, thus, it can achieve good circuit matching and matching between channels it is good.

The present application further provides a multi-phase clock generation method, which is applied to the multi-phase clock generation circuit as shown in Figures 1 to 3, including: dividing the frequency of the clock source signal by two through a frequency division module to generate mutually intersecting The first reference clock signal and the second reference clock signal, wherein, the signal input terminal of the frequency division module receives the clock source signal; the first reference clock signal and the second reference clock signal are received by the multi-phase clock generation module A clock signal that outputs a four-phase clock signal with a predetermined phase difference relationship, wherein the multi-phase clock generation module is connected to the frequency division module, which can solve the problems of complex structure and high power consumption of the existing multi-phase clock generation circuit .

A method for generating a multi-phase clock provided by an embodiment of the present application will be described below through specific embodiments and application scenarios with reference to the accompanying drawings.

FIG. 4 shows a method for generating a multiphase clock provided by an embodiment of the present application. The method can be applied to the multi-phase clock generating circuit described in FIGS. 1 to 3 above, or the method can be executed by each functional module in the above-mentioned multi-phase clock generating circuit. In other words, the method can be implemented by software or hardware of each functional module installed in the multiphase clock generating circuit, and the method includes the following steps:

S401: Divide the frequency of the clock source signal by two by a frequency dividing module to generate a first reference clock signal and a second reference clock signal intersecting each other.

Wherein, the signal input terminal of the frequency division module receives the clock source signal.

S402: Receive the first reference clock signal and the second reference clock signal through a multi-phase clock generation module, and output four-phase clock signals with a predetermined phase difference relationship.

Wherein, the multi-phase clock generation module is connected to the frequency division module.

In an implementation manner, the above step S402 includes: outputting the first reference clock signal directly or inverting the output through each multiplexing module in multiple multiplexing modules to obtain the four-phase clock The signal of at least one channel in the signal; and/or, through each of the multiplexing modules in multiple multiplexing modules, the second reference clock signal is directly output or inverted to obtain the four-phase signal of at least one channel in the clock signal.

In an implementation manner, the above step S402 includes: receiving the first reference clock signal or the second reference clock signal through each signal input port, and controlling the multiplexing module from the One of the first reference clock signal and the second reference clock signal is input to obtain a signal of at least one channel of the four-phase clock signal, wherein each of the multiplexing modules includes a plurality of the signal inputs terminal and one of the signal selection terminals, the signals received by the multiple signal input terminals are not exactly the same.

In an implementation manner, the above step S401 includes: using the frequency division module to include a synchronization signal terminal, and the synchronization signal terminal receives a synchronization control signal, wherein the synchronization control signal is used to control the first reference clock signal Synchronous control is performed with the generation of the second reference clock signal.

In an implementation manner, the above step S402 includes: the multi-phase clock generation module includes a mode selection terminal, and the mode selection terminal receives a mode control signal, wherein the mode control signal is used to control all The four-phase clock signal, the different modes correspond to different predetermined phase difference relationships.

In an implementation manner, the above step S402 includes: connecting multiple registers to the signal selection terminals of multiple multiplexing modules, and controlling the corresponding multiplexing module One of the two reference clock signals is input to obtain the signal of at least one channel of the four-phase clock signals, wherein each of the registers stores a different code for controlling the corresponding multiplexing module.

In an implementation manner, the above step S402 includes: connecting the multiplexers through a decoder to encode the mode control signal to obtain different numbers, wherein the different numbers are used for Controlling the corresponding multiplexing module to select one of the first reference clock signal and the second reference clock signal to obtain a signal of at least one channel of the four-phase clock signal.

In an implementation manner, the method for generating a multiphase clock adopts a differential mode to transmit signals.

For the specific implementation of the above steps, please refer to the description of the relevant functional modules of the multi-phase clock generation circuit in Figs.

In a method for generating a multi-phase clock provided in an embodiment of the present application, the clock source signal is divided by two through a frequency division module to generate a first reference clock signal and a second reference clock signal that intersect with each other, wherein the frequency division module The signal input end of the signal input terminal receives the clock source signal; the multi-phase clock generation module receives the first reference clock signal and the second reference clock signal, and outputs a four-phase clock signal with a predetermined phase difference relationship, wherein the The multi-phase clock generation module is connected with the frequency division module, which can solve the problems of complex structure and high power consumption of the existing multi-phase clock generation circuit.

It should be noted that, for the multi-phase clock generation method provided in the embodiment of the present application, the execution body may be the multi-phase clock generation device, or a control module in the multi-phase clock generation device for executing the multi-phase clock generation method. In the embodiment of the present application, the method for generating a multi-phase clock performed by the multi-phase clock generating device is taken as an example to illustrate the multi-phase clock generating device provided in the embodiment of the present application.

Fig. 5 shows a schematic structural diagram of a multi-phase clock generating device provided by an embodiment of the present application. As shown in FIG. 5 , the multi-phase clock generation device 500 includes: a frequency division module 510, the signal input end of the frequency division module receives the clock source signal, and is used to divide the frequency of the clock source signal by two to generate mutually intersecting The first reference clock signal and the second reference clock signal; the multi-phase clock generation module 520, the multi-phase clock generation module is connected to the frequency division module for receiving the first reference clock signal and the second reference The clock signal outputs a four-phase clock signal with a predetermined phase difference relationship.

In an implementation manner, the multiphase clock generating device 500 transmits signals in a differential manner.

In an implementation manner, the multi-phase clock generation module 520 includes: a plurality of multiplexing modules, wherein each of the multiplexing modules is used to directly output or invert the first reference clock signal Obtain a signal of at least one channel of the four-phase clock signal; and/or, each of the multiplexing modules is used to directly output or invert the second reference clock signal to obtain the four-phase clock signal at least one of the channels in the signal.

In an implementation manner, each of the multiplexing modules includes a plurality of signal input terminals and a signal selection terminal, wherein each signal input terminal receives the first reference clock signal or the second reference clock signal Clock signal, the signals received by the multiple signal input terminals are not completely the same, and the signal selection terminal is used to control the multiplexing module to select from the first reference clock signal and the second reference clock signal An input obtains a signal of at least one channel of the four-phase clock signal.

The multi-phase clock generation module 520 includes a mode selection terminal, and the mode selection terminal receives a mode control signal for controlling the generation of the four-phase clock signal in different modes, wherein the different modes correspond to different predetermined phase differences relation.

In an implementation manner, the multi-phase clock generation module 520 further includes: a buffer module, configured to directly output the first reference clock signal to obtain at least one channel of the four-phase clock signal signal of.

In an implementation manner, the frequency division module 510 includes a synchronization signal terminal, and the synchronization signal terminal receives a synchronization control signal for synchronizing the generation of the first reference clock signal and the second reference clock signal control.

In an implementation manner, the multi-phase clock generating device 500 further includes:

A plurality of registers, wherein each of the registers is connected to a signal selection terminal of a multiplexing module, and the numbers stored in each of the registers are used to control the corresponding multiplexing module from the first reference clock signal and Selecting one of the second reference clock signals to input a signal of at least one channel of the four-phase clock signal;

Or a decoder, the decoder is respectively connected to a plurality of the multiplexers, and is used to encode the mode control signal to obtain different numbers, wherein the different numbers are used to control the corresponding multiplexer The multiplexing module selects one of the first reference clock signal and the second reference clock signal to obtain a signal of at least one channel of the four-phase clock signal.

In one implementation, the multiple multiplexing modules include: multiple primary multiplexing modules and multiple secondary multiplexing modules, wherein each of the primary multiplexing modules The module is used to output one of the first reference clock signal and the second reference clock signal to obtain a third reference clock signal or a fourth reference clock signal, and each of the secondary multiplexing modules is used to combine The third reference clock signal or the fourth reference clock signal is output directly or inverted to obtain a signal of at least one channel of the four-phase clock signal.

The multi-phase clock generation device in the embodiment of the present application may be a device, or may be a component, an integrated circuit, or a chip in a terminal, which is not specifically limited in the embodiment of the present application.

The multi-phase clock generation device in the embodiment of the present application may be a device with an operating system, and may also be other possible operating systems, which are not specifically limited in the embodiment of the present application.

The multi-phase clock generation device provided in the embodiment of the present application can realize the functions of the corresponding modules in the multi-phase clock generation circuit shown in FIG. 1 to FIG. To avoid repetition, I won't go into details here.

Optionally, as shown in FIG. 6 , the embodiment of the present application further provides an electronic device 600, including a processor 601, a memory 602, and programs or instructions stored in the memory 602 and operable on the processor 601, When the program or instruction is executed by the processor 601, it is realized that the clock source signal is divided by two through the frequency division module to generate a first reference clock signal and a second reference clock signal that intersect with each other, wherein the signal of the frequency division module The input terminal receives the clock source signal; the multi-phase clock generation module receives the first reference clock signal and the second reference clock signal, and outputs a four-phase clock signal with a predetermined phase difference relationship, wherein the multi-phase The clock generation module is connected with the frequency division module.

It should be noted that the embodiment of the electronic equipment in this specification and the embodiment of the multi-phase clock generation circuit in this specification are based on the same inventive concept, so the specific implementation of this embodiment can refer to the aforementioned corresponding multi-phase clock generation circuit. implementation, the repetition will not be repeated.

The embodiment of the present application also provides a readable storage medium, the readable storage medium stores a program or an instruction, and when the program or instruction is executed by the processor, each process of the above-mentioned multi-phase clock generation method embodiment is implemented, and can To achieve the same technical effect, in order to avoid repetition, no more details are given here.

Wherein, the processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.

The embodiment of the present application further provides a chip, the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the above multi-phase clock generation method Each process of the example, or realize the function of each module of the above-mentioned multi-phase clock generation circuit or multi-phase clock generation device embodiment, and can achieve the same technical effect, in order to avoid repetition, it is not repeated here.

It should be understood that the chips mentioned in the embodiments of the present application may also be called system-on-chip, system-on-chip, system-on-a-chip, or system-on-a-chip.

Those skilled in the art should understand that the embodiments of the present application may be provided as methods, apparatuses, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowcharts and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

In a typical configuration, the electronic device includes one or more processors (CPUs), input/output interfaces, network interfaces and memory.

Memory may include non-permanent storage in computer readable media, in the form of random access memory (RAM) and/or nonvolatile memory such as read only memory (ROM) or flash RAM. Memory is an example of computer readable media.

Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can be implemented by any method or technology for storage of information. Information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash memory or other memory technology, Compact Disc Read-Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical storage, Magnetic tape cartridge, tape magnetic disk storage or other magnetic storage device or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media excludes transitory computer-readable media, such as modulated data signals and carrier waves.

It should also be noted that the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes Other elements not expressly listed, or elements inherent in the process, method, commodity, or apparatus are also included. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

The embodiments of the present application have been described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementations. The above-mentioned specific implementations are only illustrative and not restrictive. Those of ordinary skill in the art will Under the inspiration of this application, without departing from the purpose of this application and the scope of protection of the claims, many forms can also be made, all of which belong to the protection of this application.

Claims (10)

1. A multiphase clock generation circuit, comprising:

the clock source processing device comprises a frequency division module, a first frequency division module and a second frequency division module, wherein a signal input end of the frequency division module receives a clock source signal and is used for carrying out frequency division on the clock source signal by two to generate a first reference clock signal and a second reference clock signal which are intersected with each other;

and the multi-phase clock generation module is connected with the frequency division module and used for receiving the first reference clock signal and the second reference clock signal and outputting a four-phase clock signal with a predetermined phase difference relation.

2. The circuit of claim 1, wherein the multi-phase clock generation module comprises:

a plurality of multiplexing modules, wherein each multiplexing module is configured to directly output or flip-flop the first reference clock signal to obtain a signal of at least one channel in the four-phase clock signal; and/or each multiplexing module is used for directly outputting or overturning the second reference clock signal to obtain a signal of at least one channel in the four-phase clock signals.

3. The circuit of claim 1, wherein the multi-phase clock generation module further comprises:

and the buffer module is used for directly outputting the first reference clock signal to obtain a signal of at least one channel in the four-phase clock signal.

4. The circuit of claim 2, wherein each of the multiplexing modules comprises a plurality of signal input terminals and a signal selection terminal, wherein each of the signal input terminals receives the first reference clock signal or the second reference clock signal, the signals received by the plurality of signal input terminals are not identical, and the signal selection terminal is configured to control the multiplexing module to select one of the first reference clock signal and the second reference clock signal to obtain the signal of at least one channel of the four-phase clock signals.

5. The circuit of claim 1, wherein the frequency-division block comprises a synchronization signal terminal that receives a synchronization control signal for synchronously controlling the generation of the first reference clock signal and the second reference clock signal.

6. The circuit of claim 1, wherein the multi-phase clock generation module comprises a mode selection terminal, the mode selection terminal receiving a mode control signal for controlling generation of the four-phase clock signals in different modes, wherein the different modes correspond to different predetermined phase difference relationships.

7. The circuit of claim 4 or 6, further comprising:

the digital code stored in each register is used for controlling the corresponding multiplexing module to select one from the first reference clock signal and the second reference clock signal and input the selected one to obtain a signal of at least one channel in the four-phase clock signals;

or the decoder is respectively connected with the multiplexers and is used for coding the mode control signal to obtain different codes, wherein the different codes are used for controlling the corresponding multiplexing module to select one of the first reference clock signal and the second reference clock signal to input to obtain a signal of at least one channel in the four-phase clock signal.

8. The circuit of claim 1, wherein the circuit transmits signals differentially.

9. A multiphase clock generation method applied to the multiphase clock generation circuit according to any one of claims 1 to 8, the method comprising:

dividing a clock source signal by two through a frequency dividing module to generate a first reference clock signal and a second reference clock signal which are intersected with each other, wherein a signal input end of the frequency dividing module receives the clock source signal;

and receiving the first reference clock signal and the second reference clock signal through a multi-phase clock generation module and outputting a four-phase clock signal with a predetermined phase difference relation, wherein the multi-phase clock generation module is connected with the frequency division module.

10. The method of claim 9, wherein receiving the first reference clock signal and the second reference clock signal by a multi-phase clock generation module and outputting a four-phase clock signal having a predetermined phase difference relationship comprises:

directly outputting or turning over the first reference clock signal by each multiplexing module in a plurality of multiplexing modules to obtain a signal of at least one channel in the four-phase clock signal; and/or directly outputting or overturning the second reference clock signal through each multiplexing module in a plurality of multiplexing modules to obtain a signal of at least one channel in the four-phase clock signal.

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