CN115295564A - Array substrates and display panels - Google Patents

Abstract

The application discloses array substrate and display panel belongs to and shows technical field. The array substrate includes: the semiconductor device comprises a substrate base plate, a grid electrode, a grid insulating layer and an active layer, wherein the grid electrode, the grid insulating layer and the active layer are arranged on the substrate base plate; the active layer comprises a first active layer and a second active layer which are arranged in a stacked mode; the first active layer is arranged close to the grid electrode, and the second active layer is positioned on one side of the first active layer, which is far away from the grid electrode; the mobility of the first active layer is higher than the mobility of the second active layer. The array substrate adopts the laminated active layer doped with the rare earth elements, so that the array substrate with high mobility, low off-state current and high stability is obtained.

Description

Array substrate and display panel

technical field

The present application relates to the display field, in particular to an array substrate and a display panel.

Background technique

With the further increase in the market demand for high-resolution and high-definition display equipment, metal oxides have higher mobility than amorphous silicon and lower leakage current than low-temperature polysilicon, and are more compatible with current processes and have excellent performance. Process uniformity and other characteristics have become a research hotspot in the field of array substrates in recent years, and are increasingly used in LCD and AMOLED display devices. However, due to the relatively low mobility of current conventional InGaZnO devices, it is currently difficult to apply to high-end smart terminal products that require higher resolution and clarity.

Therefore, there is an urgent need to provide an array substrate with excellent performance to solve the problems in the prior art.

Contents of the invention

The purpose of the present application is to provide an array substrate, which can improve device mobility and solve the above-mentioned shortcomings of the prior art.

The application provides an array substrate, including:

a base substrate, and a gate, a gate insulating layer and an active layer disposed on the base substrate;

The active layer includes a first active layer and a second active layer stacked; wherein, the first active layer is arranged close to the gate, and the second active layer is located on the first active layer. a side of the source layer away from the gate;

The mobility of the first active layer is higher than that of the second active layer.

Optionally, in some embodiments of the present application, the material of the active layer includes oxide semiconductor and rare earth metal oxide.

Optionally, in some embodiments of the present application, the oxide semiconductor includes one or more of indium gallium zinc oxide, indium gallium tin oxide, indium gallium oxide, indium oxide and indium zinc oxide.

Optionally, in some embodiments of the present application, the rare earth elements in the rare earth metal oxide include one or more of samarium, terbium, dysprosium, europium, erbium, tin, lanthanum, cerium, ytterbium and praseodymium .

Optionally, in some embodiments of the present application, the rare earth elements in the first active layer include one or more of samarium, terbium, dysprosium, europium, erbium and tin.

Optionally, in some embodiments of the present application, the doping ratio of the rare earth metal oxide in the first active layer is 0.001-0.1. Further, the doping ratio of the rare earth metal oxide in the first active layer is 0.01-0.05.

Optionally, in some embodiments of the present application, the rare earth elements in the second active layer include one or more of lanthanum, terbium, dysprosium, cerium, erbium, ytterbium and praseodymium.

Optionally, in some embodiments of the present application, the doping ratio of the rare earth metal oxide in the second active layer is 0.1-0.3.

Optionally, in some embodiments of the present application, the doping ratio of the rare earth metal oxide in the second active layer is the same as the doping ratio of the rare earth metal oxide in the first active layer, The mobility of the rare earth element in the second active layer is lower than that of the rare earth element in the first active layer.

Optionally, in some embodiments of the present application, the rare earth element in the second active layer is the same as the rare earth element in the first active layer, and the rare earth metal in the second active layer is oxidized The doping ratio of the compound is 0.15-0.3.

Optionally, in some embodiments of the present application, the rare earth element in the second active layer is different from the rare earth element in the first active layer, and the rare earth element in the second active layer The mobility of the element is lower than that of the rare earth element in the first active layer, and the doping ratio of the rare earth metal oxide in the second active layer is 0.1-0.3.

Optionally, in some embodiments of the present application, the mobility of the rare earth metal oxide doped in the first active layer is higher than the mobility of the rare earth metal oxide in the second active layer.

Optionally, in some embodiments of the present application, the array substrate includes:

Substrate substrate;

a second active layer disposed on the base substrate;

a first active layer disposed on the second active layer, the first active layer including a source region, a channel region and a drain region;

a gate insulating layer disposed on the channel region on the first active layer;

a gate disposed on the gate insulating layer;

a source, a source region disposed on the first active layer;

a drain, a drain region disposed on the first active layer;

a passivation layer disposed on the second active layer, the first active layer, the gate insulating layer, the gate, the source and the drain.

Optionally, in some embodiments of the present application, the array substrate includes:

Substrate substrate;

a gate, arranged on the base substrate;

a gate insulating layer disposed on the gate and the base substrate;

a first active layer disposed on the gate insulating layer;

a second active layer disposed on the first active layer; the second active layer includes a source region, a channel region and a drain region;

a source, a source region disposed on the second active layer;

a drain, a drain region disposed on the second active layer;

a passivation layer disposed on the gate, the gate insulating layer, the first active layer, the second active layer, the source and the drain.

Optionally, in some embodiments of the present application, the array substrate further includes an etching stopper layer.

The etch barrier layer is disposed between the second active layer, the source electrode, and the drain electrode.

The etch barrier layer is disposed on the channel region, part of the source region and part of the drain region on the second active layer.

Optionally, in some embodiments of the present application, the material of the passivation layer includes one or more of SiO _x (silicon oxide) and SiN _x (silicon nitride).

Optionally, in some embodiments of the present application, the passivation layer includes a first passivation layer and/or a second passivation layer.

The beneficial effect of this application is:

In the embodiment of the present application, a stacked active layer doped with rare earth elements is used, and a thin film with relatively high mobility and relatively high on-state current is formed on the front channel side, which can increase the on-state current; Low and relatively low off-state current films can reduce the off-state current.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 is a first structural schematic diagram of an array substrate provided by an embodiment of the present application;

Fig. 2 is a schematic diagram II of the structure of the array substrate provided by the embodiment of the present application;

Fig. 3 is a schematic diagram of the third structure of the array substrate provided by the embodiment of the present application;

Fig. 4 is the data diagram of the device parameter and characteristic detection that the embodiment 1～4 of the present application provides;

Fig. 5 is the data diagram of the device parameter and characteristic detection that the embodiment of the present application 9～12 provides;

Fig. 6 is the data diagram of the device parameter and characteristic detection that the embodiment 17～20 of the present application provides;

Fig. 7 is the data diagram of the device characteristic parameter and property detection that the embodiment 5～8 of the present application provides;

Fig. 8 is a data diagram of device parameters and characteristic detection provided by Embodiments 13 to 16 of the present application;

FIG. 9 is a data diagram of device parameters and characteristic detection provided by Examples 21-24 of the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application. In addition, it should be understood that the specific implementations described here are only used to illustrate and explain the present application, and are not intended to limit the present application. In addition, in the description of the present application, the term "including" means "including but not limited to". The terms first, second, third, etc. are used for designation only and do not impose numerical requirements or establish an order. Various embodiments of the present application may exist in the form of a range; it should be understood that the description in the form of a range is only for convenience and brevity, and should not be construed as a rigid limitation on the scope of the application; therefore, the described range should be regarded as The description has specifically disclosed all possible subranges as well as individual values within that range.

During the research and practice of the existing technology, the inventors of the present application found that the use of metal oxide semiconductors doped with rare earth elements further increases the mobility on the basis of low leakage current, making it more satisfying for high-end Show the development requirements of the product. However, due to the lower stability compared with the traditional InGaZnO system, its popularization is limited. The inventors of the present application precisely controlled the amount of rare earth doping and designed the structure of the device, so as to further improve the performance of the device.

The inventors of the present application have proposed a stacked metal oxide semiconductor device composed of rare earth elements and a specific molar ratio, which can simultaneously combine different advantages of devices with different doping ratios, so that the device has more excellent performance.

Embodiments of the present application provide an array substrate (TFT, Thin Film Transistor) and a display panel. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.

An embodiment of the present application provides an array substrate, including a base substrate, a gate, a gate insulating layer, and an active layer. The gate, the gate insulating layer and the active layer are all arranged on the base substrate.

The active layer includes a first active layer and a second active layer stacked. Further, the first active layer is arranged close to the gate, and the second active layer is located on the side of the first active layer away from the gate; the migration of the first active layer rate is higher than the mobility of the second active layer.

In the embodiment of the present application, the advantages of multiple doped oxide semiconductors are simultaneously formed through the stacked active layer structure, and the performance of the array substrate is improved.

In the embodiment of the present application, the active layer in the array substrate is a stacked layer structure, and the mobility of the layer close to the gate is higher than that of the layer far away from the gate. In the present application, the mobility can be regulated through the material of the active layer, and then the effect of the level of the mobility can be realized.

In some embodiments of the present application, the material of the active layer includes oxide semiconductor and rare earth metal oxide. Further, the oxide semiconductor includes one or more of indium gallium zinc oxide, indium gallium tin oxide, indium gallium oxide, indium oxide and indium zinc oxide. Further, the rare earth elements in the rare earth metal oxide include one or more of samarium, terbium, dysprosium, europium, erbium, tin, lanthanum, cerium, ytterbium and praseodymium.

Further, the rare earth element is doped in the form of its metal oxide, for example, the rare earth metal oxide is selected from samarium oxide, terbium oxide, dysprosium oxide, europium oxide, erbium oxide, tin oxide, lanthanum oxide, cerium oxide, oxide One or more of ytterbium and praseodymium oxide.

It can be understood that the mobility of the doped rare earth metal oxide in the first active layer is higher than the mobility of the rare earth metal oxide in the second active layer. That is to say, in the first active layer, the front channel needs to use an oxide semiconductor with high mobility; in the second active layer, the back channel needs to use a metal oxide semiconductor with relatively low mobility.

In some embodiments of the present application, the first active layer includes the oxide semiconductor and the rare earth metal oxide. Wherein, the rare earth elements in the first active layer include one or more of samarium, terbium, dysprosium, europium, erbium and tin. Moreover, the doping ratio of the rare earth metal oxide in the first active layer is 0.001-0.1. Further, the doping ratio of the rare earth metal oxide in the first active layer may be 0.01-0.05. It can be understood that the doping ratio in the present application is the molar ratio of doping elements, for example, 0.001-0.1 is 0.001-0.1:1, and the calculation is obtained by recording the value of the first active layer as 1. For example, the doping ratio of the rare earth metal oxide in the first active layer can be 0.001:1, 0.002:1, 0.003:1, 0.004:1, 0.005:1, 0.006:1, 0.007:1, 0.008:1 , 0.009:1, 0.01:1, 0.02:1, 0.03:1, 0.04:1, 0.05:1, 0.06:1, 0.07:1, 0.08:1, 0.09:1 or 0.1:1.

In some embodiments of the present application, the second active layer includes the oxide semiconductor and the rare earth metal oxide. Wherein, the rare earth elements in the second active layer include one or more of lanthanum, terbium, dysprosium, cerium, erbium, ytterbium and praseodymium. The doping ratio of the rare earth metal oxide in the second active layer is 0.1-0.3. Further, the doping ratio of the rare earth metal oxide in the second active layer is 0.3-0.7:1. For example, the doping ratio of the rare earth metal oxide in the second active layer may be 0.1:1, 0.12:1, 0.15:1, 0.2:1, 0.25:1 or 0.3:1.

The mobility of the rare earth metal oxide doped in the first active layer is higher than the mobility of the rare earth metal oxide in the second active layer. In the embodiment of the present application, the first active layer can be controlled by adjusting the type of rare earth element of the rare earth metal oxide in the first active layer and the second active layer and/or the specific doping ratio of the rare earth metal oxide. and the mobility of the second active layer is poor.

For example, when the doping ratio of the rare earth metal oxide in the second active layer is the same as that of the rare earth metal oxide in the first active layer, the rare earth metal oxide in the second active layer Mobility of the element is lower than that of the rare earth element in the first active layer.

For example, when the rare earth element in the second active layer is the same as the rare earth element in the first active layer, the doping ratio of the rare earth metal oxide in the second active layer is 0.15-0.3 . It can be understood that at this time, the doping ratio makes the mobility of the first active layer higher than the mobility of the second active layer.

For example, when the rare earth element in the second active layer is different from the rare earth element in the first active layer, and the mobility of the rare earth element in the second active layer is higher than that in the first active layer Rare earth elements in the active layer are low. That is to say, under the same doping ratio of different elements, the mobility of the rare earth metal oxide doped in the first active layer can be higher than that of the rare earth metal oxide in the second active layer. At this time, the doping ratio of the rare earth metal oxide in the second active layer may be 0.1-0.3.

In the embodiments of the present application, the doping ratio of the rare earth metal oxide is the molar doping ratio of the rare earth elements in the rare earth metal oxide in the corresponding active layer.

In the embodiment of the present application, an oxide semiconductor laminate film with a specific molar ratio doped with rare earth elements is formed, and a film with relatively high mobility and relatively high on-state current is formed on the front channel side, which can increase the on-state current; Forming a thin film with low mobility and relatively low off-state current on the back channel side can reduce the off-state current.

In some embodiments of the present application, the material of the passivation layer includes one or more of SiO _x (silicon oxide) and SiN _x (silicon nitride). Further, the passivation layer includes a first passivation layer and/or a second passivation layer. For example, the material of the first passivation layer is SiO _x ; for example, the material of the second passivation layer is SiN _x .

In some embodiments of the present application, the array substrate of the present application may be an array substrate of a BCE structure. Referring to FIG. 1 , the array substrate includes: a gate 102 , a gate insulating layer 103 , an active layer 104 , a source 1081 , a drain 1082 , and a passivation layer 107 disposed on a base substrate 101 .

Specifically, in the array substrate, the gate 102 is disposed on the base substrate 101 . A gate insulating layer 103 is disposed on the gate 102 and the base substrate 101 . The active layer 104 is disposed on the gate insulating layer 103 . The active layer 104 includes a source region, a channel region and a drain region. The source electrode 1081 is disposed in the source region on the active layer 104 . The drain 1082 is disposed in the drain region on the active layer 104 . The passivation layer 107 is disposed on the gate 102 , the gate insulating layer 103 , the active layer 104 , the source 1081 and the drain 1082 .

Please continue to refer to FIG. 1 , the active layer 104 includes a first active layer 1041 and a second active layer 1042 which are stacked. At this time, in the double-layer laminate structure of the active layer 104, the first active layer 1041 is close to the gate 102, and the second active layer 1042 is far away from the gate 102. The mobility of the first active layer 1041 should be higher than the second active layer 1042 . Referring to the selection of the rare earth elements doped to the active layer and the doping ratio, the mobility of the first active layer 1041 is higher than that of the second active layer 1042 . For example, the first active layer 1041 can use a rare earth metal oxide with high mobility, while the second active layer 1042 can use a rare earth metal oxide with relatively low mobility to realize the mobility of the first active layer 1041. The mobility is relatively higher than that of the second active layer 1042. In addition, the same oxide semiconductor may be used but with different doping ratios, so that the mobility of the first active layer 1041 is relatively higher than that of the second active layer 1042 .

In some embodiments of the present application, the array substrate of the present application may be an array substrate of an ESL structure. Please refer to FIG. 2, the array substrate includes: a gate 202, a gate insulating layer 203, an active layer 204, an etching stopper layer 205, a source 2081, a drain 2082, and a passivation layer arranged on a base substrate 201. 207.

Specifically, in the array substrate, the gate 202 is disposed on the base substrate 201 . A gate insulating layer 203 is disposed on the gate 202 and the base substrate 201 . The active layer 204 is disposed on the gate insulating layer 203; the active layer 204 includes a source region, a channel region and a drain region. The etch barrier layer 205 is disposed on the channel region, part of the source region and part of the drain region on the active layer 204 . The source electrode 2081 is disposed in the source region on the active layer 204 and is disposed on a part of the etching stopper layer. The drain electrode 2082 is disposed on the drain region on the active layer 204 , and is disposed on a part of the etching stopper layer 205 . The passivation layer 207 is disposed on the gate 202 , the gate insulating layer 203 , the active layer 204 , the source 2081 and the drain 2082 .

In the embodiment of the present application, the array substrate with an etch stop layer (ESL) structure can improve the stability of the oxide array substrate, and this structure can effectively reduce the influence of external environmental factors and etching damage of the source and drain electrodes on the back channel.

Please continue to refer to FIG. 2 , the active layer 204 includes a first active layer 2041 and a second active layer 2042 which are stacked. At this time, in the double-layer stack structure of the active layer 204, the first active layer 2041 is close to the gate 202, and the second active layer 2042 is far away from the gate 202. The mobility of the first active layer 2041 is higher than the second active layer 2042 . Similarly, the mobility difference in the double-layer stack structure can be achieved by selecting the rare earth elements doped in the active layer and the doping ratio to achieve higher mobility of the first active layer 2041 than that of the second active layer 2042. The purpose of mobility. For example, the first active layer 2041 can use a rare earth metal oxide with high mobility, and the second active layer 2042 can use a rare earth metal oxide with relatively low mobility to realize the mobility of the first active layer 2041. The mobility is relatively higher than that of the second active layer 2042. In addition, the same oxide semiconductor may be used but with different doping ratios, so that the mobility of the first active layer 2041 is relatively higher than that of the second active layer 2042 .

In some embodiments of the present application, the array substrate of the present application may be a Top-Gate array substrate. Referring to FIG. 3 , the array substrate includes: an active layer 304 disposed on a base substrate 301 , a gate insulating layer 305 , a gate 306 , a source 3081 , a drain 3082 , and a passivation layer.

Specifically, in the array substrate, an active layer 304 is disposed on the base substrate 301, and the active layer 304 includes a source region, a channel region and a drain region. The gate insulating layer 305 is disposed on the channel region of the active layer 304 . The gate 306 is disposed on the gate insulating layer 305 . The source electrode 3081 is disposed in the source region on the active layer 304 . The drain 3082 is disposed in the drain region on the active layer 304 . A passivation layer is disposed on the active layer 304 , the gate insulating layer 305 , the gate 306 , the source 3081 and the drain 3082 .

In this embodiment, please continue to refer to FIG. 3 , the active layer 304 includes a first active layer 3041 and a second active layer 3042 that are stacked. At this time, in the double-layer stack structure of the active layer 304, the first active layer 3041 is close to the gate 306, and the second active layer 3042 is far away from the gate 306. The mobility of the first active layer 3041 should be higher than the second active layer 3042 . For example, the first active layer 3041 can use a rare earth metal oxide with high mobility, while the second active layer 3042 can use a rare earth metal oxide with relatively low mobility, so that the mobility of the first active layer 3041 can be realized. The mobility is relatively higher than that of the second active layer 3042. In addition, the same oxide semiconductor may be used but with different doping ratios, so that the mobility of the first active layer 3041 is relatively higher than that of the second active layer 3042 .

Further, please continue to refer to FIG. 3 , the passivation layer includes a first passivation layer 307 and a second passivation layer 309 .

Further, please continue to refer to FIG. 3 , firstly, a metal layer 302 and an insulating layer 303 covering the metal layer 302 are disposed on the base substrate 301 . The above-mentioned active layer 304 , gate insulating layer 305 , gate 306 , source 3081 , drain 3082 , and passivation layer are sequentially disposed on the insulating layer 303 . Further, the passivation layer includes a first passivation layer 307 and a second passivation layer 309 .

The method for preparing an array substrate according to an embodiment of the present application includes: forming an oxide semiconductor layer by co-sputtering a rare earth metal oxide target and a metal oxide matrix target, wherein a semiconductor film with a corresponding doping ratio can be obtained by adjusting the process parameters, namely Make the active layer.

The process flows of the array substrates of the top gate type (Top Gate), ESL, and BCE structures in the embodiment of the present application are as follows.

In some embodiments, the process flow of the top gate (Top Gate) array substrate in the embodiment of the present application can be manufactured by conventional manufacturing processes in the field. For example, please refer to FIG. 3, the preparation process of the top-gate array substrate includes:

Substrate substrate 301: CVD (Chemical Vapor Deposition, chemical vapor deposition);

Metal layer 302: PVD (Physical Vapor Deposition, physical vapor deposition) → PH → WET (wet etching) → STR (ashing);

Insulating layer 303: CVD→PH→DET (dry etching)→STR;

Active layer 304: PVD→PH→DET→STR→Anneal (annealing);

Gate insulating layer 305: CVD→PH→DET→STR→Anneal;

Gate 306: PVD→PH→WET→STR;

The first passivation layer 307: CVD→PH→DET→STR;

Source 3081 and drain 3082: PVD→PH→WET→STR;

The second passivation layer 309: CVD→PH→DET→STR.

In some embodiments, the process flow of the array substrate of the ESL structure in the embodiment of the present application can be made by using conventional manufacturing processes in the field. For example, referring to FIG. 2, the manufacturing process of an array substrate with an ESL structure may include the following process flow:

Substrate substrate 201: CVD (Chemical Vapor Deposition);

Gate 202: PVD (physical vapor deposition) → PH → WET (wet etching) → STR (ashing);

Gate insulating layer 203: CVD→PH→DET (dry etching)→STR;

Active layer 204: PVD→PH→DET→STR→Anneal;

Etching barrier layer 205: CVD→PH→DET→STR→Anneal;

Source 2081 and drain 2082: PVD→PH→WET→STR;

Passivation layer 207: CVD→PH→DET→STR.

In some embodiments, the process flow of the array substrate of the BCE structure in the embodiment of the present application can be manufactured by conventional preparation processes in the field. For example, please refer to FIG. 1, the preparation process of the array substrate of the BCE structure may include the following process flow:

Substrate substrate 101: CVD (Chemical Vapor Deposition, chemical vapor deposition);

Gate 102: PVD (Physical Vapor Deposition, physical vapor deposition) → PH → WET (wet etching) → STR (ashing);

Gate insulating layer 103: CVD→PH→DET (dry etching)→STR;

Active layer 104: PVD→PH→DET→STR→Anneal (annealing);

Source 1081 and drain 1082: PVD→PH→WET→STR;

Passivation layer 107: CVD→PH→DET→STR→Anneal.

An embodiment of the present application further provides a display panel, which includes the above-mentioned array substrate. The display panel also includes conventional structures such as a touch control structure and a packaging structure. Examples of suitable display panels include, but are not limited to: LCD, OLED, Micro LED.

The present application has carried out several tests successively, and a part of the test results are given as a reference to further describe the invention in detail, and will be described in detail below in conjunction with specific examples.

Example 1~4

Embodiments 1 to 4 provide an array substrate with a Top-Gate structure, please refer to FIG. pole 3082, passivation layer. The active layer 304 includes a first active layer 3041 and a second active layer 3042 which are stacked. The first active layer and the second active layer respectively include an oxide semiconductor (indium zinc oxide) and a rare earth metal oxide. The mobility of the first active layer is higher than that of the second active layer.

In Examples 1-4, the rare earth metal oxides in the first active layer and the second active layer are doped with the same element in different proportions.

Specifically, when the first active layer and the second active layer are doped with the same rare earth element but in different proportions, please refer to FIG. 4 for the rare earth element and doping molar ratio. In Examples 1 to 4, the array substrate of the Top-Gate structure obtained by the parameters in Figure 4 is used to detect device characteristics, such as threshold voltage, mobility, sub-threshold swing, switching current ratio, PBTS, and NBTIS. For the test results, see Figure 4 shows.

Embodiment 5~8

Embodiments 5 to 8 provide an array substrate of a Top-Gate structure, please refer to FIG. pole 3082, passivation layer. The active layer 304 includes a first active layer 3041 and a second active layer 3042 which are stacked. The first active layer and the second active layer respectively include an oxide semiconductor (indium zinc oxide) and a rare earth metal oxide. The mobility of the first active layer is higher than that of the second active layer.

In Examples 5-8, the rare earth metal oxides in the first active layer and the second active layer are doped with different elements in different proportions.

Specifically, when the first active layer and the second active layer are doped with different rare earth elements and in different proportions (relatively high transition doping + relatively low transition element doping), please refer to the rare earth element and doping molar ratio for details. As shown in FIG. 7 , the first active layer is doped with relatively high-mobility elements, and the second active layer is doped with relatively low-mobility elements. In Examples 5 to 8, the array substrate of the Top-Gate structure obtained by the parameters in Figure 7 is used to detect device characteristics, such as threshold voltage, mobility, sub-threshold swing, on-off current ratio, PBTS, and NBTIS, and the test results are shown in Figure 7. shown.

Embodiment 9~12

Embodiments 9 to 12 provide an array substrate of an ESL structure, please refer to FIG. pole 2081, drain 2082, and passivation layer 207. The active layer 204 includes a first active layer 2041 and a second active layer 2042 which are stacked. The first active layer and the second active layer respectively include an oxide semiconductor (indium zinc oxide) and a rare earth metal oxide.

In Examples 9-12, the rare earth metal oxides in the first active layer and the second active layer are doped with the same element in different proportions.

Specifically, when the first active layer and the second active layer are doped with the same rare earth element but in different proportions, the rare earth element and doping molar ratio are shown in FIG. 5 in detail. In Examples 9 to 12, the array substrate of the ESL structure obtained by the parameters in Figure 5 is used to detect device characteristics, such as threshold voltage, mobility, sub-threshold swing, switch current ratio, PBTS, and NBTIS. The test results are shown in Figure 5. .

Example 13~16

Embodiments 13 to 16 provide an array substrate of an ESL structure, please refer to FIG. pole 2081, drain 2082, and passivation layer 207. The active layer 204 includes a first active layer 2041 and a second active layer 2042 which are stacked. The first active layer and the second active layer respectively include an oxide semiconductor (indium zinc oxide) and a rare earth metal oxide.

In Examples 13-16, the rare earth metal oxides in the first active layer and the second active layer are doped with different elements in different proportions.

Specifically, when the first active layer and the second active layer are doped with different rare earth elements and in different proportions, the rare earth elements and doping molar ratios are shown in Figure 8, wherein the first active layer is Elements with relatively high mobility are doped, and the second active layer is doped with elements with relatively low mobility. In Examples 13 to 16, the array substrate of the ESL structure obtained by the parameters in Figure 8 is used to detect device characteristics, such as threshold voltage, mobility, sub-threshold swing, switch current ratio, PBTS, and NBTIS. The test results are shown in Figure 8. .

Example 17~20

Embodiments 17-20 provide an array substrate with a BCE structure, please refer to FIG. 1 , including: a gate 102, a gate insulating layer 103, an active layer 104, a source 1081, and a drain 1082 arranged on a base substrate 101. , Passivation layer 107 . The active layer 104 includes a first active layer 1041 and a second active layer 1042 which are stacked. The first active layer and the second active layer respectively include an oxide semiconductor (indium zinc oxide) and a rare earth metal oxide.

In Examples 17-20, the rare earth metal oxides in the first active layer and the second active layer are doped with the same element in different proportions.

Specifically, when the first active layer and the second active layer are doped with the same rare earth element but in different proportions, the rare earth element and doping molar ratio are shown in FIG. 6 in detail. For the array substrates of the BCE structure obtained in Examples 17 to 20 using the parameters in Figure 6, the device characteristics are tested, such as threshold voltage, mobility, sub-threshold swing, switch current ratio, PBTS, and NBTIS. The test results are shown in Figure 6. .

Examples 21~24

Embodiments 21 to 24 provide an array substrate with a BCE structure, please refer to FIG. 1 , including: a gate 102, a gate insulating layer 103, an active layer 104, a source 1081, and a drain 1082 arranged on a base substrate 101. , Passivation layer 107 . The active layer 104 includes a first active layer 1041 and a second active layer 1042 which are stacked. The first active layer and the second active layer respectively include an oxide semiconductor (indium zinc oxide) and a rare earth metal oxide.

In Examples 21-24, the rare earth metal oxides in the first active layer and the second active layer are doped with different elements in different proportions.

Specifically, when the first active layer and the second active layer are doped with different rare earth elements and in different proportions, the rare earth elements and doping molar ratios are shown in Figure 9, wherein the first active layer is Elements with relatively high mobility are doped, and the second active layer is doped with elements with relatively low mobility. For the array substrates of the BCE structure obtained in Examples 21 to 24 using the parameters in Figure 9, the device characteristics are tested, such as threshold voltage, mobility, sub-threshold swing, switch current ratio, PBTS, and NBTIS. The test results are shown in Figure 9. .

In summary, according to Fig. 4, Fig. 5, and Fig. 6, it can be seen that the array substrates in Examples 1-4, 9-12, 17-20 of the present application use the same elements for the first active layer and the second active layer (Tb) and in combination with smaller doping moles in the first active layer to achieve a mobility differential.

According to Fig. 7, Fig. 8 and Fig. 9, it can be known that in the array substrates in Examples 5-8, 13-16, 21-24 of the present application, the first active layer and the second active layer use different elements (the first The active layer is doped with terbium element, the second active layer is doped with ytterbium element), and the combined doping mole makes the relative mobility of the first active layer high.

4-6 and 7-9, it can be seen that the device characteristics of the array substrate of the embodiment of the present application are excellent. For example, in Example 1, the threshold voltage can reach -0.5V, the mobility μ can reach 32.9cm ² V ^-1 s ^-1 , the subthreshold swing can be 0.3 V/decade, and the on-off current ratio is about 8×106, PBTS can reach 0.42V, and NBTIS can reach -1.21V; for example, in Example 5, the threshold voltage can reach 0V, the mobility μ can reach 30.7cm ² V ^-1 s ^-1 , and the subthreshold swing can be 0.3V/decade , The switch current ratio is about 5×106, PBTS can reach 0.55V, NBTIS can reach -1.03V, etc. It can be seen that the array substrate obtained in the embodiment of the present application has excellent device characteristics, and can further increase the performance of the display panel to which it is applied.

In summary, this application forms a film with relatively high mobility and relatively high on-state current on the front channel side by co-doping oxide semiconductor laminated films with a specific molar ratio, which can increase the on-state current; Forming a thin film with low mobility and relatively low off-state current on the back channel side can reduce the off-state current.

In the foregoing embodiments, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments.

The above is a detailed introduction to an array substrate and a display panel provided by the embodiments of the present application. In this paper, specific examples are used to illustrate the principles and implementation methods of the present application. The descriptions of the above embodiments are only used to help understand the present application. method and its core idea; at the same time, for those skilled in the art, according to the idea of this application, there will be changes in the specific implementation and application scope. Application Restrictions.

Claims (10)

1. An array substrate, comprising:

the grid electrode, the grid insulating layer and the active layer are arranged on the substrate base plate;

the active layer comprises a first active layer and a second active layer which are arranged in a stacked mode; the first active layer is arranged close to the grid electrode, and the second active layer is positioned on one side of the first active layer, which is far away from the grid electrode;

the mobility of the first active layer is higher than the mobility of the second active layer.

2. The array substrate of claim 1, wherein the material of the active layer comprises an oxide semiconductor and a rare earth metal oxide, the oxide semiconductor comprises one or more of indium gallium zinc oxide, indium gallium tin oxide, indium gallium oxide, indium oxide and indium zinc oxide, and the rare earth element in the rare earth metal oxide comprises one or more of samarium, terbium, dysprosium, europium, erbium, tin, lanthanum, cerium, ytterbium and praseodymium.

3. The array substrate of claim 2, wherein the rare earth element in the first active layer comprises one or more of samarium, terbium, dysprosium, europium, erbium, and tin;

the doping ratio of the rare earth metal oxide in the first active layer is 0.001-0.1.

4. The array substrate of claim 2 or 3, wherein the rare earth elements in the second active layer comprise one or more of lanthanum, terbium, dysprosium, cerium, erbium, ytterbium and praseodymium, and the doping ratio of the rare earth metal oxide in the second active layer is 0.1-0.3.

5. The array substrate according to claim 2 or 3, wherein the doping ratio of the rare earth oxide in the second active layer is the same as the doping ratio of the rare earth oxide in the first active layer, and the mobility of the rare earth element in the second active layer is lower than the mobility of the rare earth element in the first active layer.

6. The array substrate of claim 2 or 3, wherein the rare earth element in the second active layer is the same as the rare earth element in the first active layer, and the doping ratio of the rare earth metal oxide in the second active layer is 0.15-0.3.

7. The array substrate of claim 1, wherein the array substrate comprises:

a substrate base plate;

a second active layer disposed on the substrate base plate;

a first active layer disposed on the second active layer, the first active layer including a source region, a channel region, and a drain region;

a gate insulating layer disposed on the channel region on the first active layer;

a gate electrode disposed on the gate insulating layer;

a source electrode disposed on the first active layer;

a drain electrode disposed on the first active layer;

and a passivation layer disposed on the second active layer, the first active layer, the gate insulating layer, the gate electrode, the source electrode, and the drain electrode.

8. The array substrate of claim 1, wherein the array substrate comprises:

a base substrate;

a gate electrode disposed on the substrate base plate;

the grid insulating layer is arranged on the grid and the substrate base plate;

a first active layer disposed on the gate insulating layer;

a second active layer disposed on the first active layer; the second active layer comprises a source region, a channel region and a drain region;

a source electrode disposed on the second active layer;

a drain electrode disposed on the second active layer;

and a passivation layer disposed on the gate electrode, the gate insulating layer, the first active layer, the second active layer, the source electrode, and the drain electrode.

9. The array substrate of claim 8, wherein the array substrate further comprises an etch stop layer;

the etching barrier layer is arranged between the second active layer and the source electrode and the drain electrode; the etching barrier layer is arranged on the channel region on the second active layer, and part of the source region and part of the drain region.

10. A display panel comprising the array substrate according to any one of claims 1 to 9.

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