CN115295483B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, comprising the following steps: providing a substrate, wherein a dielectric layer is formed on the substrate; forming a first opening penetrating through the dielectric layer and exposing the substrate; forming a protective layer, wherein the protective layer at least covers the side wall of the first opening and the surface of the dielectric layer, and performing a heat treatment process to densify the protective layer; and etching the substrate under the first opening by using the densified protective layer as a mask to form a second opening, wherein the side wall of the first opening and the surface of the dielectric layer still keep the protective layer with partial thickness. The first opening and the second opening form a through silicon via. When the second opening is formed, the protective layer is formed on the side wall of the first opening, so that the dielectric layer positioned on the side wall of the first opening is prevented from being damaged by etching in the etching process for forming the second opening, and the roughness of the side wall is reduced; meanwhile, the protective layer also plays a role in protecting and buffering, so that the side wall of the etched silicon through hole is uniform and smooth, and the performance of the semiconductor device is improved.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a semiconductor device and a manufacturing method thereof.

Background Art

Through Silicon Via (TSV) is the latest technology to interconnect chips by making vertical connections between chips and wafers. Different from the previous IC packaging bonding and stacking technology using bumps, TSV can make chips stacked in three dimensions with higher density and smaller size, and greatly improve chip speed and power consumption.

There are many ways to integrate the TSV process, but they all face the same problem. The TSV process needs to break through (penetrate) different material layers, such as silicon layers, various insulating layers or conductive layers in ICs. TSV technology needs to meet profile control. As the size of TSV decreases, the sidewall roughness of the silicon via needs to be controlled very small. In actual processes, the inter-metal dielectric (IMD) layer of the Low-k (low dielectric constant) material in the wafer is easily etched and damaged during the silicon via etching process, which in turn affects the performance of semiconductor devices.

Summary of the invention

The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, so as to avoid damage during TSV etching, reduce the roughness of the TSV sidewall, and improve the performance and yield of the semiconductor device.

The present invention provides a method for manufacturing a semiconductor device, comprising:

Providing a substrate, on which a dielectric layer is formed;

forming a first opening, wherein the first opening penetrates the dielectric layer and exposes the substrate;

forming a protective layer, the protective layer at least covering the sidewall of the first opening and the surface of the dielectric layer, and performing a heat treatment process to densify the protective layer;

The substrate under the first opening is etched using the densified protective layer as a mask to form a second opening, and a partial thickness of the protective layer is still retained on the sidewall of the first opening and the surface of the dielectric layer.

Furthermore, a metal layer is embedded in the dielectric layer, and the reserved portion of the protective layer is in contact with and covers the metal layer.

Furthermore, the material of the protection layer includes at least one of SiO ₂ , SiON, SiBCN, and SiCN.

Furthermore, the protective layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

Furthermore, in the atomic layer deposition process, the protective layer is formed by repeatedly performing a cycle of alternately providing a silicon source gas and an oxygen source gas to the reaction chamber, wherein the silicon source gas is selected from a silicon chloride compound, and the oxygen source gas is selected from water or hydrogen peroxide.

Furthermore, a conductive film layer is formed between the substrate and the dielectric layer, and/or on the surface of the dielectric layer, and when the first opening is formed, the first opening also penetrates the conductive film layer.

Furthermore, the conductive film layer includes a stacked structure in which low-k dielectric layers and metal layers are alternately stacked in sequence, and the dielectric constant of the low-k dielectric layer is less than or equal to 3.5.

Furthermore, the low-k dielectric layer includes at least one of a silicon nitride layer, a silicon oxide layer, a nitrogen-doped silicon carbide layer, a carbon-doped silicon oxide layer and a polyimide film.

Furthermore, after forming the second opening, the method further includes:

An interconnection layer is formed, wherein the interconnection layer fills the first opening and the second opening to form a through silicon via; the material of the interconnection layer includes at least one of aluminum, copper, tungsten and cobalt.

The present invention also provides a semiconductor device, comprising:

A substrate, wherein a dielectric layer is formed on the substrate, and a metal layer is embedded in the dielectric layer;

a first opening, wherein the first opening penetrates the dielectric layer;

a densified protective layer, the densified protective layer at least covering the sidewall of the first opening and the surface of the dielectric layer, and contacting with and covering the metal layer;

A second opening is located in the base directly below the first opening, and the second opening extends along the first opening to the inside of the base in the thickness direction of the base;

An interconnection layer fills the first opening and the second opening to form a through silicon via, wherein the densified protection layer is formed between the interconnection layer and the dielectric layer at the location of the first opening.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention provides a semiconductor device and a method for manufacturing the same, comprising: providing a substrate, on which a dielectric layer is formed; forming a first opening, the first opening penetrating the dielectric layer and exposing the substrate; forming a protective layer, the protective layer at least covering the sidewall of the first opening and the surface of the dielectric layer, and performing a heat treatment process to densify the protective layer; etching the substrate under the first opening using the densified protective layer as a mask to form a second opening, the sidewall of the first opening and the surface of the dielectric layer still retaining a portion of the thickness of the protective layer. The first opening and the second opening constitute a through silicon via. When the present invention forms the second opening, since the protective layer is formed on the sidewall of the first opening, the dielectric layer located on the sidewall of the first opening is prevented from being etched and damaged in the etching process of forming the second opening, thereby reducing the roughness of the sidewall; at the same time, the protective layer also plays a protective buffer role, so that the sidewall of the through silicon via after etching is uniform and smooth, thereby improving the performance of the semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention after providing a substrate.

FIG. 3 is a schematic diagram of a semiconductor device manufacturing method after a first opening is formed according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a semiconductor device manufacturing method after a protection layer is formed according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a semiconductor device manufacturing method after a second opening is formed according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention after an interconnection layer is formed.

FIG. 7 is a schematic diagram showing a method for manufacturing a semiconductor device in which a dielectric layer is damaged during TSV etching.

FIG. 8 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention in which a protective layer is provided to prevent damage to a dielectric layer.

The reference numerals are as follows:

10 - substrate; A - conductive film layer; 11 - dielectric layer; 12 - metal layer; 13 - protective layer; 14 - interconnection layer; V ₁ - first opening; V ₂ - second opening.

DETAILED DESCRIPTION

Based on the above research, an embodiment of the present invention provides a semiconductor device and a method for manufacturing the same. The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

An embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in FIG1 , comprising:

Step S1, providing a substrate, wherein a dielectric layer is formed on the substrate;

Step S2, forming a first opening, wherein the first opening penetrates the dielectric layer and exposes the substrate;

Step S3, forming a protection layer, the protection layer at least covering the sidewall of the first opening and the surface of the dielectric layer, and performing a heat treatment process to densify the protection layer;

Step S4, using the densified protective layer as a mask to etch the substrate under the first opening to form a second opening, and a partial thickness of the protective layer is still retained on the sidewall of the first opening and the surface of the dielectric layer.

The steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail below with reference to FIGS. 2 to 8 .

As shown in FIG2 , a substrate 10 is provided, on which a dielectric layer 11 is formed, and a metal layer 12 is embedded in the dielectric layer 11. Exemplarily, the upper surface of the dielectric layer 11 is flush with the upper surface of the metal layer 12. The substrate 10 may include semiconductor materials such as silicon, germanium, silicon-germanium, etc., or III-V semiconductor compounds such as GaP, GaAs, GaSb, etc. In some embodiments, the substrate 10 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In addition, although not shown, the substrate 10 may include a conductive pattern, which may be a metal line, a contact, a conductive pad, etc., and may be a gate electrode of a transistor, a source/drain of a transistor, or a diode, but the embodiment is not limited thereto. The material of the metal layer 12 includes at least one of aluminum, copper, tungsten and cobalt.

In one example, the dielectric layer 11 includes silicon oxide. In another example, the dielectric layer 11 may include silicon oxide containing carbon and hydrogen (SiCOH); for example, the dielectric layer may include about 10% to about 50% carbon. In yet another example, the dielectric layer may include fluorine-containing silicon oxide (F-SiO ₂ ) and/or porous silicon oxide, etc.

A conductive film layer A is formed between the substrate 10 and the dielectric layer 11, and/or on the surface of the dielectric layer 11. When the first opening is subsequently formed, the first opening also penetrates the conductive film layer A. The conductive film layer A includes a stacked structure in which low-k dielectric layers and metal layers are alternately stacked in sequence, and adjacent metal layers are isolated by low-k dielectric layers, and the dielectric constant of the low-k dielectric layer is less than or equal to 3.5. The low-k dielectric layer may have a dielectric constant of 2.0 to 3.5, for example. Low-k (low dielectric constant) materials can produce lower capacitance values due to their inherent low dielectric constants, and are therefore widely used in the field of semiconductor manufacturing, such as as dielectric layer materials filled between metal layers (including interconnects and through holes). The low-k dielectric layer may include at least one of a silicon nitride layer, a silicon oxide layer, a nitrogen-doped silicon carbide layer (NDC), a carbon-doped silicon oxide, and a polyimide film. The material of the metal layer may include at least one of copper, aluminum, and tungsten.

As shown in Fig. 3, a first opening _V1 is formed, and the first opening _V1 penetrates the dielectric layer 11 and exposes the substrate 10. Exemplarily, a metal layer 12 is embedded in the dielectric layer 11 around the first opening _V1 .

As shown in FIG4 , a protective layer 13 is formed, and the protective layer 13 at least covers the sidewall of the first opening _V1 and the surface of the dielectric layer 11, and a heat treatment process is performed to densify the protective layer 13. The protective layer 13 also covers the bottom surface of the first opening _V1 (the surface of the substrate 10 exposed by the first opening _V1 ). The protective layer 13 can be formed by an atomic layer deposition process or a chemical vapor deposition process. The material of the protective layer includes: at least one of SiO ₂ , SiON, SiBCN, and SiCN. In a specific example, the material of the protective layer is an oxide layer, and the protective layer 13 can be deposited by an atomic layer deposition method. The atomic layer deposition process has good gap filling performance and step coverage, and correspondingly improves the conformal coverage ability of the protective layer. The protective layer can be formed by repeatedly performing a cycle of alternately providing a silicon source gas and an oxygen source gas to a reaction chamber, and the silicon source gas is selected from a silicon chloride (SixCly) compound, where x representing the silicon atomic ratio is between 1 and 4, and y representing the chloride atomic ratio is between 1 and 8. The protective layer 13 is formed by repeatedly supplying a silicon source gas selected from silicon tetrachloride (SiCl 4 ) and disilicon hexachloride (Si ₂ Cl ₆ ) and an oxygen source gas such as water (H ₂ O) and hydrogen peroxide (H ₂ O ₂ ) to the reaction _chamber . The protective layer 13 is preferably deposited at a temperature between 20°C and 400°C.

After the protective layer 13 is deposited, a heat treatment process is performed to densify the protective layer 13. The heat treatment is performed at a temperature of 500° C. to 1200° C. for more than 5 minutes in an atmosphere selected from a gas group consisting of a mixed gas of hydrogen (H ₂ ), oxygen (O ₂ ), nitrogen (N ₂ ), ozone (O ₃ ) and nitrous oxide (N ₂ O). The heat treatment may be performed by a rapid thermal process (RTP) at a temperature greater than 600° C. for more than 5 seconds.

As shown in FIG5 , the densified protective layer 13 is used as a mask to etch a portion of the thickness of the substrate 10 below the first opening V ₁ to form a second opening V ₂ , and a portion of the thickness of the protective layer 13 is still retained on the sidewall of the first opening V ₁ and the surface of the dielectric layer 11. Specifically, the second opening V ₂ penetrates the protective layer 13 at the bottom of the first opening V ₁ and a portion of the thickness of the substrate 10 directly below it, and extends the first opening along the thickness direction of the substrate 10 to the inside of the substrate 10. The first opening V ₁ and the second opening V ₂ constitute a through silicon via (TSV). The second opening V ₂ can be formed by a dry etching process.

Next, as shown in FIG6 , a metal barrier layer (not shown) and an interconnection layer 14 may be deposited in the through silicon via using a conventional damascene process. A metal barrier layer may be formed on the sidewall and bottom surface of the through silicon via, and the metal barrier layer may include, for example, titanium, titanium nitride, tantalum, and tantalum nitride. The interconnection layer 14 covers the metal barrier layer and fills the through silicon via, that is, the side and bottom of the interconnection layer are wrapped by the metal barrier layer. The material of the interconnection layer 14 includes at least one of aluminum, copper, tungsten, and cobalt.

In the TSV process, due to the complexity of the types of film layers to be penetrated by the through silicon via, it is difficult to select the process parameters, and it is difficult to cover the best etching parameters for each film layer. The TSV etching is selected in two steps, first the dielectric layer 11 is etched, and then the substrate 10 is etched. When the process parameters of the dielectric layer 11 are adjusted, the etched dielectric layer 11 will be deteriorated when the substrate 10 is etched, and the roughness of the dielectric layer 11 will increase, especially when there is a conductive film layer A, the conductive film layer A will be damaged (as shown in the oval in Figure 7). In addition, after the first opening _V1 is formed, the second opening _V2 is formed immediately. In the process of etching the substrate 10 of the second opening _V2 , the dielectric layer 11 on the side wall of the first opening _V1 will be etched together, that is, the dielectric layer 11 on the side wall of the _first opening V1 is damaged, causing the first opening _V1 to expand outward to the periphery and even expose the metal layer 12.

In the embodiment of the present invention, when the second opening _V2 is formed, since the protective layer 13 is formed on the side wall of the first opening _V1 , the dielectric layer 11 located on the side wall of the first opening _V1 is prevented from being etched and damaged in the etching process of forming the second opening _V2 , and the roughness of the side wall of the through silicon via is reduced; at the same time, the protective layer 13 also plays a protective buffer role, so that the side wall after TSV etching is uniform and smooth (as shown in the ellipse of Figure 8), thereby improving the performance and yield rate of the semiconductor device. At the same time, the protective layer 13 of a certain thickness is still retained on the surface of the dielectric layer 11, so that the metal layer 12 in the dielectric layer 11 is prevented from being etched and damaged in the etching process of forming the second opening _V2 . Further, when a conductive film layer A is formed between the substrate 10 and the dielectric layer 11, and/or on the surface of the dielectric layer 11, when the first opening _V1 is formed, the first opening _V1 also penetrates the conductive film layer A. The protection layer 13 also covers the sidewalls of the conductive film layer A exposed by the first opening, thereby preventing the conductive film layer A located on the sidewalls of the first opening _V1 from being etched and damaged during the etching process of forming the second opening _V2 , thereby reducing the roughness of the sidewalls of the through silicon via.

The present invention uses the densified protective layer 13 as a mask to etch the substrate under the first opening to form a second opening. The sidewall of the first opening and the surface of the dielectric layer still retain a partial thickness of the protective layer. The retained partial thickness of the protective layer can be retained as a part of the device. On the one hand, it can protect the sidewall of the first opening and can be used as a functional layer to cover the metal layer 12 embedded in the dielectric layer. On the other hand, no additional process is required to remove the protective layer to avoid secondary damage to the sidewall of the first opening, the substrate surface of the second opening, and the metal layer 12 embedded in the dielectric layer 11 during the removal process.

An embodiment of the present invention further provides a semiconductor device, as shown in FIG6 , comprising:

A substrate 10, wherein a dielectric layer 11 is formed on the substrate 10, and a metal layer 12 is embedded in the dielectric layer 11;

A first opening, wherein the first opening penetrates the dielectric layer 11;

a densified protective layer 13, wherein the densified protective layer 13 at least covers the sidewall of the first opening and the surface of the dielectric layer 11, and is in contact with and covers the metal layer 12;

A second opening is located in the base 10 directly below the first opening, and the second opening extends along the first opening to the inside of the base 10 in the thickness direction of the base 10;

An interconnection layer 14 is provided, wherein the interconnection layer 14 fills the first opening and the second opening to form a through silicon via, wherein the densified protection layer 13 is formed between the interconnection layer 14 and the dielectric layer 11 at the location of the first opening.

Specifically, the material of the interconnection layer 14 includes at least one of aluminum, copper, tungsten and cobalt. A conductive film layer A may be formed between the substrate 10 and the dielectric layer 11, and/or on the surface of the dielectric layer 11, and the first opening _V1 penetrates the conductive film layer A. The protective layer 13 also covers the sidewalls of the conductive film layer A exposed by the first opening.

In summary, the present invention provides a semiconductor device and a method for manufacturing the same, including: providing a substrate, on which a dielectric layer is formed; forming a first opening, the first opening penetrating the dielectric layer and exposing the substrate; forming a protective layer, the protective layer at least covering the sidewalls of the first opening and the surface of the dielectric layer, and performing a heat treatment process to densify the protective layer; using the densified protective layer as a mask to etch the substrate under the first opening to form a second opening, the sidewalls of the first opening and the surface of the dielectric layer still retain a portion of the thickness of the protective layer. The first opening and the second opening constitute a through silicon via. When the present invention forms the second opening, since the protective layer is formed on the sidewalls of the first opening, the dielectric layer located on the sidewalls of the first opening is prevented from being etched and damaged in the etching process of forming the second opening, thereby reducing the roughness of the sidewalls; at the same time, the protective layer also plays a protective buffer role, so that the sidewalls of the through silicon via after etching are uniform and smooth, thereby improving the performance of the semiconductor device.

In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims (9)

1. A method of fabricating a semiconductor device, comprising:

Providing a substrate, wherein a dielectric layer is formed on the substrate, a conductive film layer is formed between the substrate and the dielectric layer and/or on the upper surface of the dielectric layer, and the conductive film layer comprises a stacked structure of low-k dielectric layers and metal layers which are alternately stacked in sequence;

forming a first opening, wherein the first opening penetrates through the dielectric layer, the conductive film layer and the substrate;

Forming a protective layer, wherein the protective layer covers at least the side wall of the first opening, the protective layer also covers the side wall of the conductive film layer exposed by the first opening, when the conductive film layer is formed between the substrate and the dielectric layer, the protective layer also covers the upper surface of the dielectric layer, and when the conductive film layer is formed on the upper surface of the dielectric layer, the protective layer also covers the upper surface of the conductive film layer on the upper surface of the dielectric layer; and performing a heat treatment process to densify the protective layer;

Etching the substrate under the first opening to form a second opening by taking the densified protective layer as a mask, wherein the side wall of the first opening still keeps a part of the protective layer; when the conductive film layer is formed between the substrate and the dielectric layer, the protective layer with partial thickness still remains on the upper surface of the dielectric layer, and when the conductive film layer is formed on the upper surface of the dielectric layer, the protective layer with partial thickness remains on the upper surface of the conductive film layer on the upper surface of the dielectric layer.

2. The method of manufacturing a semiconductor device according to claim 1, wherein a metal layer is embedded in the dielectric layer, and the protective layer is in contact with and covers the metal layer at a certain thickness.

3. The method of manufacturing a semiconductor device according to claim 1, wherein the material of the protective layer comprises: at least one of SiO ₂, siON, siBCN, siCN.

4. The method of manufacturing a semiconductor device according to claim 1, wherein the protective layer is formed using an atomic layer deposition process or a chemical vapor deposition process.

5. The method of manufacturing a semiconductor device according to claim 4, wherein the protective layer is formed by repeatedly performing a cycle of alternately supplying a silicon source gas selected from a silicon chloride compound and an oxygen source gas selected from water or hydrogen peroxide to the reaction chamber in the atomic layer deposition process.

6. The method of manufacturing a semiconductor device according to claim 1, wherein a dielectric constant of the low-k dielectric layer is 3.5 or less.

7. The method of manufacturing a semiconductor device according to claim 6, wherein the low-k dielectric layer comprises at least one of a silicon nitride layer, a silicon oxide layer, a nitrogen-doped silicon carbide layer, a carbon-doped silicon oxide, and a polyimide film.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, further comprising, after forming the second opening:

Forming an interconnection layer, wherein the interconnection layer fills the first opening and the second opening to form a through silicon via; the material of the interconnection layer comprises at least one of aluminum, copper, tungsten and cobalt.

9. A semiconductor device, comprising:

the substrate is provided with a dielectric layer, and a metal layer is embedded in the dielectric layer; a conductive film layer is formed between the substrate and the dielectric layer and/or on the upper surface of the dielectric layer, and the conductive film layer comprises a stacked structure of low-k dielectric layers and metal layers which are alternately stacked in sequence;

A first opening penetrating the dielectric layer and the conductive thin film layer;

A densified protective layer covering at least the sidewalls of the first opening, the densified protective layer also covering the sidewalls of the conductive film layer exposed by the first opening; when the conductive film layer is formed between the substrate and the dielectric layer, the densified protective layer also covers the upper surface of the dielectric layer, and the densified protective layer is in contact with and covers the metal layer; when the conductive film layer is formed on the upper surface of the dielectric layer, the densified protective layer also covers the upper surface of the conductive film layer on the upper surface of the dielectric layer, and the conductive film layer is in contact with the metal layer and covers the metal layer;

A second opening located in the substrate directly below the first opening, the second opening being formed by following the first opening into the substrate in the thickness direction of the substrate;

And the interconnection layer fills the first opening and the second opening to form a silicon through hole, wherein the densified protection layer is formed between the interconnection layer at the position of the first opening and the dielectric layer and between the interconnection layer and the conductive film layer.